Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements Storage elements therefor

GPHYSICS G11Information storage G11CSTATIC STORES

G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements Storage elements therefor

G11C2211/401Indexing scheme relating to cells needing refreshing or charge regeneration G11C2211/4013Memory devices with multiple cells per bit G11C2211/4016Memory devices with silicon-on-insulator cells G11C2211/406Refreshing of dynamic cells G11C2211/4061Calibration or ate or cycle tuning G11C2211/4062Parity or ECC in refresh operations G11C2211/4063Interleaved refresh operations G11C2211/4065Low level details of refresh operations G11C2211/4066Pseudo-SRAMs G11C2211/4067Refresh in standby or low power modes G11C2211/4068Voltage or leakage in refresh operations G11C2211/56Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups G11C2211/561Multilevel memory cell aspects G11C2211/5611Multilevel memory cell with more than one control gate G11C2211/5612Multilevel memory cell with more than one floating gate G11C2211/5613Multilevel memory cell with additional gates, not being floating or control gates G11C2211/5614Multilevel memory cell comprising negative resistance, quantum tunneling or resonance tunneling elements G11C2211/5615Multilevel magnetic memory cell using non-magnetic non-conducting interlayer G11C2211/5616Multilevel magnetic memory cell using non-magnetic conducting interlayer G11C2211/5617Multilevel ROM cell programmed by source, drain or gate contacting G11C2211/562Multilevel memory programming aspects G11C2211/5621Multilevel programming verification G11C2211/5622Concurrent multilevel programming of more than one cell G11C2211/5623Concurrent multilevel programming and reading G11C2211/5624Concurrent multilevel programming and programming verification G11C2211/5625Self-converging multilevel programming G11C2211/563Multilevel memory reading aspects G11C2211/5631Concurrent multilevel reading of more than one cell G11C2211/5632Multilevel reading using successive approximation G11C2211/5633Mixed concurrent serial multilevel reading G11C2211/5634Reference cells G11C2211/564Miscellaneous aspects G11C2211/5641Multilevel memory having cells with different number of storage levels G11C2211/5642Multilevel memory with buffers, latches, registers at input or output G11C2211/5643Multilevel memory comprising cache storage devices G11C2211/5644Multilevel memory comprising counting devices G11C2211/5645Multilevel memory with current-mirror arrangements G11C2211/5646Multilevel memory with flag bits G11C2211/5647Multilevel memory with bit inversion arrangement G11C2211/5648Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant G11C2211/5649Multilevel memory with plate line or layer G11C2211/565Multilevel memory comprising elements in triple well structure