Patent Application
20240429111
This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0079770, filed on Jun. 21, 2023, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.
The inventive concepts relate to a semiconductor memory module, and more particularly, relate to a semiconductor memory module having improved reliability.
Many electronic systems include semiconductor memory modules, such as solid state drives (SSDs), dual in-line memory modules (DIMMs), and small outline-DIMMs, all of which utilize memory cells to store data as an electrical charge or voltage. Improvements in storage density of these modules have been brought about by increasing the density of the memory cells on each individual memory component using enhanced manufacturing techniques. Additionally, the storage density of these modules has also been increased by including more memory components in each memory device or module using advanced board-level packaging techniques.
An object of the inventive concepts is to provide a semiconductor memory module with improved reliability.
The benefits provided by the inventive concepts are not limited to addressing the problems mentioned above, and other benefits not mentioned will be clearly understood by those skilled in the art from the description below.
A semiconductor memory module according to some embodiments of the inventive concepts includes a first substrate including a first corner, first semiconductor packages mounted on a lower surface of the first substrate, a second substrate disposed over the first substrate and including a second corner corresponding to the first corner, second semiconductor packages mounted on an upper surface of the second substrate, and a fixing structure into which the first corner and the second corner are fitted.
A semiconductor memory module according to some embodiments of the inventive concepts includes a case and a stacked structure housed therein, wherein the stacked structure includes a first substrate including a plurality of first corners and having a first side surface and a second side surface, first semiconductor packages mounted on a lower surface of the first substrate, second semiconductor packages mounted on an upper surface of the first substrate, a second substrate disposed over the first substrate, including a plurality of second corners with each second corner respectively corresponding to a respective first corner, and having a third side surface and a fourth side surface, third semiconductor packages mounted on an upper surface of the second substrate, a plurality of fixing structures in which corresponding pairs of the first corners and the second corners are fitted in a respective fixing structure of the plurality of fixing structures, a frame interposed between the first substrate and the second substrate, at least one flexible connector connecting the second side surface and the fourth side surface, and at least one capacitor connected to the first side surface, wherein a length, width or height of each of the fixing structures is in a range from 0.1 mm to 200 mm, wherein at least one fixing structure of the plurality of fixing structures includes a first slot into which one of the first corners is fitted and a second slot in which one of the second corners is fitted, and wherein the distance between the first slot and the second slot is in a range from 0.1 mm to 100 mm.
A semiconductor memory module according to some embodiments of the inventive concepts includes a first substrate including a first corner and a first side surface, first semiconductor packages mounted on a lower surface of the first substrate, a second substrate disposed over the first substrate and including a second corner and a second side surface respectively corresponding to the first corner and the first side surface, second semiconductor packages mounted on an upper surface of the second substrate, a fixing structure in which the first corner and the second corner are inserted, the fixing structure fixing a distance between the first substrate and the second substrate, and at least one flexible connector connecting the first side surface and the second side surface.
Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The accompanying drawings represent non-limiting, example embodiments as described herein.
Hereinafter, to explain the inventive concepts in detail, embodiments according to the inventive concepts will be described with reference to the accompanying drawings. The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. These example embodiments are just that—examples—and many implementations and variations are possible that do not require the details provided herein. It should also be emphasized that the disclosure provides details of alternative examples, but such listing of alternatives is not exhaustive. Furthermore, any consistency of detail between various examples should not be interpreted as requiring such detail—it is impracticable to list every possible variation for every feature described herein. The language of the claims should be referenced in determining the requirements of the invention.
Ordinal numbers such as “first,” “second,” “third,” etc. may be used simply as labels of certain elements, steps, etc., to distinguish such elements, steps, etc. from one another. Terms that are not described using “first,” “second,” etc., in the specification, may still be referred to as “first” or “second” in a claim. In addition, a term that is referenced with a particular ordinal number (e.g., “first” in a particular claim) may be described elsewhere with a different ordinal number (e.g., “second” in the specification or another claim).
Items described in the singular herein may be provided in plural, as can be seen, for example, in the drawings. Thus, the description of a single item that is provided in plural should be understood to be applicable to the remaining plurality of items unless context indicates otherwise.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “top,” “bottom,” “front,” “rear,” and the like, may be used herein for ease of description to describe positional relationships, such as illustrated in the figures, for example. It will be understood that the spatially relative terms encompass different orientations of the device in addition to the orientation depicted in the figures. Also, these spatially relative terms such as “above” and “below” as used herein have their ordinary broad meanings—for example element A can be above element B even if when looking down on the two elements there is no overlap between them (just as something in the sky is generally above something on the ground, even if it is not directly above).
It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element (or using any form of the word “contact”), there are no intervening elements present at the point of contact.
As used herein, components described as being “electrically connected” are configured such that an electrical signal can be transferred from one component to the other (although such electrical signal may be attenuated in strength as it is transferred and may be selectively transferred). Moreover, components that are “directly electrically connected” share a common electrical node through electrical connections by one or more conductors, such as, for example, wires, pads, internal electrical lines, through vias, etc. As such, directly electrically connected components do not include components electrically connected through active elements, such as transistors or diodes.
Referring to
The first substrate 100 may have a first upper surface 100a and a first lower surface 100b. First upper conductive pads 101a are disposed on the first upper surface 100a of the first substrate 100. First lower conductive pads 101b are disposed on the first lower surface 100b of the first substrate 100. A first internal wiring 2 may be disposed in the first substrate 100. The first substrate 100 may have four first corners CR1 arranged in a clockwise direction. The first substrate 100 may have a first side surface RS1 and a second side surface RS2 opposite to each other. When viewed in a plan view, the first side surface RS1 and the second side surface RS2 of the first substrate 100 may be recessed toward a center of the first substrate 100.
The second substrate 200 may have a second upper surface 200a and a second lower surface 200b. Second upper conductive pads 201a are disposed on the second upper surface 200a of the second substrate 200. A second internal wiring 4 may be disposed in the second substrate 200. Although not shown, second lower conductive pads may also be disposed on the second lower surface 200b of the second substrate 200. The second substrate 200 may have four second corners CR2 arranged in a clockwise direction. The second corners CR2 are positioned over the first corners CR1 and each second corner CR1 may overlap (or correspond to) a respective first corner CR1. The second substrate 200 may have a third side surface RS3 and a fourth side surface RS4 opposite to each other. When viewed in a plan view, the third side surface RS3 and the fourth side surface RS4 of the second substrate 200 may be recessed toward a center of the second substrate 200. The third side surface RS3 may be disposed over the first side surface RS1 and may overlap the first side surface RS1 in a vertical direction. The fourth side surface RS4 may be disposed over the second side surface RS2 and may overlap the second side surface RS2 in a vertical direction.
First semiconductor packages 20 and at least one second semiconductor package 30 may be mounted on the first lower surface 100b of the first substrate 100. The first semiconductor packages 20 may be bonded to some of the first lower conductive pads 101b through first solder balls 12. The second semiconductor package 30 may be bonded to other portions of the first lower conductive pads 101b through second solder balls 14. Third semiconductor packages 40 may be disposed on the first upper surface 100a of the first substrate 100. The third semiconductor packages 40 may be bonded to other portions of the first upper conductive pads 101a through third solder balls 16.
Fourth semiconductor packages 50 may be mounted on the second upper surface 200a of the second substrate 200. The fourth semiconductor packages 50 may be bonded to some of the second upper conductive pads 201a through fourth solder balls 18. At least one of the first to fourth semiconductor packages 20, 30, 40, and 50 may independently be system large scale integration (LSI) chips or logic circuit chips. Alternatively, other semiconductor packages of the first to fourth semiconductor packages 20, 30, 40, and 50 may independently be NAND flash memory chips, DRAM chips, SRAM chips, EEPROM chips, PRAM chips, MRAM chips, ReRAM chips, high bandwidth memory (HBM) chips, and hybrid memory cubic (HMC) chips. The other semiconductor packages of the first to fourth semiconductor packages 20, 30, 40, and 50 may independently be a microelectromechanical system (MEMS) device chip or an application-specific integrated circuit (ASIC) chip. At least one of the first to fourth semiconductor packages 20, 30, 40, and 50 may be replaced with a passive element. The passive element may be a capacitor or resistor.
A first thermal interface material layer 62 may be interposed between the first semiconductor packages 20 and the case 500. A second thermal interface material layer 64 may be interposed between the second semiconductor package 30 and the case 500. A third thermal interface material layer 66 may be interposed between the fourth semiconductor packages 50 and the case 500. The thicknesses of the first thermal interface material layer 62, the second thermal interface material layer 64, and the third thermal interface material layer 66 may be different from each other. For example, the thickness of the first thermal interface material layer 62 may be greater than that of the second thermal interface material layer 64. The densities of the first thermal interface material layer 62, the second thermal interface material layer 64, and the third thermal interface material layer 66 may be different from each other. For example, the density of the first thermal interface material layer 62 may be higher than that of the second thermal interface material layer 64. The first thermal interface material layer 62, the second thermal interface material layer 64, and the third thermal interface material layer 66 may include a thermosetting resin layer. The first thermal interface material layer 62, the second thermal interface material layer 64, and the third thermal interface material layer 66 may further include filler particles dispersed in the thermosetting resin layer. The filler particles may include at least one of silica, alumina, zinc oxide, and nitrogen boride.
A first frame 90 may be interposed between the first substrate 100 and the second substrate 200. The first frame 90 may maintain a space between the first substrate 100 and the second substrate 200 at a certain distance or greater. A portion of the first frame 90 may be inserted into first grooves (H1 in
Referring to
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As shown in
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Each of the fixing structures 400 may include a first slot SL1 into which the first corner CR1 is fitted and a second slot SL2 into which the second corner CR2 corresponding to the first corner CR1 is fitted. The fixing structures 400 may fit the first corners CR1 of the first substrate 100 and the corresponding second corners CR2 of the second substrate 200, and thus a distance between the first substrate 100 and the second substrate 200 may be fixed to be constant by the fixing structure 400. The fixing structure 400 may have a single-layer or multi-layer structure formed of and/or including at least one of plastic, fiber, rubber, sponge, urethane, carbon material, ceramic, metal, and porous material. The fixing structure 400 may also be referred to as a ‘clip’. The fixing structures 400 may each independently have a length, width, and/or height in the range of 0.1 mm to 200 mm. A distance (DS1 in
However, in the inventive concepts, the fixing structures 400 may suppress the elastic restoring force of the first flexible connector 150. Accordingly, the physical stress applied to the first, second, and fourth solder balls 12, 14, and 18 may be dispersed, alleviated, and/or reduced, thereby preventing the solder ball cracks. Accordingly, the reliability of the semiconductor memory module may be improved by the fixing structures 400. Additionally, according to the inventive concepts since the corners CR1 and CR2 of the stacked structure ST that are inserted into the fixing structures 400 are generally not areas where the semiconductor packages 20 to 50 are disposed, the space utilization is efficient. Accordingly, the described integrated semiconductor memory module 1000 may provide an improved semiconductor memory module.
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The first semiconductor packages 20 are mounted on the first lower surface 100b of the first substrate 100 with first solder balls 12 interposed therebetween. The second semiconductor package 30 is mounted on the first lower surface 100b of the first substrate 100 with second solder balls 14 interposed therebetween. Third semiconductor packages 40 is mounted on the first upper surface 100a of the first substrate 100 with third solder balls 16 interposed therebetween. The third semiconductor packages 40 may be bonded to other portions of the first upper conductive pads 101a. Capacitors 70 are connected to the first side surface RS1 of the first substrate 100.
A second substrate 200 is prepared. The second substrate 200 may have a second upper surface 200a and a second lower surface 200b. The second substrate 200 as viewed in the state of
With the components in place as shown in the state of
The fourth semiconductor packages 50 are mounted on the second upper surface 200a of the second substrate 200 with fourth solder balls 18 interposed therebetween. The second side surface RS2 of the first substrate 100 is connected to the fourth side surface RS4 of the second substrate 200 by the first flexible connector 150.
A first thermal interface material layer 62 is formed on the first semiconductor packages 20. A second thermal interface material layer 64 is formed on the second semiconductor package 30. Third thermal interface material layers 66 are formed on the fourth semiconductor packages 50, respectively.
Referring to
Referring to
Two first corners CR1 of the first substrate 100 and the corresponding second corners CR2 of the second substrate 200 may be fitted into the fixing structures 400. In this example, for the first substrate 100, the two first corners CR1 adjacent to the first side surface RS1 and opposite to the second side surfaces RS2 on which the first flexible connector 150 is disposed may be fitted into the fixing structures 400. The remaining first corners CR1 of the first substrate 100 are not fitted in the fixing structures 400. For the second substrate 200, the two second corners CR2 adjacent to the third side surface RS3 and opposite to the fourth side surfaces RS4 on which the first flexible connector 150 is disposed may be fitted into the fixing structures 400. The remaining second corners CR2 of the second substrate 200 are not fitted in the fixing structures 400. Other structures may be the identical to or similar to those described with reference to
Referring to
The third substrate 300 may have a third upper surface 300a and a third lower surface 300b. A third internal wiring 6 may be disposed in the third substrate 300. The third substrate 300 may have four third corners CR3 arranged in a clockwise direction. The third substrate 300 may have a fifth side surface RS5 and a sixth side surface RS6 opposite to each other. When viewed in a plan view, the fifth side surface RS5 and the sixth side surface RS6 of the third substrate 300 may be recessed toward a center of the third substrate 300.
Fifth semiconductor packages 80 and at least one sixth semiconductor package 82 may be mounted on the third lower surface 300b of the third substrate 300 using solder balls. Seventh semiconductor packages 84 may be mounted on the third upper surface 300a of the third substrate 300 using solder balls.
Each of the fifth to seventh semiconductor packages 80, 82, and 84 may independently be a system large scale integration (LSI) chip or a logic circuit chip, or may be a memory device chip such as a NAND flash memory chip, a DRAM chip, an SRAM chip, an EEPROM chip, a PRAM chip, an MRAM chip, a ReRAM chip, a high bandwidth memory (HBM) chip, a hybrid memory cubic (HMC) chip, or the like, or may be a microelectromechanical system (MEMS) device chip, or an application-specific integrated circuit (ASIC). At least one of the fifth to seventh semiconductor packages 80, 82, and 84 may be replaced with a passive element. The passive element may be a capacitor or resistor.
A fourth thermal interface material layer 86 may be interposed between the fifth semiconductor packages 80 and the case 500. A fifth thermal interface material layer 88 may be interposed between the sixth semiconductor package 82 and the case 500.
The second frame 190 may be interposed between the first substrate 100 and the third substrate 300. The second frame 190 may maintain a gap between the first substrate 100 and the third substrate 300 of at least a certain distance. A portion of the second frame 190 may be inserted into the first substrate 100 and the third substrate 300.
The second flexible connector 250 may connect the recessed first side surface RS1 of the first substrate 100 to the recessed fifth side surface RS5 of the third substrate 300. The structure of the second flexible connector 250 may be identical or similar to the first flexible connector 150 described with reference to
Corners CR1, CR2, and CR3 of the stacked structure ST may be fitted into the fixing structures 400. The first corners CR1, the second corners CR2, and the third corners CR3 corresponding to each other may be fitted into the fixing structures 400. In the present example, four fixing structures 400 may be provided. The four corners of the stacked structure ST may be fitted into the fixing structures 400. Each of the fixing structures 400 may include a first slot SL1 into which a first corner CR1 is inserted, a second slot SL2 into which a second corner CR2 corresponding to the first corner CR1 is inserted, and a third slot SL3 into which a third corner CR3 corresponding to the first corner CR1 is inserted. Other configurations may be the identical to or similar to those described with reference to
In the semiconductor memory module according to the inventive concepts, at least one corner of the stacked structure including a first substrate and a second substrate that are stacked with each other is inserted into the fixing structure. The fixing structure may suppress the elastic restoring force of a flexible connector connecting the side surfaces of the substrates and may fix the first substrate and the second substrate to be spaced apart from each other by a least a certain distance. Accordingly, cracks of the solder balls under the semiconductor packages mounted on the first substrate and the second substrate may be prevented. Accordingly, the reliability of the bump solder joint may be improved, thereby improving the reliability of the semiconductor memory module.
In addition, as the corners of the substrates according to the inventive concepts may be inserted into the fixing structures, the regions where the semiconductor packages are disposed may be avoided, and thus space utilization is efficient. Accordingly, an improved the integrated semiconductor memory module may be provided.
While embodiments are described above, a person skilled in the art may understand that many modifications and variations are made without departing from the spirit and scope of the inventive concepts defined in the following claims. Accordingly, the example embodiments of the inventive concepts should be considered in all respects as illustrative and not restrictive, with the spirit and scope of the inventive concepts being indicated by the appended claims. The embodiments of
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0079770 | Jun 2023 | KR | national |
