3675319

Information

• Patent Grant
• 3675319

• References
• Source

• Patent Number

  3,675,319

• Date Filed

  Not available

• Date Issued

  Tuesday, July 11, 1972
  52 years ago

• CPC

  • H01L23/522 - including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L21/00 - Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/32134 - by liquid etching only
  • H01L21/7684 - Smoothing; Planarisation
  • H01L23/485 - consisting of layered constructions comprising conductive layers and insulating layers
  • H01L49/02 - Thin-film or thick-film devices
  • H01L2924/0002 - Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
  • Y10S148/041 - Doping control in crystal growth
  • Y10S148/042 - Doping, graded, for tapered etching
  • Y10S148/049 - Equivalence and options
  • Y10S148/051 - Etching
  • Y10S148/067 - Graded energy gap
  • Y10S148/122 - Polycrystalline

• US Classifications

  • 438 - Semiconductor device manufacturing: process
  • 148 - Metal treatment
  • 257 - Active solid-state devices
  • 427 - Coating processes