Patent Grant
11610780
The present invention generally relates to semiconductor fabrication and, more particularly, to the formation of hardmasks in semiconductor fabrication processes.
Fin field effect transistors (FinFETs) and other fin-based devices are frequently used in semiconductor structures to provide small-scale integrated circuit components. As these devices scale down in size, performance can be increased but fabrication becomes more difficult. In particular, errors in edge placement, critical dimension, and overlay approach the size of the structures being fabricated, making it difficult to accurately form such structures.
One particular challenge in forming fin structures is the selective removal of particular fins. For example, while a series of fins can be created using, e.g., sidewall image transfer techniques, significant errors in masking the fins may occur when operating near the limit of the lithographic process. Such errors may cause fins neighboring the removed fin to be damaged or removed entirely.
A method of forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.
A method of forming a three-color hardmask fin pattern includes depositing a second-color material around fins of a first color. Fins of the first color are etched away, leaving gaps. The etch further leaves at least one fin of the first color remaining. Fins of a third color are formed in the gaps.
A method of forming a three-color hardmask fin pattern includes forming fins of a first color on a fin base layer, by forming self-assembled fins on a seed layer, etching away every other self-assembled fin, leaving remaining self-assembled fins having differing heights, and etching down into a layer of first-color material around the remaining self-assembled fins to form fins of a first color. A second-color material is deposited around the fins of the first color. Fins of the first color are etched away, leaving gaps. Fins of a third color are formed in the gaps.
These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The following description will provide details of preferred embodiments with reference to the following figures wherein:
Embodiments of the present invention provide a hardmask fabrication process that may be used for fin formation in semiconductor fabrication. The present embodiment forms hardmask fins of three different compositions that have mutual etch selectivity, such that a spacing between fins of the same type is large enough that lithographic masking errors will not interfere when selectively removing fins. This provides a tri-color alternating hardmask, where the three different “colors” represent the three different fin hardmask composition. Thus the term “color” is defined herein to refer to one particular hardmask composition.
The present disclosure therefore refers to “first-color,” “second-color,” and “third-color” materials and fins. Each of these “colors” can be etched selectively to the other two, making it possible to remove a fin of one color without damaging nearby fins of a different color.
Referring now to
The fin base material 104 may be any appropriate material that may be used as a hardmask for the eventual formation of semiconductor fins in the semiconductor substrate 102. In one embodiment, it is contemplated that the layer of fin base material 104 may have a thickness of about 40 nm. It is specifically contemplated that silicon nitride may be used for the fin base material 104, but it should be understood that any appropriate hardmask material having etch selectivity with the underlying semiconductor and the three tri-color hardmask materials may be used. As used herein, the term “selective” in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied.
A layer of first-color hardmask material 106 is formed on the fin base material 104. It is specifically contemplated that the first-color hardmask material 106 may be formed from amorphous silicon, but any appropriate hardmask material having etch selectivity with the fin base material 104 and the other two tri-color hardmask materials may be used instead. In one embodiment the layer of first-color hardmask material 106 may have a thickness of about 20 nm.
A stack of layers is formed on top of the layer of first-color hardmask material 106. In particular, a first stack layer 108 is formed on the layer of first-color hardmask material 106 and may be formed from the same material as the fin base material 104 or any other appropriate material. In one embodiment the first stack layer 108 may have a thickness of about 5 nm. A second stack layer 110 is formed on the first stack layer 108. It is specifically contemplated that the second stack layer 110 may be formed from a dielectric material such as silicon dioxide and may have a thickness of about 10 nm.
A thin seed layer of polymer material 112 is formed on the stack. It is specifically contemplated that the seed layer 112 may be formed from, e.g., cross-linkable polystyrene, though it should be understood that other materials may be selected instead. The seed layer 112 is selected for its ability to guide later self-assembly of block copolymers (BCPs). In particular, seed material should match one of the two chains of the block copolymer system. For example, if a polystyrene/poly(methyl methacrylate) (PMMA) block copolymer is used, the seed layer 112 may be cross-linkable polystyrene. If a polystyrene/polyvinyl phenol (PVP) block copolymer is used, then the seed layer 112 may be cross-linkable PVP. In one particular embodiment, the seed layer 112 may be formed to a thickness between about 5 nm and about 8 nm, though it should be understood that greater or lesser thicknesses are also contemplated.
A set of fins 116 is formed on the seed layer 112. It is specifically contemplated that the fins 116 may be formed from a photoresist. The resist pattern of fins is formed at a pitch that is twice the natural period of the BCPs, which determines the ultimate fin pitch. For example, if fins having a pitch of 20 nm are ultimately needed, the fins 116 are formed at a pitch of 40 nm.
Referring now to
RIE is a form of plasma etching in which, during etching, the surface to be etched is placed on a radio-frequency powered electrode. Moreover, during RIE the surface to be etched takes on a potential that accelerates the etching species extracted from plasma toward the surface, in which the chemical etching reaction is taking place in the direction normal to the surface. Other examples of anisotropic etching that can be used at this point include ion beam etching, plasma etching or laser ablation.
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The lengths of the polymer chains can be selected to produce micro-domains with pitch between about 10 nm and about 200 nm. In this case, it is specifically contemplated that the self-assembling material may have halves of equal length of about 5 nm each, forming a chain with a total length of about 10 nm. When the chains self-assemble, with like ends facing one another, the resulting fins of each material are about, e.g., 10 nm in width. The resulting alternating fin configuration has fin pitch of half the original fin pitch on the guiding pattern. For example, if the original resist pattern 116 were formed with a fin pitch of about 40 nm, the fins of first DSA material and second DSA material have a respective fin pitch of about 20 nm.
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CVD is a deposition process in which a deposited species is formed as a result of chemical reaction between gaseous reactants at greater than room temperature (e.g., from about 25° C. about 900° C.). The solid product of the reaction is deposited on the surface on which a film, coating, or layer of the solid product is to be formed. Variations of CVD processes include, but are not limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD), Plasma Enhanced CVD (PECVD), and Metal-Organic CVD (MOCVD) and combinations thereof may also be employed. In alternative embodiments that use PVD, a sputtering apparatus may include direct-current diode systems, radio frequency sputtering, magnetron sputtering, or ionized metal plasma sputtering. In alternative embodiments that use ALD, chemical precursors react with the surface of a material one at a time to deposit a thin film on the surface. In alternative embodiments that use GOB deposition, a high-pressure gas is allowed to expand in a vacuum, subsequently condensing into clusters. The clusters can be ionized and directed onto a surface, providing a highly anisotropic deposition.
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It is to be understood that aspects of the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps can be varied within the scope of aspects of the present invention.
It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
The present embodiments can include a design for an integrated circuit chip, which can be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer can transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
Methods as described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
It should also be understood that material compounds will be described in terms of listed elements, e.g., SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes SixGe1−x where x is less than or equal to 1, etc. In addition, other elements can be included in the compound and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys.
Reference in the specification to “one embodiment” or “an embodiment”, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This can be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context dearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation n addition to the orientation depicted in the FIGS. For example, if the device in the FIGS. is turned over, elements described as “below” or “beneath” other elements or features could then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two lave one or more intervening layers can also be present.
It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.
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Block 1708 forms alternating, self-assembled fins 402, 404, and 406 from the guiding pattern, using molecular chains that have one block that is attracted by the seed layer 204 and one block that sits on brush material 302. Block 1710 then removes one type of the fins (particularly fins 404) using a selective etch process. Block 1712 etches down into a first-color hardmask material 106 to form first-color fins 604.
Block 1714 forms second-color hardmask material (e.g., OPL 702) in the gaps between the first-color fins 604. Block 1716 then recesses the second-color hardmask material down below the height of every other first-color fin, such that the second-color hardmask material has a height below the height of half of the first-color fins 604 and above the height of the other half of the first color fins 604.
Block 1718 removes the exposed first-color fins using any appropriate etch to form gaps 802. Block 1720 forms third-color hardmask material in the gaps 802. This material may be deposited by any appropriate deposition process and then polished down using, e.g., chemical mechanical planarization. CMP is performed using, e.g., a chemical or granular slurry and mechanical force to gradually remove upper layers of the device. The slurry may be formulated to be unable to dissolve, for example, the work function metal layer material, resulting in the CMP process's inability to proceed any farther than that layer.
Block 1722 recesses the second-color material below the height of all the first-color fins 604. The result is three sets of fins: first-color fins 604, second-color fins 1002, and third-color fins 902. Each color of fins has etch selectivity with each of the others, such that positioning or size errors in a mask that covers or uncovers a particular fin are unlikely to affect neighboring fins of the same color.
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Having described preferred embodiments of a system and method (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.
This patent application is a continuation of and claims priority to U.S. patent application Ser. No. 16/508,691, filed Jul. 11, 2019, now U.S. Pat. No. 11,031,248, issued Jun. 8, 2021, which is a continuation of U.S. patent application Ser. No. 15/802,634, filed Nov. 3, 2017, now U.S. Pat. No. 10,410,875, issued Sep. 10, 2019, which is a continuation of U.S. patent application Ser. No. 15/445,112, filed Feb. 28, 2017, now U.S. Pat. No. 10,312,103, issued Jun. 4, 2019, which are fully incorporated herein by reference.
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| Number | Date | Country | |
|---|---|---|---|
| 20210335619 A1 | Oct 2021 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16508691 | Jul 2019 | US |
| Child | 17340915 | US | |
| Parent | 15802634 | Nov 2017 | US |
| Child | 16508691 | US | |
| Parent | 15445112 | Feb 2017 | US |
| Child | 15802634 | US |
