Patent Application
20120190216
The present invention relates to the electrical and electronic arts, and, more particularly, to semiconductor fabrication and the like.
Complementary metal oxide semiconductor (CMOS) technology is employed in a number of applications, such as, for example, microprocessors, microcontrollers, static random access memory (SRAM), and the like, and even for some analog applications. Continued progress has been made in reducing the node size in CMOS semiconductor device fabrication technologies. The 22 nm node is expected to be the next step following 32 nm technology.
Principles of the invention provide annealing techniques for high performance complementary metal oxide semiconductor (CMOS) device fabrication. In one aspect, an exemplary method includes the steps of providing a semiconductor structure; and subjecting at least a portion of the structure to a long flash anneal process.
As used herein, “facilitating” an action includes performing the action, making the action easier, helping to carry the action out, or causing the action to be performed. Thus, by way of example and not limitation, instructions executing on one processor might facilitate an action carried out by instructions executing on a remote processor, by sending appropriate data or commands to cause or aid the action to be performed. For the avoidance of doubt, where an actor facilitates an action by other than performing the action, the action is nevertheless performed by some entity or combination of entities.
Techniques of the present invention can provide substantial beneficial technical effects. For example, one or more embodiments provide enhanced chip performance and/or quality.
These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
For 22 nm technology and beyond, where gate pitch is 80 nm or less, there is a difficult trade-off to increase the source-drain (SD) area for lower contact resistance while taking into account the need for adequate final spacer width to prevent the encroachment of SD to extension, which worsens device short channel effect (SCE) performance. This trade-off tends to drive the use of a thinner extension offset spacers, and the corresponding reduction of spike rapid thermal annealing (RTA) temperature for device centering. Although subsequent diffusionless laser and/or flash anneal can improve the dopant activation, defects anneal and activation typically deteriorates with lower starting spike RTA temperature. Diffusionless ms-laser- and/or flash-only approaches offer inadequate defect anneal and profile control to fully optimize device performance. One or more embodiments provide a high temperature long ms-anneal approach to meet the conflicting needs described above for scaled device centering and/or shallow junction optimization.
One or more embodiments provide sub-20 nm abrupt USJ formation with long ms-flash with sub-2 nm dopant motion control.
One or more embodiments provide a new combination of long millisecond (1-2.5 ms) flash anneal at high peak temperature (1200-1300° C.) and a new absorber with low deposition temperature (<400° C.) which generate highly activated (Rs˜500 ohm/sq), sub-20 nm abrupt (<3 nm/decade) N+ and P+ junctions. Details on exemplary embodiments of the new absorber are provided in U.S. patent application Ser. No. 12/760,620, IBM Attorney Docket Number YOR920090608US1, filed Apr. 15, 2010, entitled LOW-TEMPERATURE ABSORBER FILM AND METHOD OF FABRICATION, of inventors Katherina E. Babich et al., which is reproduced herein in pertinent part and also expressly incorporated herein by reference in its entirety for all purposes. This new approach also provides sub-2 nm T\N+ and P+ junction dopant motion control with multiple long ms-flash which are required for precision device centering and doping for 22 nm and beyond devices. High performance SOI (silicon-on-insulator) CMOS has been achieved with single long ms-flash and matches well with CMOS created with spike RTA+laser. In addition, long ms-flash NFETs (n-type field effect transistors) were found to need only ˜½ of the B halo dose and exhibit no anomalous corner leakage which is sometime found in spike RTA+laser NFETs. These results demonstrate better B halo localization in NFETs with long ms-flash, in one or more embodiments.
Thus, one or more embodiments provide high performance CMOS integrated with e-SiGe (PFETs), e-SIC(NFETs) source/drain, poly-pre-doped and long millisecond (1-5 ms) anneal at high peak temperature (1200-1350° C.) for extension/SD junctions formation and SiC source/drains strain optimization. Advantageously, one or more embodiments provide integration schemes which resolve the major conflicts in high performance CMOS device fabrication with e-SiGe (PFETs) and e-SiC for NFETs where substantial SiC strain loss results with the current high temperature RTA 1065° C./spike anneal for extension/SD activation and junction diffusion for device Coy optimization.
One aspect of one or more embodiments involves the replacement of the incompatible RTA 1065° C./spike implant junction anneal which causes the significant strain loss in SiC source/drain with the high temperature (1200-1350° C.) long ms (1-5 ms) flash anneal. The appropriate high temperature long millisecond (1-5 ms)-flash anneal will, in one or more embodiments, enable the rapid re-growth (<1 ms) of implanted SiC source/drain region without loss of substitutional carbon in SiC source/drain which is the primary source for the loss of SiC strain during standard RTA 1065° C./spike anneal, and/or at the same time provide better dopant activation and appropriate diffusion for reducing device external Rs reduction and optimal device Coy. In this manner, higher performance CMOS device performance results from the more well activated abrupt junctions and improved channel mobility for both PFETs (p-type field effect transistors) and NFETs with strain e-SiGe and e-SiC source/drains.
Ultra Shallow Junction (USJ) Formation with High Temperature Long MS-Flash
New Low temperature absorber coating: In connection with a series of experiments, USJ formation with long ms-anneal was carried out using a Mattson tool, known per se to the skilled artisan and available from Mattson Technology, Inc. 47131 Bayside Pkwy., Fremont, Calif. 94538 USA and/or Mattson Technology Canada, Inc., 605 West Kent Avenue, Vancouver, British Columbia V6P 6T7. Given the teachings herein, the skilled artisan will be able to implement one or more embodiments of the invention using the aforesaid Mattson tool.
The standard and long ms-flash time-temperature profiles are shown in
One or more embodiments advantageously employ a new absorber for long ms-flash. The absorber deposition temperature is <400° C. so that premature PAI SPE re-growth is avoided. With the new absorber, as seen in
Sub-20 nm abrupt N+ and P+ USJ formation:
Sub-2 nm N+ and P+ dopant motion control:
Devices with Long-MS-Flash and Spike RTA+ Laser
For experimental purposes, long ms-flash has been implemented in a SOI route with a Poly/SiON stack to compare with spike RTA+laser for an initial assessment of device centering and performance. SMT, e-SiGe and dual stress liner are used for achieving high performance n- and p-type FETs. Pre-doping and activation were done for poly gates before S/D to achieve ˜same Tinv which was otherwise compromised by the reduced diffusion from long ms-flash. For a MG/HK (metal-gate/high-k) process, gate pre-doping should not be needed in one or more embodiments. With the same extension I/I, device centering with single long-ms flash to match spike RTA+laser device performance can be achieved with a thinner offset spacer. For centered PFETs, similar As halo dose was needed. However, for centered NFETs, only ˜½ of B halo dose was needed in long-ms flash NFETs. This suggests better localization of B halo with long-ms flash compared with spike RTA+laser.
With continued reference to
In 2608, carry out chemical vapor deposition (CVD) of e-SiC in the source-drain regions 2668 of the NFET and chemical vapor deposition (CVD) of e-SiGe in the source-drain regions 2670 of the PFET. In 2610, carry out ion implantation for the extensions 2672 and halo regions 2674. Note shallow junction spacers 2676, also known as extension junction spacers. In 2612, carry out ion implantation for the source-drain regions 2668, 2670 and PAI (not separately numbered). Note deep source-drain spacers 2678, also known as wide spacers. In 2614, employ the stress memorization technique (SMT) for the NFETs using nitride stressor 2680. In 2616, carry out the long ms-flash anneal process as described elsewhere herein, optionally first applying the appropriate absorber material (in some cases, no absorber is used, as described elsewhere). In a non-limiting example, the absorber material (omitted from the drawings for clarity) is applied just prior to the annealing step 2616, as a blanket over the entire surface, with a thickness of at least about 3000 Angstroms. The absorber blanket is then removed after the annealing is complete. The absorber material may include graphite and may have a high thermal conductivity in at least some instances. In 2618, carry out silicide contact formation to obtain contacts 2682.
High temperature (1200-1300° C.) long ms-flash anneal (1-2.5 ms), optionally combined with a new absorber, has been developed to generate better activated and more box-like abrupt sub-20 nm N+ & P+ junctions over standard ms-flash anneal (in some cases, no absorber is used, as described elsewhere). Sub-2 nm N+ & P+ dopant motion control had been demonstrated with multiple long-ms flash. High performance SOI CMOS has been achieved with single long ms-flash and matched well with CMOS created with spike RTA+laser. Long ms-flashed NFETs show no corner leakage which is sometimes found in spike RTA+laser NFETs. These results demonstrate the application of high temperature long ms-anneal for improved junction activation, precision device centering and/or doping control for 22 nm & beyond device technology, in accordance with one or more embodiments of the invention.
Given the discussion thus far, it will be appreciated that, in general terms, an exemplary method, according to an aspect of the invention, includes the step of providing a semiconductor structure (see, e.g., steps 2612, 2614, and 2616 of
In a non-limiting example of a semiconductor structure, the structure includes a plurality of NFET portions 2654 and a plurality of PFET portions 2656. The structure also includes a plurality of shallow trench isolation regions 2652 separating the NFET portions and the PFET portions. In addition, the structure includes a plurality of NFET source-drain regions 2668 associated with the NFET portions, which have been subjected to e-SiC chemical vapor deposition (see, e.g. step 2608). Even further, the structure includes a plurality of PFET source-drain regions 2670 associated with the PFET portions, that have been subjected to e-SiGe chemical vapor deposition (again, see, e.g., step 2608). Still further, the structure includes a plurality of NFET gates 2662 intermediate given ones of the source-drain regions associated with the NFET portions, and a plurality of PFET gates 2664 intermediate given ones of the source-drain regions associated with the PFET portions. The structure even further includes a plurality of NFET halo regions intermediate the given ones of the source-drain regions associated with the NFET portions and the NFET gates, and a plurality of PFET halo regions intermediate the given ones of the source-drain regions associated with the PFET portions and the PFET gates. Please refer to step 2610 and note that only a single one of the halo regions (in this case, a PFET halo region) has been given reference character 2674 to avoid clutter.
In some instances, the long flash anneal process includes a peak temperature of about 1300 degrees centigrade maintained for about 2.5 milliseconds. In some cases where the absorber is used, the low deposition temperature is no greater than about 400 degrees centigrade.
The different ranges of parameters set forth herein can be combined in any desired combination.
In some instances, the structure provided in the providing step has a gate pitch of no more than about 80 nanometers.
In some cases, the method further comprising maintaining the semiconductor structure at an intermediate temperature, Ti, of about 300 to about 900 degrees centigrade prior to the long flash anneal process. In some applications, the intermediate temperature is about 400 to about 900 degrees centigrade.
In some instances, the intermediate temperature is about 300 to about 400 degrees centigrade and the semiconductor structure comprises a silicide. In such cases, the long flash anneal process could include, for example, a peak temperature of about 900 to about 950 degrees centigrade maintained for about 1 to about 5 milliseconds.
In one or more embodiments, the long flash anneal process includes a peak temperature of about 1200 to about 1300 degrees centigrade maintained for about 1 to about 2.5 milliseconds; and in some embodiments, the long flash anneal process includes a peak temperature of about 1200 to about 1350 degrees centigrade maintained for about 1 to about 5 milliseconds.
In some cases, the long flash anneal process includes a peak temperature of about 950 to about 1300 degrees centigrade maintained for about 1 to about 2.5 milliseconds; in some embodiments, the long flash anneal process includes a peak temperature of about 950 to about 1250 degrees centigrade maintained for about 1 to about 2.5 milliseconds; and in some embodiments, the long flash anneal process comprises a peak temperature of about 1150 to about 1300 degrees centigrade maintained for about 1 to about 5 milliseconds.
In some instances, the structure provided in the providing step comprises a silicon body having a thickness of no more than about 10 nanometers.
In one or more embodiments, the low deposition temperature is no greater than about 450 degrees centigrade; in some embodiments, the low deposition temperature ranges from about 250 degrees centigrade to about 450 degrees centigrade; and in some embodiments, the low deposition temperature ranges from about 350 degrees centigrade to about 400 degrees centigrade.
In some instances, the long flash anneal process includes a peak temperature of about 1300 degrees centigrade maintained for about 2.5 milliseconds, and the low deposition temperature is no greater than about 400 degrees centigrade; and in some instances, the long flash anneal process includes a peak temperature of about 1200 to about 1350 degrees centigrade maintained for about 1 to about 5 milliseconds, and the low deposition temperature ranges from about 250 degrees centigrade to about 450 degrees centigrade.
In one or more embodiments, in the applying step, the absorber includes an amorphous carbonitride film. In some cases, the amorphous carbonitride film has an extinction coefficient of greater than 0.2 and an emissivity of greater than 0.8. In some cases, the subjecting step includes causing electromagnetic radiation having at least one wavelength between 190 nm and 1000 nm to be absorbed by the absorber.
In some instances, the long flash anneal process includes a peak temperature of about 1200 to about 1350 degrees centigrade maintained for about 1 to about 5 milliseconds; the low deposition temperature ranges from about 250 degrees centigrade to about 450 degrees centigrade; and, in the applying step, the absorber comprises an amorphous carbonitride film. In some cases, the amorphous carbonitride film has an extinction coefficient of greater than 0.2 and an emissivity of greater than 0.8. In some cases, the subjecting step includes causing electromagnetic radiation having at least one wavelength between 190 nm and 1000 nm to be absorbed by the absorber.
In some cases, the peak temperature is no more than about 1100 degrees centigrade. In some cases, peak temperature ranges specified elsewhere as about 1200 to about 1350 degrees centigrade can instead range from about 1100 to about 1350 degrees centigrade; peak temperatures at or near 1100 degrees centigrade are believed to be particularly useful for gate stacks.
Thus, one or more techniques disclosed herein can be used to anneal a variety of structures, such as, for example, junctions, gate stacks such as metal gate stacks, silicides, and the like. It is believed that one or more embodiments are especially helpful for use with metal gate stacks, which tend to be sensitive. Furthermore, use of an absorber is optional, but may be helpful to reduce power requirements or for highly reflective substrates such as Silicon on Insulator (SOI). In such cases, the dynamic range (temperature rise from intermediate to peak temperature) may be limited without use of the absorber. In some cases, the absorber will increase the dynamic range to about 500 to about 600 degrees centigrade.
In some instances, the structure is a metal high-k gate stack.
In a typical case, the structure will be at ambient temperature and will be heated to an intermediate temperature, Ti. In some cases, there will be little or no dwell time at Ti (say, 1 millisecond) before the lamp of the Mattson tool is activated. However, in other cases, a more significant dwell time at Ti may be appropriate (say, a few seconds) before activating the lamp. In some cases, regardless of whether an absorber is employed, the dwell time at Ti may range from about zero to about five seconds.
It should be noted that all ranges for intermediate temperature, peak temperature, dwell time, time at peak, and related parameters are, in general, equally applicable for cases with and without absorber use.
The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Reproduction of Pertinent Portions of U.S. patent application Ser. No. 12/760,620
For purposes of this portion of the present application, it will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
It has been determined through experimentation that in order to achieve a sufficient amorphous carbon only absorbent film, as defined by a k greater than 0.15, an emissivity of about 0.8 or greater, and a film with a minimum of hydrocarbon in it as observed by FTIR, it was necessary to deposit an amorphous carbon only layer (ACL) at 550° C. This is undesirable as the constantly shrinking sizes of transistors put an unavoidable limitation on the processing temperatures of devices. When scaling down the dimensions of metal oxide semiconductor field effect transistor (MOSFET) devices, ultra-shallow contacts and extremely abrupt junctions between the source/drain electrodes and the channel are needed in order to suppress short channel effects. At the same time, the source/drain contacts must be highly doped to keep parasitic resistances as small as possible. Current MOSFET fabrication schemes employ ion implantation for the amorphization and subsequent dopant introduction into a silicon crystal lattice. Silicon amorphization reduces dopant atom channeling during implantation, thereby allowing ultra-shallow junction formation. Although ion implantation offers a number of advantages, the inherent damage to the crystal lattice structure contributes to the mobility degradation in the final device structures. Lattice repair via the application of an annealing step is thus appropriate. It has been determined that preamorphized silicon (PAI) regrowth during deposition of the amorphous carbon layer at 550° C. (Sample 1. Table 1) hinders dopant activation at higher subsequent anneals. During the ACL deposition process, the PAI growth rate for implanted wafers is significant.
One potential solution is to lower the deposition temperature of amorphous carbon only films, however as the deposition temperature of the amorphous carbon only films was decreased below 550° C., hydrocarbon content in the film increased rapidly which reduced the absorptive capabilities of the film, k was reduced and emissivity was reduced. As detailed in Table 1, the normalized hydrocarbon content rapidly increases as the deposition temperature is reduced from 550° C. to 480° C. and 400° C. As summarized in Table 1, the k decreased with lower deposition temperature.
FTIR analysis of the resultant amorphous carbon only films (See,
The increased hydrocarbon content lowered the extinction coefficient (k) of the amorphous carbon only films and resulted in a higher level of outgassing during laser and flash anneals. Higher extinction coefficient (k) is desirable because it results in greater absorbance and minimizes reflectance variations from the underlying substrate.
The overall higher hydrocarbon content adversely affects the optical properties of the film, and lowers the extinction coefficient (k), and the emissivity of the film making the film more transparent to the impinging laser.
In some instances, an improved electromagnetic radiation absorber is provided that comprises, consists essentially of or consists of, an amorphous carbonitride (ACN) film having an extinction coefficient of greater than 0.15, and an emissivity of greater than 0.8. In some cases, the amorphous carbonitride film can be characterized as having a low hydrocarbon content as observed by FTIR. ACN films having the low hydrocarbon content, minimize outgassing during a subsequent laser annealing or flash annealing process. The ACN films can be easily removed after annealing by plasma oxygen ashing. Such an amorphous carbonitride film represents an improvement over conventionally used amorphous carbon only films.
Reference is now made to
When a semiconductor material is employed as an element of substrate 10, the semiconductor material can include, but is not limited to Si, Ge, SiGe, SiC, SiGeC, GaAs, GaN, InAs, InP and all other III/V or II/VI compound semiconductors. The semiconductor material may also comprise an organic semiconductor or a layered semiconductor such, as for, example. Si/SiGe, a silicon-on-insulator (SOI), a SiGe-on-insulator (SGOI) or a germanium-on-insulator (GOI). In some embodiments of the invention, the semiconductor material is a Si-containing semiconductor material that includes silicon. The semiconductor material may be doped, undoped or contain doped and undoped regions therein. The semiconductor material can include a single crystal orientation or it may include at least two coplanar surface regions that have different crystal orientations (the latter semiconductor material can be referred to as a hybrid orientation substrate). The semiconductor material can be process utilized techniques well known to those skilled in the art to include one or more well regions, and/or one or more isolation regions. The semiconductor material can also be processed utilizing techniques well known to those skilled in the art to include one or more semiconductor devices atop an uppermost surface of the semiconductor substrate.
When a dielectric material is employed as an element of substrate 10, the dielectric material can include an organic insulator, an inorganic insulator or any combination thereof including multilayers. In some cases, the dielectric material is an oxide, a nitride, and/or an oxynitride. In yet another case, the dielectric material has a dielectric constant, as measured in a vacuum of equal to, or greater than, the dielectric constant of silicon oxide.
When a conductive material is employed as an element of substrate 10, the conductive material can include, for example, a doped Si-containing material, an elemental metal, an alloy of an elemental metal, a metal silicide, a metal nitride or any combination thereof including multilayers.
It is observed that the semiconductor material, dielectric material and/or conductive material may be part of a device or structure, which may be discrete or interconnected.
As stated above, and as illustrated in
The amorphous carbonitride film 12 also has an emissivity of greater than 0.8. Typically, the amorphous carbonitride film 12 has an emissivity from 0.8 to 0.95. More typically, film 12 has an emissivity from 0.85 to 0.92.
A further feature of the amorphous carbonitride film 12 is that it has a minimum hydrocarbon content as measured by FTIR. By “a minimum of hydrocarbon content as observed by FTIR” it is meant a normalized hydrocarbon content less than 3 as defined by integrating under the C—H stretching peak in the FTIR spectra from 3170-2750 cm−1 and dividing the integrated peak area by the film thickness in microns.
The thickness of the amorphous carbonitride film 12 that is formed may vary depending on the conditions in which the amorphous carbonitride film 12 is deposition. Typically, the amorphous carbonitride film 12 that is formed atop the substrate 10 has a thickness from 50 nm to 5000 nm, with a thickness from 100 nm to 500 nm being more typical. Other thicknesses can also be employed so long as the thickness does not interfere with the amorphous carbonitride film being employed as an absorbing layer for exposures to various wavelengths of electromagnetic radiation including, for an example, an exposure wavelength between 190 nm and 1000 nm.
The amorphous carbonitride film 12 can be formed utilizing any low temperature (e.g., of less than, or equal to, 450° C.) deposition process. Suitable examples of low temperature deposition processes that can be used in forming the amorphous carbonitride film 12 include, but are not limited to chemical vapor deposition (CVD) and plasma enhanced chemical vapor deposition (PECVD). In one embodiment of the invention, the amorphous carbonitride film 12 is formed utilizing a low temperature PECVD process. As stated above, any deposition process can be used in forming the amorphous carbonitride film 12 having the above properties so long as the deposition temperature is less than, or equal to, 450° C. In one embodiment of the invention, the amorphous carbonitride film 12 having the above properties can be produced using a deposition temperature from 250° C. to 450° C. In yet another embodiment of the invention, the amorphous carbonitride film 12 having the above properties can be produced using a deposition temperature from 350° C. to 400° C.
In one embodiment of the invention, the amorphous carbonitride film 12 having the above properties can be produced using a combination of at least a carbon precursor source, and a nitrogen source. An oxidant is also typically, but not necessarily always, employed to facilitate decomposition, fragmentation and hydrogen removal. Such a combination of gases can be referred to herein as a reactant gas mixture. The reactant gas mixture may further include an inert gas such as helium or argon. The inert gas may be introduced as a separate component of the reactant gas mixture or it can be present within at least one of the carbon precursor source, the nitrogen source and the oxidant.
In some cases, the amorphous carbonitride film 12 having the above properties can be produced using a single carbonitride precursor that includes both carbon and nitrogen in the molecule. An oxidant is also typically, but not necessarily always, employed in this embodiment of the invention as well.
The carbon precursor source that can be employed in the invention is selected from alkanes, alkenes, alkynes and mixtures thereof. The carbon precursor sources may be linear, branched, and/or cyclic. In one embodiment of the invention, the carbon precursor sources have a minimal C/H ratio. By “minimal C/H ratio” it is meant less than 3 hydrogens for every carbon atom in the precursor.
The term “alkane” denotes a chemical compound that consists only of the elements carbon and hydrogen (i.e. hydrocarbons), wherein these atoms are linked together exclusively by single bonds (i.e., they are saturated compounds). In one embodiment of the invention, the alkane includes from 1 to 22, typically from 1 to 16, more typically, from 1 to 12 carbon atoms.
The term “alkene” denotes an unsaturated chemical compound containing at least one carbon-to-carbon double bond. In one embodiment, the alkene is an acyclic alkene, with only one double bond and no other functional groups. In such an embodiment, the acrylic alkene forms a homologous series of hydrocarbons with the general formula CnH2n, wherein n is an integer from 2 to 22, typically 2 to 16, more typically 2 to 12 carbon atoms.
The term “alkyne” denotes a hydrocarbon that has a triple bond between two carbon atoms, with the formula CnH2n-2, wherein n is an integer from 2 to 22, typically 2 to 16, more typically 2 to 12 carbon atoms. Alkynes are traditionally known as acetylenes.
Some examples of typical carbon precursor sources that can be employed in forming the amorphous carbonitride film 12 include, but are not limited to ethylene, propylene, butene, acetylene, and/or methyl acetylene. In some cases, propylene (C3H6) is employed as the carbon precursor source.
The nitrogen source that can be employed in forming the amorphous carbonitride film 12 can be selected from nitriding sources including, but not limited to nitrogen, ammonia, amines, azides, and/or hydrazines. In some cases, nitrogen (N2) and/or ammonium (NH3) is employed as the nitrogen source. The oxidant that can be employed in forming the amorphous carbonitride film 12 can be selected from oxidizing sources including oxygen, nitrous oxide, water, and/or ozone. In some cases, oxygen is employed as the oxidant.
Although any combination of carbon precursor source, nitrogen source and oxidant can be employed in forming the amorphous carbonitride film 12, some instances employ propylene (C3H6) as the carbon precursor source, nitrogen (N2) or ammonium (NH3) as the nitrogen source, and oxygen (O2) as the oxidant. Such a reactant gas mixture can be used as is or diluted with an inert gas such as helium or argon.
In some cases, as mentioned above, a single carbonitride precursor that includes both carbon and nitrogen in the molecule can be used to form the amorphous carbonitride film 12. One example of such a single carbonitride precursor that can be employed is acetonitrile (CH3CN). Other single carbonitride precursors beside acetonitrile can be used as long as the precursor includes carbon and nitrogen atoms therein. When a single carbonitride precursor is employed, an oxidant, as described above can also be used. The single carbonitride precursor can be used as is or diluted with an inert gas such as helium or argon. Other potential single carbonitride precursors include heterocyclic compounds such as pyrrole, imidazole, pyrazole, pyridine, pyrazine, pyrimidine, pyridazine, pyrazinyl, imidazolyl, pyrimidinyl, piperazine, triazine, amines such as methylamine, diamine ethane, diamine methane, aminoethane, aminopropane, azo, hydrzo, dimethylhydrazine, alkylazo compounds such as diethyldiazene, and amidines including acetamidine.
The gases may be introduced separately into a reactor chamber of a deposition tool, or some, or all of the gases may be admixed prior to being introduced into a reactor chamber of a deposition tool. Typically, the various gases are admixed in a mixing system prior to being introduced into the reactor chamber of a deposition tool. The reactor chamber of the deposition tool typically includes a substrate holder in which the substrate 10 is positioned within the reactor chamber. The distance of the substrate holder from the nozzle (or nozzles or showerhead) in which the reactant gas mixture (or gasses) is (are) introduced may vary within typical ranges well known to those skilled in the art. Typically, the substrate holder and hence substrate 10 is positioned a distance from 600 mils to 200 mils from the nozzle (or nozzles).
In addition, the gases may be introduced in a deposition tool in different stochiometries. In some cases, the carbon source may be introduced at a flow rate between 50 sccm and 2000 sccm, the nitrogen source may be introduced at a flow rate between 10 sccm and 50000 sccm, and the oxidant may be introduced at a flow rate between 10 sccm and 500 sccm. In other cases, the carbon source may be introduced at a flow rate between 50 sccm and 5000 sccm, the nitrogen source may be introduced at a flow rate between 10 sccm and 5000 sccm, and the oxidant may be introduced at a rate between 1 sccm and 1000 sccm. The inert gas may be introduced at a flow rate from 50 sccm to 50000 sccm.
In some further cases, the process pressure used in forming the amorphous carbonitride film 12 can be varied from 1 torr to 8 torr. In yet another embodiment of the invention, the substrate temperature during the deposition process can be fixed at 400° C. or 350° C. In an even further embodiment of the invention, the plasma can be generated using either a low frequency radio frequency (LFRF) plasma source at 100 MHz or a high frequency radio frequency HFRF plasma source at 13.56 GHz. The process pressure, substrate temperature and power used in generating the plasma are exemplary and other conditions are possible provided the selected conditions are capable of forming an amorphous carbonitride film having an extinction coefficient of greater than 0.15, an emissivity of greater than 0.8 and a minimum of hydrocarbon content.
In one embodiment of the invention, the amorphous carbonitride film 12 is formed by positioning substrate 10 within a parallel plate plasma enhanced chemical vapor deposition chamber. A reactant gas mixture, as defined above, is then introduced into the reactor chamber and thereafter an amorphous carbonitride film 12 having an extinction coefficient of greater than 0.15, an emissivity of greater than 0.8 and a minimum of hydrocarbon is formed.
Reference is now made to
The amorphous carbonitride films described hereinabove can be used for absorbing electromagnetic radiation having one or more wavelengths between 190 nm and 1000 nm. The amorphous carbonitride films described hereinabove can also be used in conjunction with conventional laser anneals to improve the heating uniformity across a plurality of surfaces.
The following examples are provided to illustrate the formation of amorphous carbonitride films having an extinction coefficient (k) of greater than 0.15, an emissivity of greater than 0.8 and a minimum of hydrocarbon. The following examples illustrate some advantages and/or improvements that can be obtained from such amorphous carbonitride films.
Amorphous carbonitride films were deposited onto an oxide coated silicon substrate using the following conditions: 400° C. deposition temperature, 500 watts LFRF, 220 mils, and 3 torr pressure. Propylene (C3—H6) was fixed at 1000 sccm, while the reactant gases (i.e. nitrogen and ammonia), and the oxidant (N2O) were varied as detailed in Table 2. Refractive index (n) and extinction coefficient (k) were measured using an n&k tool.
As summarized in the Table 2, for Sample 1 deposited from propylene and N2O only, the extinction coefficient was 0.15. However, by formation of the carbonitride in Sample 2 of this example with the addition of nitrogen, and ammonia the extinction coefficient, k was increased to 0.19. In Sample 3 of this example an additional increase in N2O increased k to 0.3. The oxidant, N2O in this particular case was essential in increasing k.
Amorphous carbonitride films were deposited onto an oxide coated silicon substrate with deposition conditions as summarized in Table 3 at 400° C. Propylene (C3H6) was fixed at 500 sccm, oxygen was fixed at 50 sccm, mil spacing was fixed at 220 mils and pressure was fixed at 4 torr. Refractive index (n) and extinction coefficient (k) were measured using an n&k tool. Oxygen was used as the oxidant as shown in Table 3.
Switching from HFRF to LFRF plasma power resulted in a halving of the normalized hydrocarbon content as observed by FTIR. The normalized hydrocarbon content is defined by integrating under the C—H stretching peak in the FTIR spectra from 3170-2750 cm−1 and dividing the integrated peak area by the film thickness in microns.
Thin layers of amorphous carbonitride (ACN) films were deposited on top of each other with varying plasma frequencies to achieve thicker films. Such a structure is shown, for example, in
Surface resistance measurements were taken with the last four conditions. As shown in
As shown in
The effect of He dilution on k was also observed, and it was determined that by increasing the He dilution resulted in an ACN film having a larger k. In this example, the deposition temperature was 350° C., 220 mil, the pressure was 4 torr. Table 6 includes the other conditions used in this example. As shown in the table by increasing He flow k can be increased.
Amorphous carbonitride films were deposited at 350° C. with varying amounts of oxygen and other conditions as mentioned in this example. The carbon precursor. i.e., C3H6, was flowed at 350 sccm, 1\17 at 2500 sccm. NH3 at 300 sccm, He at 5000 sccm and a LFRF power of 500 watts (approximately 100 MHz) and a pressure of 4 torr were employed. The optical properties measured on the films indicated that extinction coefficient of such films were very high. See Table 7.
These films were then subjected to flash lamp annealing and SEM micrographs were obtained on ACN films after flash anneal applications. It was evident from the SEM micrographs that ACN films deposited at 350° C. survived the flash lamp annealing and also they are very conformal with intact microstructure after annealing. One such SEM micrograph is shown, for example, in
As shown in
Reduction in reflectivity enables higher front surface temperatures during flash anneal which, in turn, enables lower backside substrate temperatures to minimize dopant movement, source/drain junction profile broadening and increased junction depth. Shown in
Flash anneal and laser spike anneals have been introduced to activate dopants in milliseconds. Boron dopant deactivation is proposed to be due to the formation of inactive boron-interstitial clusters (BICs) as a result of the release of silicon interstitials from the end-of-range (EOR) defects upon annealing. Carbon atoms are reported to be an effective sink for silicon interstitials and that extended defect levels are reduced or eliminated with increasing carbon dose. See, Chyiu Hyia Poon, JOURNAL OF APPLIED PHYSICS 103, 084906 2008. In this example, the carbonitride absorber layer deposited at 350° C. (Sample 2. Table 7) was employed as an efficient absorber coating for a flash anneal so that the arc-lamp light from the flash anneal is efficiently absorbed and subsequently increased the temperature jump for the SOI device substrate to achieve improved C substitution in SiC source/drain and to maximize junction activation for 22 nm CMOS technology devices and beyond.
Shown in
This patent application claims the benefit of U.S. Provisional Patent Application Ser. No. 61/434,618 filed on Jan. 20, 2011, and entitled “ANNEALING TECHNIQUES FOR HIGH PERFORMANCE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR(CMOS) DEVICE FABRICATION.” The disclosure of the aforementioned Provisional Patent Application Ser. No. 61/434,618 is expressly incorporated herein by reference in its entirety for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 61434618 | Jan 2011 | US |
