Patent Grant
10923340
The present disclosure relates generally to a method and apparatus for electroplating a metal layer on a semiconductor wafer. More particularly, the method and apparatus described herein are useful for controlling plating uniformity.
In semiconductor device manufacturing, a conductive material, such as copper, is often deposited by electroplating onto a seed layer of metal to fill one or more recessed features on a semiconductor wafer substrate. Electroplating is a method of choice for depositing metal into the vias and trenches of the wafer during damascene processing, and is also used in wafer level packaging (WLP) applications to form pillars and lines of metal on the wafer substrate. Another application of electroplating is filling of Through-Silicon Vias (TSVs), which are relatively large vertical electrical connections used in 3D integrated circuits and 3D packages.
In some electroplating substrates, the seed layer is exposed over the entire surface of the substrate prior to electroplating (typically in damascene and TSV processing), and electrodeposition of metal occurs over the entirety of the substrate. In other electroplating substrates, a portion of the seed layer is covered by a non-conducting material, such as by photoresist, while another portion of the seed layer is exposed. In such substrates with partially masked seed layer electroplating occurs only over the exposed portions of the seed layer, while the covered portions of the seed layer are protected from being plated upon. Electroplating on a substrate having a seed layer that is coated with patterned photoresist is referred to as through resist plating and is typically used in WLP applications.
During electroplating, electrical contacts are made to the seed layer (e.g., a copper seed layer) at the periphery of the wafer, and the wafer is electrically biased to serve as a cathode. The wafer is brought into contact with an electrolyte, which contains ions of metal to be plated. The electrolyte typically also includes an acid that provides sufficient conductivity to the electrolyte and may also contain additives, known as accelerators, suppressors, and levelers that modulate electrodeposition rates on different surfaces of the substrate.
One of the problems encountered during electroplating is non-uniform distribution of thickness of electrodeposited metal along the radius of the circular semiconductor wafer. This type of non-uniformity is known as radial non-uniformity. Radial non-uniformity may occur due to a variety of factors, such as due to a terminal effect, and due to variations in electrolyte flow at the surface of the substrate. Terminal effect manifests itself in edge-thick electroplating, because the potential in the vicinity of the electrical contacts at the edge of the wafer can be significantly higher than at the center of the wafer, particularly if a thin resistive seed layer is used.
Another type of non-uniformity, which can be encountered during electroplating is azimuthal non-uniformity. For clarity, we define azimuthal non-uniformity, using polar coordinates, as thickness variations exhibited at different angular positions on the wafer at a fixed radial position from the wafer center, that is, a non-uniformity along a given circle or portion of a circle within the perimeter of the wafer. This type of non-uniformity can be present in electroplating applications, independently of radial non-uniformity, and in some applications may be the predominant type of non-uniformity that needs to be controlled. It often arises in through resist plating, where a major portion of the wafer is masked with a photoresist coating or similar plating-preventing layer, and the masked pattern of features or feature densities are not azimuthally uniform near the wafer edge. For example, in some cases there may be a technically required chord region of missing pattern features near the notch of the wafer to allow for wafer numbering or handling.
Excessive radial and azimuthal non-uniformity can lead to non-functional chips. Therefore methods and apparatus for improving plating uniformity are needed.
Described are method and apparatus for electroplating metal on a substrate with improved plating uniformity. Apparatus and methods described herein can be used for electroplating on a variety of substrates, and are particularly useful for through resist plating during WLP processing. The apparatus and methods make use of an ionically resistive ionically permeable element having spatially tailored resistivity that is positioned in proximity of the substrate during electroplating and is configured to target the selected type of non-uniformity. For example radial non-uniformity due to terminal effect is mitigated by using an ionically resistive ionically permeable element positioned in close proximity to the wafer, wherein the element is more resistive at the edge than at the center. The resistivity can be spatially varied by spatially varying the thickness of the element, the porosity of the element, or a combination of thickness and porosity.
In one aspect of the invention an electroplating apparatus is provided, wherein the apparatus includes (a) a plating chamber configured to contain an electrolyte and an anode while electroplating metal onto a semiconductor substrate; (b) a substrate holder configured to hold the semiconductor substrate such that a plating face of the semiconductor substrate is separated from the anode during electroplating; and (c) an ionically resistive ionically permeable element comprising a substantially planar substrate-facing surface and an opposing surface, wherein the element allows for flow of ionic current through the element towards the substrate during electroplating, and wherein the element comprises a region having varied local resistivity. In some embodiments the local resistivity is varied gradually in the region having varied local resistivity.
In one example the region having varied local resistivity is coextensive with the element (i.e. the region is the entire element) and the local resistivity in this region decreases radially from an edge of the element to the center of the element. This embodiment is particularly useful for mitigating terminal effect, particularly when depositing metal in WLP features.
In another example, the element includes a region of constant local resistivity surrounding the region of varied local resistivity, wherein the region of varied local resistivity is located in a central portion of the element and wherein the local resistivity in the region of varied local resistivity decreases radially from an interface with the region of constant resistivity to the center of the element. This embodiment is particularly useful for addressing non-uniformity that arises due to thicker photoresist layer in the center of the semiconductor substrate encountered in through-resist electroplating.
The resistivity of the element can be varied using a number of approaches. In one approach, the element has a varied thickness and constant porosity in the region having varied local resistivity. The variation in thickness is preferably, but not necessarily, gradual. In another approach, the element has varied porosity (preferably gradually varied porosity) and constant thickness in the region having varied local resistivity. A combination of these approaches can also be used. For example, in some embodiments, the element has both gradually varied porosity and gradually varied thickness in the region having varied local resistivity.
In some embodiments, the element has a plurality of non-communicating channels made through an ionically resistive material and connecting the substrate-facing surface of the element with the opposite surface of the element, wherein the element allows for movement of the electrolyte through the channels towards the substrate. In some embodiments the region having varied local resistivity has a gradually varied density of the non-communicating channels. In some embodiments the region having varied local resistivity has a gradual variation in diameter of the non-communicating channels. In some embodiments the region having varied local resistivity has a gradual variation in an incline angle of the non-communicating channels relative to a plane defined by the plating face of the substrate. All combinations of these embodiments (variation of channel density, variation of channel diameter, and variation of incline angle) can also be used to provide variation in resistivity.
In one specific example, that employs variation of thickness to achieve resistivity variation, the region having varied local resistivity is coextensive with the element and the local resistivity in this region decreases radially from an edge of the element to the center of the element due to gradually decreasing thickness of the element from the edge of the element to the center of the element. In some embodiments of this example the opposite surface of the element is a convex surface that follows a second order polynomial function, when viewed in a radial cross-section.
In another specific example that employs variation of thickness to achieve resistivity variation, the element includes a region of constant thickness surrounding the region having varied local resistivity, wherein the region having varied local resistivity is located in a central portion of the element and wherein the thickness of the element in the region having gradually varied local resistivity decreases radially from an interface with the region of constant thickness to the center of the element.
In those embodiments, where variation of thickness is used to achieve the variation of resistivity, the thickness variation is typically between about 3-100% of the greatest thickness of the element.
In some embodiments the element is substantially coextensive with the semiconductor substrate and has between about 6,000-12,000 non-communicating channels made in an ionically resistive material. The element is located in close proximity of the semiconductor substrate. Typically, the substrate-facing surface of the element is separated from a plating face of the semiconductor substrate by a gap of about 10 millimeters or less during electroplating. In some embodiments, the apparatus further includes an inlet to the gap for introducing electrolyte flowing to the gap and an outlet to the gap for receiving electrolyte flowing through the gap, wherein the inlet and the outlet are positioned proximate azimuthally opposing perimeter locations of the plating face of the substrate, and wherein the inlet and outlet are adapted to generate cross-flow of electrolyte in the gap.
In another aspect, a method of electroplating metal on a semiconductor substrate comprising a plurality of recessed features, is provided. The method includes: (a) providing the substrate to a plating chamber configured to contain an electrolyte and an anode while electroplating metal onto the substrate, wherein the plating chamber includes: (i) a substrate holder holding the substrate such that a plating face of the substrate is separated from the anode during electroplating, and (ii) an ionically resistive ionically permeable element comprising a substantially planar substrate-facing surface and an opposing surface, wherein the element allows for flow of ionic current through the element towards the substrate during electroplating, and wherein the element comprises a region having varied local resistivity; and (b) electroplating a metal onto the substrate plating surface while cathodically biasing and rotating the semiconductor substrate.
In another aspect an electroplating apparatus is provided, wherein the apparatus includes: (a) a plating chamber configured to contain an electrolyte and an anode while electroplating metal onto a semiconductor substrate; (b) a substrate holder configured to hold the semiconductor substrate such that a plating face of the substrate is separated from the anode during electroplating; (c) an ionically resistive ionically permeable element, wherein the element allows for flow of an ionic current through the element towards the substrate during electroplating, and wherein the element comprises an azimuthally asymmetric ionically permeable region having an average resistivity that is different (e.g., greater) from the average resistivity of the rest of the element. The azimuthally asymmetric region can be located over an azimuthal fraction of the porous portion of the elements' peripheral region. The azimuthally asymmetric region can either have a smaller but constant porosity (or density of holes) than the rest of the element, or the region can have a porosity that gradually varies within the region but taken as a whole has a substantially lower porosity than the rest of the element. Such electroplating apparatus can be used for improving azimuthal non-uniformity. In one aspect, a method for electroplating is provided, wherein the method involves providing a substrate into the electroplating apparatus described above, and electroplating metal on the substrate while rotating the substrate relative to the ionically resistive ionically permeable element such that a selected azimuthally asymmetric region on the substrate dwells over the azimuthally asymmetric region of the element having different resistivity than the rest of the element for a different amount of time than another region of the substrate having the same area, same average radial position, and same average arc length but residing at a different azimuthal (angular) position.
The methods provided herein can be integrated into the processes that employ photolithographic patterning. In one aspect, the methods include any of the methods described above and further include applying photoresist to the wafer substrate; exposing the photoresist to light; patterning the photoresist and transferring the pattern to the wafer substrate; and selectively removing the photoresist from the wafer substrate. In another aspect of the invention, a system is provided, which includes any of the apparatuses described above and a stepper.
In some embodiments, an apparatus is provided, wherein the apparatus further includes a controller comprising program instructions and/or logic for performing any of the methods described herein. In one aspect a non-transitory computer machine-readable medium comprising program instructions is provided. The program instructions for control of an electroplating apparatus comprise code for performing any of the methods described above.
These and other features and advantages of the present invention will be described in more detail below with reference to the associated drawings.
Methods and apparatus for electroplating a metal on a substrate with improved uniformity, such as with improved radial uniformity, azimuthal uniformity, or both, are provided. The methods are particularly useful for through resist plating in WLP applications, but are not limited to these applications. The methods can also be used for electroplating in other processing schemes, such as in TSV processing and in fabrication of integrated circuits using damascene processing. The methods and apparatus employ an ionically resistive ionically permeable element having spatially tailored resistivity to address various uniformity challenges, such as terminal effect and non-uniform thickness of photoresist in through resist plating. The use of provided methods and apparatuses can result, in many cases, in good within wafer uniformity of 5% or less, wherein the uniformity value refers to a ratio of variation in thickness of electrodeposited metal layer (thicknessmax−thicknessmin) to twice the average thickness.
Embodiments are described generally where the substrate is a semiconductor wafer, however the invention is not so limited. The terms “semiconductor wafer” and “semiconductor substrate” are used herein interchangeably and refer to a workpiece that contains semiconductor material, such as silicon, anywhere within the workpiece. Typically the semiconductor material in the semiconductor substrate is covered with one or more layers of other materials (e.g., dielectric and conductive layers). The substrates used for electroplating include a conductive seed layer which is exposed at least at some positions on the surface of the substrate. The seed layer is typically a layer of metal, and may be, for example, a copper layer (including pure copper and its alloys), a nickel layer (including NiB and NiP layers), a ruthenium layer, etc. The substrate typically has a number of recessed features on its surface that are filled during the electroplating process. Examples of metals that can be electroplated using provided methods include, without limitation, copper, silver, tin, indium, chromium, a tin-lead composition, a tin-silver composition, nickel, cobalt, nickel and/or cobalt alloys with each other and with tungsten, a tin-copper composition, a tin-silver-copper composition, gold, palladium, and various alloys which include these metals and compositions.
A schematic cross-sectional view of a substrate that undergoes WLP processing is shown in
The embodiments provided herein make use of an ionically resistive ionically permeable element that has spatially tailored resistivity to counteract the terminal effect. Specifically, the element can have a greater local resistivity in the peripheral portion of the element than in the central portion of the element. Such element can be used in electroplating apparatuses for electrodepositing metal on both fully-exposed seed layer and on partially exposed seed layer (e.g., in through resist plating). The use of such element is particularly advantageous in through resist plating on copper seed layers having thicknesses of less than 1,000 Å, such as between about 200-950 Å, or on seed layers that are made of more resistive metals than copper. In addition, the use of such elements is particularly advantageous when electroplating is conducted in an electrolyte having particularly high conductivity (e.g. a conductivity of 50 mS/cm or more), as high-conductivity electrolytes exacerbate the terminal effect. When electroplating is conducted on seed layers having very high sheet resistance and/or with electrolytes having extremely high conductivity, the terminal effect can be so great that it may not be adequately compensated with the use of a conventional ionically permeable ionically resistive element with uniform local resistivity. Or, such element would be required to have an extremely high thickness and/or low porosity that would be impossible to manufacture or fit into the electroplating apparatus. In these situations, the provided element having varied local resistivity would be an effective solution to the terminal effect problem.
Another uniformity problem encountered in through resist electroplating is non-uniform electrodeposition of metal due to variation of thickness of photoresist on a substrate. It was observed that electroplating of metal occurs at a lower rate in recessed features surrounded by thicker photoresist. Therefore, variations in photoresist thickness directly affect the uniformity of electrodeposition. Thinner metal layers are electrodeposited in recessed features surrounded by relatively thicker photoresist. Photoresist is typically deposited on a substrate by a spin-on method, and it can be inadvertently deposited in the central portion of the wafer substrate at a greater thickness than near the edge of the wafer substrate. Such center-thick deposition of photoresist, although undesired, is typically reproducible from wafer to wafer, and therefore non-uniform electroplating due to center-thick photoresist may be reliably addressed by using an ionically permeable ionically resistive element having varied local resistivity that compensates for the variation in photoresist thickness. Thus, an element that has lower local resistivity in the center than at the edge can be used to improve plating uniformity during electroplating on wafers having center-thick photoresist layers.
Generally, ionically resistive ionically permeable element with varied local resistivity can be used to address a variety of radial and azimuthal uniformity problems both in through resist plating and in other types of electroplating. Generally, the local resistivity of the element is spatially tailored in such a fashion as to provide higher local resistivity directly below the portion of the substrate, which would otherwise receive higher than needed ionic current (referring to plating face-down orientation). If the non-uniformity is azimuthal, and the substrate is rotated during electroplating, the rotation rate is adjusted such that the portion of the substrate that would otherwise receive higher than needed ionic current would dwell for a longer time over a region of the element that has higher resistivity than the rest of the element.
Ionically Resistive Ionically Permeable Element
The ionically resistive ionically permeable element (also referred to as “the element”) is a component of an electroplating apparatus that provides an additional resistance on the path of ionic current towards the cathodically biased wafer substrate, and that allows for movement of ions through the element towards the substrate during electroplating.
In some embodiments the element is a porous plate, where the body of the plate is made of a resistive material, and the pores in the resistive material (which may be non-communicating channels or interconnected networks of pores) allow for movement of the ions through the plate towards the cathodically biased substrate. The element has a substrate-facing surface that is preferably planar and parallel to the substrate, and an opposing surface, which does not need to be planar. The element is positioned in close proximity of the substrate, but does not contact the substrate. Preferably the element is positioned within about 10 mm of the substrate, more preferably within about 5 mm of the substrate, such as within about 2-3 mm of the substrate during electroplating, where this gap refers to a distance between the plating face of the substrate and the substrate-facing surface of the element.
The thickness and porosity of the element may vary throughout the body of the element. The maximum thickness of the element ranges, in some implementations, from between about 10 to about 50 mm, and the minimal porosity is typically in the range of between about 1-5%, and is preferably less than about 3%. If the element is a plate having non-communicating drilled channels, the porosity is determined as a ratio of the area of channel openings on the substrate-facing surface of the element to the total area of the substrate-facing surface of the element. If the element has 3-dimensional networks of pores, the porosity is determined as a ratio of the volume of the pores to the total volume of the element.
In some embodiments the pores of the element are non-communicating channels (e.g., drilled holes in a dielectric plate that do not interconnect within the plate). These through-holes are distinct from 3-D porous networks, where the channels extend in three dimensions and form interconnecting pore structures. An example of an element with non-communicating through holes is a disc made of an ionically resistive material, such as polyethylene, polypropylene, polyvinylidene difluoride (PVDF), polytetrafluoroethylene, polysulphone, polyvinyl chloride (PVC), polycarbonate, and the like, having between about 6,000-12,000 1-D through-holes. In some implementations the element may further serve an electrolyte flow-shaping function, and may allow for large volume of electrolyte to pass through the channels of its body and provide an impinging flow of electrolyte at the wafer surface. The diameters of the channels should not be larger than the distance between the substrate and the substrate-facing surface of the element, and typically the diameters should not exceed 5 mm. Typically, the diameters of the channels are in a range of between about 0.5-1 mm. For example the channels may have diameters of 0.508 mm or 0.66 mm. The channels may be directed at a 90 degree angle to the substrate-facing surface of the element, or at a different angle of incline.
In other embodiments the pores are three-dimensional networks interconnected within the body of the element and the element is made of a porous dielectric material such as porous silicon carbide, porous glass, and the like.
An ionically resistive ionically permeable element having varied local resistivity is illustrated in
In some embodiments the local resistivity in the element changes gradually. Gradual change is defined as the presence of at least four local resistivity values that increase or decrease along any vector on the substrate-facing surface of the element. In some embodiments, the vector is the radius of the substrate facing surface, as radius 203, shown in
Another embodiment of an element having varied local resistivity is illustrated in
The local resistivity of the element can be varied using a number of approaches. These approaches include varying the thickness and/or porosity of the element.
For example, when the element is a plate having a plurality of non-communicating channels, local resistivity is determined by equation (1):
R=L/(ρAK)=4L/(πρDK) (1),
wherein R is local resistivity, L is length of the channel, A is cross-sectional area of a channel, ρ is the density of channels, D is the diameter of channels, and K is conductivity of electrolyte within the channels.
When the channels are perpendicular to the substrate-facing surface of the element, the length of the channels at each location of the element is equal to the thickness of the element at this location (the distance between the substrate-facing surface of element and the opposite surface of the element). Therefore, the local resistivity in the element can be varied by varying the thickness of the element, while maintaining the local porosities at a constant value throughout the element.
One example of an element having varied thickness and varied local resistivity is shown in
Another example of an element having varied local resistivity is shown in
The local resistivity, as it can be seen from equation (1) can also be modulated by modulating the size of the channels (or diameter of the channels when channels are cylindrically shaped). In the illustration shown in
While in many embodiments the element includes only channels that are perpendicular to the substrate-facing surface of the element, in some embodiments it may be advantageous to use channels that have an angle of incline that is different from 90 degrees. The angle of incline is defined herein as an acute angle formed between the channel and the plane of the substrate-facing surface of the element. In some embodiments this angle is locally varied typically in the range of between about 35-90 degrees in order to achieve variation in local resistivity. The locations where channels are angled at smaller angles have relatively longer channels and consequently have greater resistivity. An example of an element having varied incline angles for the channels is shown in
The variation in local resistivity can also be achieved by variations of local porosity, wherein local porosity can be varied by varying the diameters of the channels, the density of the channels, or the combination of the two. Further, if the element contains networks of three-dimensional pores, the local porosity is varied by varying the volume occupied by these pores at various locations of the element. In some embodiments, the local porosity is increased in a radial direction from the edge of the element towards the center of the element. In some embodiments, the porosity may increase by about 10-200%, such as by 50-150%. For example, in some embodiments the local porosity at the edge of the element is about 4%, and is about 8% at the center of the element. The change may follow a variety of functions, including a linear function, and a second order polynomial function.
The principles illustrated above can be applied to any type of variation of local resistivity. For example local resistivity can be varied (e.g., by thickness variation, porosity variation or both) in a selected region of the element, rather than across the entire element as was shown in
It should be noted that the resistivity of the element, its thickness and porosity profile should be tailored to the type of wafer that is being processed. Thus, for example, an element that provides uniform plating on a 500 Å seed layer may provide non-uniform plating on a 300 Å seed layer. Similarly, an element that is tailored for uniform plating on center-thick photoresist layer can provide non-uniform plating on a uniform photoresist layer. The principles discussed herein (such as providing the element with more resistivity, and with more center-to-edge local resistivity variation for thinner seed layers, and providing more local resistivity for regions of the element directly below thicker photoresist) can be used to manufacture a variety of elements tailored for different types of substrates.
Apparatus
The ionically resistive ionically permeable element having varied local resistivity can be used in a variety of electroplating apparatuses, including wafer face-up and wafer face-down apparatuses. An example of a wafer face-down apparatus that can incorporate the provided element is Sabre 3D™ electroplating system available from Lam Research Corporation of Fremont, Calif. Generally, the electroplating apparatus includes an electroplating chamber configured to contain an electrolyte and an anode while electroplating metal onto a semiconductor substrate; a substrate holder configured to hold the semiconductor substrate such that a plating face of the substrate is separated from the anode during electroplating; and an ionically resistive ionically permeable element having a region of varied local resistivity, which was described in the previous section. The region of varied local resistivity can be coextensive with the element, or this region can be only a localized portion of the element.
One example of an apparatus, where the ionically resistive ionically permeable element has radially varied thickness throughout the element is presented in
The plating solution is continuously provided to plating bath 303 by a pump (not shown). In some embodiments, the plating solution flows upwards through the membrane 311 and through the ionically resistive ionically permeable element having varied local resistivity 317 located in close proximity of the wafer. In other embodiments, such as when the membrane 311 is largely impermeable to flow of the plating fluid (e.g. a nanoporous media such as a cationic membrane), the plating fluid enters the plating chamber between the membrane 311 and the element 317, for example at the chamber periphery, and then flows through the element. In this case, plating fluid within the anode chamber may be circulated and the pressure can be regulated separately from the cathode chamber. Such separate regulation is described, for example, in the U.S. Pat. No. 8,603,305, issued Dec. 10, 2013 and in the U.S. Pat. No. 6,527,920, issued Mar. 4, 2003, both of which are herein incorporated by reference in their entireties.
In the depicted example the element with varied resistivity 317 has varied thickness, wherein its thickness is gradually reduced in radial direction from the edge of the element towards the center of the element. Other types of the elements with varied local resistivities (such as elements with varied local porosity) can also be used. The arrows schematically show the plating current in the illustrated apparatus. The current originating from the anode 310 is directed upward, passes through the membrane 311 separating anolyte and catholyte compartments and through the element 317. In the depicted example the ionic current meets with lower resistance in the central portion of the plating chamber than at the edge of the plating chamber because the element 317 is thinner at the center. This mitigates the terminal effect and improves plating uniformity.
A DC power supply (not shown) is electrically connected with the wafer 305 and the anode 310, and is configured to negatively bias the wafer 305 and to positively bias the anode 310. The apparatus further includes a controller 319, which allows for modulation of current and/or potential provided to the elements of electroplating cell. The controller may include program instructions specifying current and voltage levels that need to be applied to various elements of the plating cell, as well as times at which these levels need to be changed. The controller can also include program instructions specifying the rates of electrolyte delivery and electrolyte composition, and the rates at which the substrate is rotated. Generally, the controller is electrically connected with the components of the plating apparatus, and can include program instructions or logic specifying any of the parameters of provided electroplating methods.
Additional Features of Provided Apparatus
In some embodiments it is preferable to equip the apparatus having the ionically resistive ionically permeable element with a manifold that provides for a cross-flow of electrolyte near the surface of the wafer. Such manifold is particularly advantageous for electroplating in relatively large recessed features, such as WLP or TSV features. In these embodiments the apparatus may include a flow shaping device positioned between the element and the wafer, where the flow-shaping device provides for a cross-flow substantially parallel to the surface of the wafer substrate. For example the flow shaping device may be an omega-shaped plate that directs the cross-flow towards an opening in the omega-shaped plate. A cross-sectional depiction of such configuration is illustrated in
The electroplating apparatus may further include one or more additional components that may help tune the uniformity of electrodeposition. For example, in some embodiments the apparatus further includes a thieving cathode positioned near the periphery of the substrate and configured to divert plating current from the near-edge portion of the substrate. In some embodiments the apparatus may further include one or more dielectric shields on the path of the plating current to restrict the current in the shielded area. These optional components are not shown in the illustration of the apparatus to preserve clarity.
Methods
Methods for electrodepositing metals with improved uniformity are provided. The process flow diagram presented in
Correction of Azimuthal Non-Uniformity
In some embodiments an ionically resistive ionically permeable element with varied local resistivity is used to improve azimuthal uniformity during electroplating. In some semiconductor substrates the distribution of recessed features is azimuthally non-uniform, which may lead to azimuthal non-uniformity of the electroplated layer. Other substrates may be azimuthally asymmetric due to a presence of a notch at the edge of the substrate. Such notch can lead to azimuthally non-uniform distribution of ionic current over the substrate, with current crowding being present near the notch.
In some embodiments azimuthal non-uniformity is corrected using an ionically resistive ionically permeable element having an azimuthally asymmetric region that has an average resistivity that is different from the average resistivity of the rest of the element. The area of this region (referring to the area of the substrate-facing surface) should be at least 0.35% of the total area of the substrate-facing surface of the element. An example of such element is illustrated in
The uniformity of copper electroplating on a circular substrate having a diameter of 300 mm and a copper seed layer having a thickness of 500 Å, was studied using computational modeling.
Referring to
Curve (a) on
t=0.38649858−0.00052899r−0.01118511r2 (2),
This is a second-order polynomial equation, where t is the thickness of the element, and r is the radial position. The porosity of the element is uniform and is equal to 4%.
Curve (b) was obtained by modeling using the same parameters, but the ionically resistive ionically permeable element has a uniform resistivity, a uniform thickness of 12.5 mm and its wafer-facing surface and the opposing surface are both flat and parallel to each other.
Curve (c) was obtained by modeling using the same parameters, but the ionically resistive ionically permeable element has a uniform resistivity, a uniform thickness of 12.5 mm and both its wafer-facing surface and the opposing surface are convex. The distance from the wafer-facing surface of the element to the plating surface of the wafer is 4.5 mm in the center of the element, and is 13 mm at the edge of the wafer.
It can be seen from the curves (a), (b), and (c), that curve (a) which corresponds to electroplating with an element having varied local resistivity results in the most uniform radial distribution of the plating current. The most pronounced gains in plating uniformity (in comparison with elements having uniform resistivity) are obtained in the center and mid-radius range.
Referring to
Curve (a) on
Curve (b) was obtained by modeling using the same parameters, but the ionically resistive ionically permeable element has a uniform porosity of 4%.
Curve (c) was obtained by modeling using the same parameters, but the ionically resistive ionically permeable element has a uniform porosity of 8%.
It can be seen from the curves (a), (b), and (c) that curve (a) which corresponds to electroplating with an element having varied local resistivity results in the most uniform radial distribution of the plating current. The most pronounced gains in uniformity (in comparison with elements having uniform resistivity) are obtained in the center and mid-radius range.
It can be seen from
Controller
In some implementations, a controller is part of a system, which may be part of the above-described examples. Such systems can comprise semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems. The controller, depending on the processing requirements and/or the type of system, may be programmed to control any of the processes disclosed herein, including the parameters of delivery of power to primary anode, secondary electrode, and the substrate. Specifically, the controller may provide instructions for timing of application of power, level of power applied, etc.
Broadly speaking, the controller may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, circuits, and/or dies of a wafer.
The controller, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus as described above, the controller may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.
Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and/or manufacturing of semiconductor wafers.
As noted above, depending on the process step or steps to be performed by the tool, the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.
The apparatus/process described hereinabove may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels and the like. Typically, though not necessarily, such tools/processes will be used or conducted together in a common fabrication facility. Lithographic patterning of a film typically comprises some or all of the following steps, each step enabled with a number of possible tools: (1) application of photoresist on a workpiece, i.e., substrate, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or UV curing tool; (3) exposing the photoresist to visible or UV or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove resist and thereby pattern it using a tool such as a wet bench; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.
This application is a continuation of U.S. application Ser. No. 14/712,553 filed May 14, 2015 titled “Apparatus and Method for Electrodeposition of Metals with the Use of an Ionically Resistive Ionically Permeable Element Having Spatially Tailored Resistivity”, naming Kagajwala et al. as inventors, which is herein incorporated by reference in its entirety.
| Number | Name | Date | Kind |
|---|---|---|---|
| 3652442 | Powers et al. | Mar 1972 | A |
| 3706651 | Leland | Dec 1972 | A |
| 3862891 | Smith | Jan 1975 | A |
| 4033833 | Bestel et al. | Jul 1977 | A |
| 4082638 | Jumer | Apr 1978 | A |
| 4240886 | Hodges et al. | Dec 1980 | A |
| 4272335 | Combs | Jun 1981 | A |
| 4304641 | Grandia et al. | Dec 1981 | A |
| 4389297 | Korach | Jun 1983 | A |
| 4409339 | Matsuda et al. | Oct 1983 | A |
| 4469564 | Okinaka et al. | Sep 1984 | A |
| 4545877 | Hillis | Oct 1985 | A |
| 4604177 | Siyilotti | Aug 1986 | A |
| 4604178 | Flegener et al. | Aug 1986 | A |
| 4605482 | Shirgami et al. | Aug 1986 | A |
| 4696729 | Santini | Sep 1987 | A |
| 4828654 | Reed | May 1989 | A |
| 4906346 | Hadersbeck et al. | Mar 1990 | A |
| 4931149 | Stierman et al. | Jun 1990 | A |
| 4933061 | Kulkarni et al. | Jun 1990 | A |
| 5000827 | Schuster et al. | Mar 1991 | A |
| 5035784 | Anderson et al. | Jul 1991 | A |
| 5039381 | Mullarkey | Aug 1991 | A |
| 5078852 | Yee et al. | Jan 1992 | A |
| 5096550 | Mayer et al. | Mar 1992 | A |
| 5146136 | Ogura et al. | Sep 1992 | A |
| 5156730 | Bhatt et al. | Oct 1992 | A |
| 5162079 | Brown | Nov 1992 | A |
| 5217586 | Datta et al. | Jun 1993 | A |
| 5316642 | Young, Jr. et al. | May 1994 | A |
| 5332487 | Young et al. | Jul 1994 | A |
| 5368711 | Poris | Nov 1994 | A |
| 5391285 | Lytle et al. | Feb 1995 | A |
| 5421987 | Tzanavaras et al. | Jun 1995 | A |
| 5443707 | Mori | Aug 1995 | A |
| 5452053 | Nozue | Sep 1995 | A |
| 5472592 | Lowery | Dec 1995 | A |
| 5476578 | Forand | Dec 1995 | A |
| 5498325 | Nishimura et al. | Mar 1996 | A |
| 5516412 | Andricacos et al. | May 1996 | A |
| 5567300 | Datta et al. | Oct 1996 | A |
| 5660699 | Saito et al. | Aug 1997 | A |
| 5723028 | Poris | Mar 1998 | A |
| 5744019 | Ang | Apr 1998 | A |
| 5816900 | Nagahara et al. | Oct 1998 | A |
| 5935402 | Fanti | Aug 1999 | A |
| 6004440 | Hanson et al. | Dec 1999 | A |
| 6027631 | Broadbent | Feb 2000 | A |
| 6080291 | Woodruff et al. | Jun 2000 | A |
| 6106687 | Edelstein | Aug 2000 | A |
| 6126798 | Reid et al. | Oct 2000 | A |
| 6132587 | Jorné et al. | Oct 2000 | A |
| 6132805 | Moslehi | Oct 2000 | A |
| 6156167 | Patton et al. | Dec 2000 | A |
| 6179983 | Reid et al. | Jan 2001 | B1 |
| 6193860 | Weling | Feb 2001 | B1 |
| 6228231 | Uzoh | May 2001 | B1 |
| 6251255 | Copping et al. | Jun 2001 | B1 |
| 6261433 | Landau | Jul 2001 | B1 |
| 6368475 | Hanson et al. | Apr 2002 | B1 |
| 6391166 | Wang | May 2002 | B1 |
| 6391188 | Goosey | May 2002 | B1 |
| 6395152 | Wang | May 2002 | B1 |
| 6398926 | Mahneke | Jun 2002 | B1 |
| 6402923 | Mayer et al. | Jun 2002 | B1 |
| 6497801 | Woodruff et al. | Dec 2002 | B1 |
| 6521102 | Dordi | Feb 2003 | B1 |
| 6527920 | Mayer et al. | Mar 2003 | B1 |
| 6551483 | Mayer et al. | Apr 2003 | B1 |
| 6569299 | Reid et al. | May 2003 | B1 |
| 6627051 | Berner et al. | Sep 2003 | B2 |
| 6632335 | Kunisawa et al. | Oct 2003 | B2 |
| 6692588 | Uzoh et al. | Feb 2004 | B1 |
| 6755954 | Mayer et al. | Jun 2004 | B2 |
| 6773571 | Mayer et al. | Aug 2004 | B1 |
| 6800187 | Reid et al. | Oct 2004 | B1 |
| 6821407 | Reid et al. | Nov 2004 | B1 |
| 6890416 | Mayer et al. | May 2005 | B1 |
| 6919010 | Mayer et al. | Jul 2005 | B1 |
| 6921468 | Graham et al. | Jul 2005 | B2 |
| 6964792 | Mayer et al. | Nov 2005 | B1 |
| 7070686 | Contolini et al. | Jul 2006 | B2 |
| 7141146 | Bogart et al. | Nov 2006 | B2 |
| 7169705 | Ide et al. | Jan 2007 | B2 |
| D544452 | Nakamura et al. | Jun 2007 | S |
| D548705 | Hayashi | Aug 2007 | S |
| D552565 | Nakamura et al. | Oct 2007 | S |
| D553104 | Oohashi et al. | Oct 2007 | S |
| D587222 | Sasaki et al. | Feb 2009 | S |
| 7622024 | Mayer et al. | Nov 2009 | B1 |
| 7641776 | Nagar et al. | Jan 2010 | B2 |
| D609652 | Nagasaka et al. | Feb 2010 | S |
| D609655 | Sugimoto | Feb 2010 | S |
| 7670465 | Yang et al. | Mar 2010 | B2 |
| D614593 | Lee et al. | Apr 2010 | S |
| 7837841 | Chen et al. | Nov 2010 | B2 |
| 7854828 | Reid et al. | Dec 2010 | B2 |
| 7935240 | Singh et al. | May 2011 | B2 |
| 7967969 | Mayer et al. | Jun 2011 | B2 |
| D648289 | Mayer et al. | Nov 2011 | S |
| 8308931 | Reid et al. | Nov 2012 | B2 |
| 8475636 | Mayer et al. | Jul 2013 | B2 |
| 8475644 | Mayer et al. | Jul 2013 | B2 |
| 8603305 | Rash et al. | Dec 2013 | B2 |
| 8623193 | Mayer et al. | Jan 2014 | B1 |
| 8795480 | Mayer et al. | Aug 2014 | B2 |
| 9309604 | Mayer et al. | Apr 2016 | B2 |
| 9670588 | He | Jun 2017 | B2 |
| 9816194 | He et al. | Nov 2017 | B2 |
| 10014170 | Kagajwala et al. | Jul 2018 | B2 |
| 10301739 | He | May 2019 | B2 |
| 20010050233 | Uzoh et al. | Dec 2001 | A1 |
| 20020008037 | Wilson et al. | Jan 2002 | A1 |
| 20020017456 | Graham et al. | Feb 2002 | A1 |
| 20020020627 | Kunisawa et al. | Feb 2002 | A1 |
| 20020119671 | Lee | Aug 2002 | A1 |
| 20020125141 | Wilson et al. | Sep 2002 | A1 |
| 20030029527 | Yajima et al. | Feb 2003 | A1 |
| 20030038035 | Wilson et al. | Feb 2003 | A1 |
| 20030079995 | Contolini et al. | May 2003 | A1 |
| 20030087522 | Ngo et al. | May 2003 | A1 |
| 20030102210 | Woodruff et al. | Jun 2003 | A1 |
| 20030199156 | Fujii | Oct 2003 | A1 |
| 20030201166 | Zheng et al. | Oct 2003 | A1 |
| 20040026257 | Gonzalez et al. | Feb 2004 | A1 |
| 20040149584 | Nagai et al. | Aug 2004 | A1 |
| 20050145499 | Kovarsky et al. | Jul 2005 | A1 |
| 20050202346 | Yamano | Sep 2005 | A1 |
| 20060000704 | Sato et al. | Jan 2006 | A1 |
| 20060243598 | Singh et al. | Nov 2006 | A1 |
| 20070029193 | Brcka | Feb 2007 | A1 |
| 20070068819 | Singh et al. | Mar 2007 | A1 |
| 20070238265 | Kurashina et al. | Oct 2007 | A1 |
| 20100032304 | Mayer et al. | Feb 2010 | A1 |
| 20100032310 | Reid et al. | Feb 2010 | A1 |
| 20100044236 | Mayer et al. | Feb 2010 | A1 |
| 20100116672 | Mayer et al. | May 2010 | A1 |
| 20110031112 | Birang et al. | Feb 2011 | A1 |
| 20120000786 | Mayer et al. | Jan 2012 | A1 |
| 20120261254 | Reid et al. | Oct 2012 | A1 |
| 20130137242 | He et al. | May 2013 | A1 |
| 20130313123 | Abraham et al. | Nov 2013 | A1 |
| 20130327650 | Mayer et al. | Dec 2013 | A1 |
| 20140124361 | Reid et al. | May 2014 | A1 |
| 20140326608 | He | Nov 2014 | A1 |
| 20160222535 | Zhou et al. | Aug 2016 | A1 |
| 20160273119 | He et al. | Sep 2016 | A1 |
| 20160333495 | Kagajwala et al. | Nov 2016 | A1 |
| 20170236715 | He | Aug 2017 | A1 |
| Number | Date | Country |
|---|---|---|
| 1582491 | Feb 2005 | CN |
| 1624207 | Jun 2005 | CN |
| 1705774 | Dec 2005 | CN |
| 101056718 | Oct 2007 | CN |
| 100487855 | May 2009 | CN |
| 101736376 | Jun 2010 | CN |
| 101925981 | Dec 2010 | CN |
| 102296344 | Dec 2011 | CN |
| 301883011 | Apr 2012 | CN |
| 102459717 | May 2012 | CN |
| 102560612 | Jul 2012 | CN |
| 102732925 | Oct 2012 | CN |
| 104131327 | Nov 2014 | CN |
| 0037325 | Mar 1981 | EP |
| 59-162298 | Sep 1984 | JP |
| 09-53197 | Feb 1997 | JP |
| 2001-316887 | Nov 2001 | JP |
| 2003-268591 | Sep 2003 | JP |
| 10-2006-0043811 | May 2006 | KR |
| 1020060048645 | May 2006 | KR |
| 10-0707121 | Apr 2007 | KR |
| 0657600 | Aug 2012 | KR |
| 223678 | Nov 2004 | TW |
| 201107536 | Mar 2011 | TW |
| D148167 | Jul 2012 | TW |
| WO 1999041434 | Aug 1999 | WO |
| WO 2005043593 | May 2005 | WO |
| WO 2010144330 | Dec 2010 | WO |
| Entry |
|---|
| U.S. Office Action dated Aug. 26, 2016 issued in U.S. Appl. No. 14/251,108. |
| U.S. Notice of Allowance dated Feb. 3, 2017 issued in U.S. Appl. No. 14/251,108. |
| U.S. Notice of Allowance [Corrected Notice of Allowability] dated May 10, 2017 issued in U.S. Appl. No. 14/251,108. |
| U.S. Notice of Allowance dated Jul. 19, 2017 issued in U.S. Appl. No. 14/662,823. |
| U.S. Office Action dated Feb. 23, 2017 issued in U.S. Appl. No. 14/712,553. |
| U.S. Final Office Action dated Oct. 3, 2017 issued in U.S. Appl. No. 14/712,553. |
| U.S. Notice of Allowance dated Mar. 2, 2018 issued in U.S. Appl. No. 14/712,553. |
| U.S. Office Action dated Oct. 26, 2007 issued in U.S. Appl. No. 11/040,359. |
| U.S. Final Office Action dated Jul. 25, 2008 issued in U.S. Appl. No. 11/040,359. |
| U.S. Office Action dated Jan. 8, 2009 issued in U.S. Appl. No. 11/040,359. |
| U.S. Notice of Allowance dated Jul. 20, 2009 issued in U.S. Appl. No. 11/040,359. |
| U.S. Office Action dated Oct. 6, 2010 issued in U.S. Appl. No. 12/578,310. |
| U.S. Notice of Allowance dated Mar. 4, 2011 issued in U.S. Appl. No. 12/578,310. |
| U.S. Office Action dated Oct. 5, 2012 issued in U.S. Appl. No. 13/110,759. |
| U.S. Final Office Action dated Mar. 29, 2013 issued in U.S. Appl. No. 13/110,759. |
| U.S. Notice of Allowance dated Sep. 11, 2013 issued in U.S. Appl. No. 13/110,759. |
| U.S. Office Action dated Sep. 19, 2011 issued in U.S. Appl. No. 12/291,356. |
| U.S. Final Office Action dated Feb. 27, 2012 issued in U.S. Appl. No. 12/291,356. |
| U.S. Notice of Allowance dated Jul. 27, 2012 issued in U.S. Appl. No. 12/291,356. |
| U.S. Office Action dated Jun. 24, 2011 issued in U.S. Appl. No. 12/481,503. |
| U.S. Final Office Action dated Mar. 1, 2012 issued in U.S. Appl. No. 12/481,503. |
| U.S. Office Action dated Jul. 9, 2012 issued in U.S. Appl. No. 12/481,503. |
| U.S. Final Office Action dated Dec. 19, 2012 issued in U.S. Appl. No. 12/481,503. |
| U.S. Notice of Allowance dated Mar. 1, 2013 issued in U.S. Appl. No. 12/481,503. |
| U.S. Office Action dated Jun. 24, 2011 issued in U.S. Appl. No. 12/606,030. |
| U.S. Final Office Action dated Mar. 1, 2012 issued in U.S. Appl. No. 12/606,030. |
| U.S. Office Action dated Jun. 28, 2012 issued in U.S. Appl. No. 12/606,030. |
| U.S. Office Action dated Jul. 13, 2012 issued in U.S. Appl. No. 12/606,030. |
| U.S. Final Office Action dated Dec. 17, 2012 issued in U.S. Appl. No. 12/606,030. |
| U.S. Notice of Allowance dated Mar. 1, 2013 issued in U.S. Appl. No. 12/606,030. |
| U.S. Office Action dated Jul. 29, 2015 issued in U.S. Appl. No. 13/907,265. |
| U.S. Notice of Allowance dated Dec. 30, 2015 issued in U.S. Appl. No. 13/907,265. |
| U.S. Office Action, dated May 23, 2013, issued in U.S. Appl. No. 13/108,881. |
| U.S. Final Office Action, dated Oct. 25, 2013, issued in U.S. Appl. No. 13/108,881. |
| U.S. Office Action, dated Oct. 22, 2015, issued in U.S. Appl. No. 14/153,582. |
| U.S. Office Action, dated May 9, 2016, issued in U.S. Appl. No. 14/153,582. |
| U.S. Office Action, dated Dec. 2, 2016, issued in U.S. Appl. No. 14/153,582. |
| U.S. Notice of Allowance dated Aug. 10, 2011 issued in Design U.S. Appl. No. 29/377,521. |
| Chinese First Office Action dated Jan. 29, 2016 issued in Application No. CN 201410183216.6. |
| Chinese Second Office Action dated Sep. 27, 2016 issued in Application No. CN 201410183216.6. |
| Chinese Third Action dated Mar. 28, 2017 issued in Application No. CN 201410183216.6. |
| Chinese First Office Action dated Oct. 20, 2017 issued in Application No. CN 201610318396.3.1. |
| Chinese First Office Action dated May 15, 2013 issued in Application No. CN 200910209697.2. |
| Chinese Second Office Action dated Dec. 10, 2013 issued in Application No. CN 200910209697.2. |
| PCT International Search Report and Written Opinion dated Jan. 12, 2011 issued in Application No. PCT/US2010/037520. |
| PCT International Preliminary Report on Patentability and Written Opinion dated Dec. 22, 2011 issued in Application No. PCT/US2010/037520. |
| Chinese First Office Action dated Nov. 6, 2013 issued in Application No. CN 201080032109.3. |
| Chinese Second Office Action dated Jun. 10, 2014 issued in Application No. CN 201080032109.3. |
| Korean First Office Action dated Jun. 23, 2016 issued in Application No. KR 10-2012-7000614. |
| Taiwan Office Action dated Jul. 31, 2014 issued in Application No. TW 099118603. |
| Chinese First Office Action dated Jul. 20, 2015 issued in Application No. CN 201210108100.7. |
| Chinese Second Office Action dated Feb. 25, 2016 issued in Application No. CN 201210108100.7. |
| Taiwan Office Action dated Jan. 20, 2016 issued in Application No. TW 101113319. |
| Chinese Office Action dated Jul. 19, 2011 issued in Application No. CN 201130081716.6. |
| Taiwan Office Action dated Nov. 28, 2011 issued in Application No. TW 100301923. |
| Korean Office Action dated Apr. 20, 2012 issued in Application No. KR 2011-0012881. |
| Fang et al. (2004) “Uniform Copper Electroplating on Resistive Substrates,” Abs. 167, 205th Meeting, The Electrochemical Society, Inc., 1 page. |
| Malmstadt et al. (1994) “Microcomputers and Electronic Instrumentation: Making the Right Connections,” American Chemical Society, p. 255 (3pp). |
| “Release of Sabre™ electrofill tool with HRVA by Novellus Systems, Inc.” no earlier than Aug. 2005. (3 pages). |
| U.S. Notice of Allowance dated Jan. 23, 2019 issued in U.S. Appl. No. 15/583,592. |
| Taiwanese First Office Action dated May 16, 2018 issued in Application No. TW 103115586. |
| Chinese Second Office Action dated Nov. 5, 2018 issued in Application No. CN 201610318396.3. |
| Taiwanese First Office Action dated Dec. 18, 2019 issued in Application No. TW 105114493. |
| Korean Office Action dated May 9, 2018 issued in Application No. KR 10-2012-0038891. |
| Chinese First Office Action dated Apr. 28, 2019 issued in Application No. CN 201810195785.0. |
| Taiwanese Second Office Action dated Aug. 31, 2020 issued in Application No. TW 105114493. |
| Korean Office Action dated Sep. 1, 2020 issued in Application No. KR 10-2014-0052594. |
| Number | Date | Country | |
|---|---|---|---|
| 20180286660 A1 | Oct 2018 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 14712553 | May 2015 | US |
| Child | 15995974 | US |
