Claims
- 1. A test structure that is designed for voltage contrast inspection, comprising:
a first substructure having a plurality of floating conductive structures that are designed to charge to a first potential during a voltage contrast inspection; and a second substructure that is coupled with a conductive structure having a size selected to cause the second substructure to charge to a second potential that differs from the first potential during the voltage contrast inspection.
- 2. A test structure as recited in claim 1, wherein the first and second substructure are formed in a single photolithography step.
- 3. A test structure as recited in claim 1, wherein the first and second substructure are not coupled to the substrate.
- 4. A test structure as recited in claim 1, wherein the first and second substructure are both on a same level.
- 5. A test structure as recited in claim 1, wherein the second substructure includes a plurality of parallel strip segments that are each adjacent to a one of the conductive lines of the first substructure.
- 6. A test structure as recited in claim 5, wherein the second substructure forms a serpentine shape.
- 7. A test structure as recited in claim 1, wherein the second substructure is designed to charge more slowly than the first substructure during a voltage contrast inspection.
- 8. A test structure as recited in claim 1, wherein the second substructure is designed to have a different intensity level than the first substructure during a voltage contrast inspection.
- 9. A test structure as recited in claim 1, wherein the conductive structure of the second substructure has a size selected so that a partial open may be detected within the second substructure during the voltage contrast inspection.
- 10. A method of fabricating a test structure that is designed for voltage contrast inspection, comprising:
forming a first substructure having a plurality of floating conductive structures that are designed to charge to a first potential when they are scanned with an electron beam; and forming a second substructure that is coupled with a conductive structure having a size selected to cause the second substructure to charge to a second potential that differs from the first potential when it is scanned with the electron beam, wherein the first and second substructures are both formed within a single photolithography step.
- 11. A method as recited in claim 10, wherein the first and second substructure are formed in a single photolithography step.
- 12. A method as recited in claim 10, wherein the first and second substructure are not coupled to the substrate.
- 13. A method as recited in claim 10, wherein the first and second substructure are both on a same level.
- 14. A method as recited in claim 10, wherein the second substructure includes a plurality of parallel strip segments that are each adjacent to a one of the conductive lines of the first substructure.
- 15. A method as recited in claim 14, wherein the second substructure forms a serpentine shape.
- 16. A method as recited in claim 10, wherein the second substructure is designed to charge more slowly than the first substructure during a voltage contrast inspection.
- 17. A method as recited in claim 10, wherein the second substructure is designed to have a different intensity level than the first substructure during a voltage contrast inspection.
- 18. A method as recited in claim 10, wherein the conductive structure of the second substructure has a size selected so that a partial open may be detected within the second substructure during the voltage contrast inspection.
- 19. A method as recited in claim 10, further comprising inspecting the first and second substructures by scanning a portion of such substructures with an electron beam and obtaining a voltage contrast image of such scanned portion.
- 20. A method as recited in claim 19, further comprising determining whether there is a defect present within the first and/or second substructure based on the voltage contrast image and when a defect is present, determining a position of such defect by stepping the electron beam to various portions of the first and/or second substructures.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation-in-part and claims priority of U.S. patent application Ser. No. 09/648,380 (Attorney Docket No. KLA1P016B), entitled TEST STRUCTURES AND METHODS FOR INSPECTION OF SEMICONDUCTOR INTEGRATED CIRCUITS, filed Aug. 25, 2000, by Akella V. S. Satya et al., which application is incorporated herein by reference in its entirety for all purposes.
Provisional Applications (1)
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Number |
Date |
Country |
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60329804 |
Oct 2001 |
US |
Continuation in Parts (1)
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Number |
Date |
Country |
| Parent |
09648380 |
Aug 2000 |
US |
| Child |
10265051 |
Oct 2002 |
US |