Patent Application
20230268249
This application claims priority under 35 U.S.C. §119 to European Patent Application No. 22305205.1, filed on Feb. 24, 2022, in the European Patent Office, the entire contents of which are hereby incorporated by reference.
Various example embodiments relate to embodiments of an apparatus for integrating an electronic integrated circuit, hereafter abbreviated by EIC and a photonic integrated circuit, hereafter abbreviated by PIC. More particularly, various embodiments relate to enabling effective thermal management temperature control and heat removal.
Integrated Photonics is considered to be one of the most important key technologies for a broad range of applications in many fields, such as health, environmental monitoring, telecom, datacom, transport, manufacturing, etc. Innovative products benefit from highly integrated photonic circuits comprising light sources (lasers), detectors and sensors as well as integrated electronics for driving those photonic components or processing the acquired signals. These integration efforts come together with a constant need for higher switching frequencies, especially in telecom.
One of the main obstacles to the dense and advanced integration of photonic and related electronic components into a single photonic integrated circuit (PIC) is the parasitic and detrimental thermal crosstalk effects between the integrated devices.
It is known by those skilled in the art, to realize thermal management of EIC-INTEGRATED PICs by means of a smart micro-thermoelectric coolers (µTECs) integrated circuit (TEIC) layer, sitting above a functional layer containing advanced electronic integrated circuits (EICs), allowing smaller footprint PIC and lower energy consumption.
Thus, considering the foregoing, there is growing interest in a smart thermal management solution consisting in a new approach.
Various embodiments provide apparatuses and method to remedy some or all the disadvantages of the above identified prior art.
The embodiments and features described in this specification which, if any, would fall outside the scope of the independent claims are to be interpreted as useful examples for understanding the various embodiments.
A general embodiment relates to an apparatus integrating an Electronic Integrated Circuit (EIC) and at least one photonic-integrated circuit (PIC), said apparatus further comprising:
The apparatus of the general embodiment allows the design and implementation of a common technology platform for various photonic integrated circuits (PICs) for various application areas such as fibre optic environmental sensing and very highspeed transceivers for the telecommunications and data communications industries, using either the coherent format or other wavelength division multiplexing systems (also called WDM systems).
Advantageously, the apparatus according to the general embodiment may further comprise an array of heat-dissipating fins (64) situated on the top side of the top wall of the lid.
Advantageously, the lid and, if applicable, the heat-dissipating fins may be made of a thermally conductive material, preferably consisting of a metal or silicon.
Advantageously, the Electronic Integrated circuit may further comprise at least one heat generating component that is an electric or electronic component from the Electronic Integrated Circuit (EIC), that is either positioned on the top side of the first substrate (i.e. the glass substrate) or on the bottom side of the first substrate.
The at least one heat generating component from the photonic-integrated circuit may be selected among usual III-V-based devices (such as laser active sections, SOAs, photodiodes or phase modulators) and Si-based devices (phase modulators, ring-resonators, Ge-based PDs).
Advantageously, the at least one heat generating component from the photonic-integrated circuit may comprise a III-V-based device.
The apparatus of the general embodiment may further comprise:
Advantageously, according to a first specific embodiment of the general embodiment, said at least one photonic integrated circuit may comprise:
The at least electrical interconnection plane may be a RF and/or DC inputs/outputs plane positioned on the upper side of said first substrate and/or said second electrical interconnection plane may be a RF and/or DC inputs/outputs plane.
Advantageously, the apparatus according to the general embodiment may further comprise an organic substrate being positioned beneath the first substrate.
Advantageously, according to a second specific embodiment, the Electronic Integrated circuit may further comprise at least one heat generating component being an electric or electronic component from the Electronic Integrated Circuit (EIC)being positioned on the bottom side of the first substrate and electrically connected to said electrical interconnection plane by means of Through-Glass-Vias traversing the first substrate.
Some example embodiments are now described, by way of example only, and with reference to the accompanying drawings in which:
The same reference number represents the same element or the same type of element on all drawings, unless stated otherwise.
Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are illustrated. In the figures, the thicknesses of lines, layers or regions may be exaggerated for clarity.
Accordingly, while example embodiments are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the figures and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments to the forms disclosed, but on the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of the claims.
Like numbers refer to like or similar elements throughout the description of the figures.
In the following description of the figures, schematic representations are non-limiting and serve only for the understanding.
In particular,
The III-V-based die 510 from the PIC 51 and electric or electronic component 50 from the EIC are flip-chip bonded on the glass platform 40 through the pads (also called flip-chip balls) contacting the electrical interconnection plane 20.
It is to be remarked that also other types of PICs can be part of such apparatus, e.g. PICs for transceiver applications, containing many types of photonic devices, including lasers (DFB, extended cavity tunable lasers, frequency combs etc.), optical amplifiers (SOAs), modulators (electro-absorption modulators, Mach-Zehnder modulators, ring-resonator modulators, etc.), photodetectors (any type of photodiodes), on top of passive devices (single mode waveguides, wave couplers, multimode interferometer couplers (MMIs), mode transition tapers, Bragg grating couplers or edge couplers for optical in/outs, etc.); PICs for quantum applications, containing many of the above mentioned photonic devices, plus high finesse optical filters, variable optical attenuators, cascaded ring resonators, etc.; PICs for optical switching and routing, containing many of the above-mentioned photonic devices, plus optical switches, passive waveguide crossings, etc. The above-mentioned PIC types are not exhaustive.
The lid 6 defines a lidded cavity 63 comprised between the top wall 61, the side wall 62 and the SOI layer 41, such that the III-V-based die 510, the Si-based optical modulator and the EIC are inside this cavity, and the optical inputs/outputs 30 and the electrical inputs/outputs of the apparatus on the electrical interconnection plane 20 are outside the lidded cavity 63,
The lid 6 and the heat-dissipating fins 64 are preferably made of a thermally conductive material, such as a metal or silicon.
Metal vias 9 consisting of Through-Substrate-Vias hereinafter designated by TSV, traverse the silicon-on-insulator (SOI) layer 41 for electrically connecting the III-V-based device 510 and the Si-based optical modulator 511 to the EIC 2 via the electrical interconnection plane 20.
Furthermore, the III-V laser die 510 is also electrically connected via such TGV metal vias.
In addition an organic substrate 42 is present on the bottom surface of the glass platform 40, to which it is attached by means of regularly spaced bumps or an underfill.
As one can observe from
As earlier mentioned, secondary vias 95 traversing said III-V laser die 510 are present for electrically connecting the III-V laser die to the TGV metal vias 9.
A thermal conductive, yet electrical insulating thin layer (such as AlN) 72 may be positioned between this thermal management layer 8 (TEC) and the functional layer 51.
In some embodiments, the TEC may be needed to be electrically driven, via further electrical contacts and interconnections between the TEC 8 and the electrical interconnection layer on the upper surface of the glass platform 40.
As to the electric or electronic component 50 from the EIC 2, the apparatus according 1 to this first specific embodiment further comprises a third thermal interface (TIM) 70 being positioned between the bottom side of the top wall 61 of the lid 6 and the electric or electronic component 50.
The TGVs 10 may be drilled in the glass substrate 40. Since ordinary glass is used, cylindrical holes 10 can be drilled and filled with metal in order to provide DC signals to circuits from the second interconnection plane 20′ on the rear (down) side of the glass platform 40.
This variant has the advantage of doubling the surface for electrical routing, which can help the decrease the overall footprint of the integrated circuits system. Indeed, due to larger (and increasing) number of devices in PICs and EICs, electrical routing fan-out and the global size of the integrated system is bounded by the peripheral electrical I/O pad distribution. Providing this pad distribution on two levels (at both sides of the glass platform) instead of only one level (only the upper surface as in the previous embodiment) does have the advantage of decreasing the global horizontal footprint of the whole system. For practical and obvious reasons, it is better to use the upper surface for RF routing and I/O pads 20 since this reduces the RF line length.
In that configuration, the interconnection layer is a RF and DC inputs/outputs plane that is set on the upper side of the glass platform 40 to benefit from the low RF propagation loss. This configuration can present other advantages as the heat generating EICs 50 are further away from the temperature sensitive devices on the PIC 51, the heat insulation is better in this third embodiment, than in the first and second embodiments. In this third embodiment, the SOI thickness is comprised between 150 µm and 750 µm.
In some further variants of all these three specific embodiments, the upper surface of the PIC 51 can further be used for DC line routing and can provide DC pads at its peripheral sides, thus providing in this way an additional electrical interconnection layer, further contributing in reducing the overall size of the integrated system. This feature is not represented in any of
| Number | Date | Country | Kind |
|---|---|---|---|
| 22305205.1 | Feb 2022 | EP | regional |
