In the fabrication of low-voltage field-effect transistors, at least one body doping which corresponds to the doping of the channel zone is generated in the substrate. In a later step, the gate oxide is produced, typically through oxidation. In addition, the gate is produced, e.g., by means of applying and structuring a polysilicon layer, which is then structured, optionally together with the gate oxide.
Only subsequent to this structuring is the so-called LDD (=Lightly Doped Drain) implantation performed, with which a shallow doping is generated with a dopant of the second conductivity type in the source and drain region of low-voltage transistors and preferably also high-voltage transistors.
In a narrowed implantation region, the relatively high terminal doping of the second conductivity type then is produced for the source and drain connection, wherein the narrowed implantation region can be produced in a simple way by forming a spacer on the gate stack, which is formed from gate oxide and polysilicon gate.
For a semiconductor process with different gate oxide thicknesses, there is the problem that in the structuring of the gate stack, the gate oxide is not completely removed in the area of the LDD doping to be generated in case of a thicker gate oxide, in order not to generate undesired oxide ablation at other positions. In this way, LDD implantation can now be optimized for thin gate oxide thicknesses, as they are used for low-voltage transistors. For high-voltage transistors, which can have thicker gate-oxide thicknesses, however, the energy of LDD implantation is too small to penetrate through the thick gate oxide. This leads to a transistor with degraded electrical connection to the source, wherein the problem is aggravated with increasing thickness of the gate oxide.
The object of the present invention is to specify an arrangement improved in this respect with different transistors, together with a fabrication method for the source doping, that can be used independent of the gate oxide thickness and therefore for both low-voltage and also high-voltage transistors.
This object is solved according to the invention with an arrangement according to Claim 1. Advantageous constructions of the invention and also a method for the fabrication of the arrangement can be inferred from the other claims.
It is proposed to eliminate the LDD implant for the doping of source and drain regions of a first transistor and to replace it with doping that is already used at another point in the processing sequence and which is formed before the production of gate stack and especially before the production of the gate oxide.
By suitable selection of the structure of the first transistor, especially the type, extent, and relative arrangement of the doped regions, a transistor can be obtained that allows a suitable connection to the source. In this way, a simplified fabrication method is also produced, which can eliminate the step of an additional LDD implantation for transistors with a thicker gate oxide.
For the transistor, there is also the advantage that the length of the transistor channel is now no longer dependent on the orientation of two different masks relative to each other or one mask relative to the gate, but is determined only by the structure of one mask. In this way, a transistor of constant, easily adjustable channel length is produced, which is now independent of a change in the other processing or structuring parameters. In this way, the parameters that are dependent on the channel length of the transistor are also realized with higher accuracy and less deviation from the desired values. With the proposed transistor, certain structural tolerances can be successfully eliminated in this way, and a narrower transistor design and thus a transistor of smaller surface area is possible.
A transistor that takes into account these viewpoints has:
a substrate,
body doping of the first conductivity type,
a source and a drain region, which each have high terminal doping of the second conductivity type,
a gate oxide,
a gate electrode arranged above the gate oxide and in the area of a channel zone,
wherein, in the source region, another shallow doping of the second conductivity type is generated, which is inserted in the transistor in at least one other position for generating a functional doping and which is generated before the application of the gate oxide and thus independently of the position of the gate oxide. This other shallow doping can also be formed in parallel in the drain region of the transistor. Here, the transistor can be of the high-voltage type. It is advantageous that this doping is also suitable for low-voltage transistors and therefore different transistor types can be produced in parallel with the same doping in the source and drain region, in the same doping step.
It is possible, for example, for generating the other shallow doping of the second conductivity type to use the same doping and the same doping step as used also for the body doping of the complementary transistor, wherein the two equal dopings can be generated in parallel in the same step.
In principle, the first transistor can be of the p-channel type or of the n-channel type and can represent, accordingly, a PMOS or NMOS transistor. In the following, suitable structures for a PMOS transistor are specified as a first transistor, which, however, can also be adapted easily for an NMOS transistor.
For example, in a PMOS transistor for further shallow doping in the source region, doping can be used that corresponds to the body doping of the second NMOS transistor complementary to the first transistor and which is constructed, for example, as a shallow p-type well. For this purpose, the implantation mask for the shallow p-type well is provided with an additional opening for the desired p-doping in the source and/or drain region.
Another possibility consists in masking the body doping of the first transistor in the area of the source region. Then, for generating the other shallow doping a low implantation dose is sufficient. This shallow doping can be implemented with a doping of the second conductivity type, which is used in at least one other position of the transistor for another structure or another purpose. Such shallow doping is used, for example, to set the threshold voltage of the transistor. This so-called VT Implant (Threshold Implant) involves a relatively shallow doping of, e.g., only 0.2 μm depth, which can generate in the present embodiment the desired counter doping (relative to the substrate or body doping) in the source region.
In another construction, the first transistor has body doping that is limited in terms of surface area to the region of the channel zone. Accordingly, in this case, the area of the source region is also masked from the body doping, so that the other shallow doping of the second conductivity type can be constructed with the above-mentioned shallow doping, for example, the above-mentioned doping for setting the threshold voltage. Here, it can be advantageous to mask the VT implant in the channel zone, in order to obtain a suitable threshold voltage.
In an NMOS transistor, the body doping can be realized as a shallow p-type well, which is arranged in a deep p-type well and boosts its n-doping. This shallow p-type well can then be masked in the area of the source region and optionally also in the area of the channel zone. In this case, a body and thus also a channel zone that are each doped only weakly are obtained.
Below, the invention and the steps of the process for the fabrication of the transistor that are decisive (because they have been changed) will be explained in more detail with reference to embodiments and the associated figures. The figures are purely schematic and not true to scale, so that neither absolute nor relative dimensional information can be inferred from the figures.
The LDD implantation, shown in the figure by arrows, is masked by the gate oxide GO, which is significantly thicker in comparison with the low-voltage transistor, remains bonded at least partially in this region and does not lead to a sufficient doping LDD of the source region, shown very shallow in the figure, and thus leads to an insufficient channel connection. To solve this problem, it would be possible to increase the implantation energy for the LDD implant, but for this purpose a separate mask and an additional implantation step would be required. Another possibility consists of thinning the gate oxide before the LDD implant in the source region, but for this a separate mask and an additional processing step would also be required.
The substrate or body contact BK is arranged in the second window F2. Underneath the second window F2, an n+-doping is formed, for example, by the mask window Mn indicated here.
The body contact BK, under which an n+-doping is provided, is also arranged within the shallow n-type well SN. Underneath the source contact SK there is p+-doping as terminal doping, which boosts the LDD implant LDD at a distance to the gate electrode GP. Underneath the gate oxide GO, a shallow p-doping VT is formed, which is used for setting the transistor threshold voltage (Threshold Implant) and is generated before the application of the gate oxide GO. The channel width L is measured from the left end of the shallow n-type well SN in the figure up to the right end of the gate electrode GP, wherein the channel width L is defined by the arrangement of the shallow n-region SN relative to the gate electrode GP. The shallow p-doping VT is not occupied with holes at 0 V gate voltage for a gate electrode doped with donors. For this reason, the transistor is then switched off.
It is clearly visible from the figure that the width L of the channel zone in this embodiment is no longer dependent on the relative arrangement of the gate electrode GP and the doped regions underneath. Instead, the width L of the channel zone is determined by the distance of the shallow p-type well generated with the mask MSP and the adjacent edge of the window opening F1 at the bottom in
In addition, this transistor and the method used for its fabrication have the advantage that the other shallow doping in the source region can be generated independently of the thickness of the gate oxide, so that this step can be used for the parallel production of these regions for different transistors with gate oxides of different thicknesses and especially on the same wafer.
Therefore, it is also possible with this second embodiment to eliminate the LDD implant especially for the source of the transistor. Reliable setting of the channel width L is simultaneously enabled, which now is dependent only on the width of the shallow n-type well region SN generated with the mask MSN. This structure can also be generated completely independently of the thickness of the gate oxide, because it is formed, with the exception of the source terminal dopings p+, completely before the application of the gate oxide and the gate electrode.
As another effect of the third embodiment shown in
With the invention it is possible, for the fabrication of source and drain dopings, to form a process sequence that can be used both for low-voltage and for high-voltage transistors. The process sequence is designed in such a way that source and drain dopings of both low-voltage transistors and high-voltage transistors of one type can be generated in parallel in the same processing step. This simplifies the processing sequence in all cases in which high-voltage and low-voltage transistors are realized one next to the other on one component. The transistors produced are also distinguished by an easily adjustable channel width L, which is significantly less sensitive to processing deviations and therefore leads to transistors with easily reproducible characteristics. The invention is especially suitable for the fabrication of source regions of high-voltage transistors of the PMOS type and can be used in corresponding modifications and for inversion of the conductivity types of various wells and doped regions for NMOS transistors as well.
The application was explained only with reference to a few concrete embodiments, but is not limited to these. Within the scope of the invention, it is possible to deviate from the actual transistor structures shown in the figures and described in the text and to use and implement correspondingly adapted and varying mask regions. However, it is always essential that, in addition to the high source terminal doping created after the production of the gate stack, another shallow doping, which is formed before the production of the gate stack with a surface area larger relative to the source terminal doping, is used for the production of the source region. For these other shallow dopings, other dopings of the desired conductivity type in the process flow can also be used. These dopings can be a component of structures that are the opposite of the complementary transistor. It is especially advantageous, however, as described in
S Source
D Drain
G Gate
GO Gate oxide
SUB Substrate
FOX Field oxide
DZ Drift zone
LDD LDD implant
BK Body contact
SK Source contact
F1, F2 First and second window in FOX
L Channel width
Mn Mask for n-doping
MSP Mask for shallow p-type well
MP Mask for shallow p-doping
GP Gate polysilicon=G
VT Threshold implant
SN Shallow n-type well
DP Deep p-type well
DN Deep n-type well
p+ Source terminal doping
n+ Body contact doping
Filing Document | Filing Date | Country | Kind | 371c Date |
---|---|---|---|---|
PCT/EP2006/009685 | 10/6/2006 | WO | 00 | 1/12/2009 |