Patent Application
20230105007
The present invention relates generally to the electrical, electronic and computer arts and, more particularly, to phase change memory (PCM) cells useful, for example, in artificial intelligence (AI) applications, and the like. PCM is a type of non-volatile random-access memory, making use of properties of chalcogenide glass. Heat produced by the passage of an electric current through a heating element, generally made of titanium nitride, can quickly heat and quench the glass, making it amorphous, or hold it in its crystallization temperature range for some time, thereby switching it to a crystalline state.
Chalcogenide materials are an emerging class of commercial electronic materials that exhibit switching, memory, logic, and processing functionality. The basic principles of chalcogenide materials were developed in the 1960s and much effort since then has led to advancements of the underlying science and an expansion of the field of application of chalcogenide materials.
One type of PCM chalcogenide memory device utilizes the wide range of resistance values available for the active chalcogenide material as the basis of memory operations (i.e., to encode information). Each resistance value corresponds to a distinct structural state of the chalcogenide material, and one or more of the states can be selected and used to define operational memory states. Chalcogenide materials, as noted, exhibit a crystalline state or phase as well as an amorphous state or phase. Different structural states of a chalcogenide material differ with respect to the relative proportions of crystalline and amorphous phase in a given volume or region of chalcogenide material. The range of resistance values is bounded by a SET state and a RESET state of the chalcogenide material. The SET state is a low resistance structural state whose electrical properties are primarily controlled by the crystalline portion of the chalcogenide material and the RESET state is a high resistance structural state whose electrical properties are primarily controlled by the amorphous portion of the chalcogenide material.
Utilizing phase change memory for analog computing typically requires memory cells with a resistance that changes linearly with programming pulses and is predictable and repeatable. Amorphous phase change materials often suffer from “resistance drift,” whereby the resistance of the cell changes over time, which makes the resistance of the cell unpredictable. To mitigate resistance drift, a “projection segment” (a parallel resistor that bypasses current around the amorphous volume), is added to the cell. Depending on the geometry of the cell and the projection segment, however, the cell resistance can become very non-linear. For an exemplary “mushroom” cell design using a projection segment that covers the bottom of the phase change material (Ge2Sb2Te5 (GST)), the simulated resistance of the cell is highly non-linear with the side length of the amorphous volume.
Phase change material (PCM) devices with resistive liners (e.g. projection segments) provide better cycling endurance and reduce resistance drift of the device due to bypass of current through the amorphous phase-change volume during READ operations. Seung-Wook Ryu, Young-Bae Ahn, Jong-Ho Lee, and Hyeong-Joon Kim, Thermal Stability of SiO2 Doped Ge2Sb2Te5 for Application in Phase Change Random Access Memory, JSTS: Journal of Semiconductor Technology and Science. 2011; 11(3):146-52, discloses that the addition of a small amount of SiO2 into GST film restricts the deterioration of physical and chemical properties of GST film, resulting in better thermal stability after isothermal annealing. Multi GST/dGST/GST (i.e., undoped GST/doped GST/undoped GST) structures provide better thermal stability, without process issues such as liner or heater oxidation, during dGST deposition. Wabe W. Koelmans, Abu Sebastian, Vara Prasad Jonnalagadda, Daniel Krebs, Laurent Dellmann, and Evangelos Eleftheriou, Projected phase-change memory devices, Nature communications, 2015 Sep. 3; 6(1):1-7 discloses techniques to decouple the physical mechanism of resistance storage from the information-retrieval process.
Referring to
Principles of the invention provide techniques for artificial intelligence (AI) devices with improved thermal stability and scaling behavior. In one aspect, an exemplary phase change memory semiconductor structure includes a substrate; a landing pad located in the substrate; a dielectric located outwardly of the substrate; a heater element located in the substrate outward of the landing pad; a stack including an inner undoped chalcogenide layer outward of the dielectric, a doped chalcogenide layer outward of the inner undoped chalcogenide layer, and an outer undoped chalcogenide layer outward of the doped chalcogenide layer; and at least one lateral conductive metal layer associated with the stack.
In another aspect, an exemplary phase change memory semiconductor array includes a plurality of word lines; a plurality of bit lines intersecting the plurality of word lines at a plurality of cell locations; a plurality of access devices, controlled by the word lines, at the plurality of cell locations; and a plurality of phase change memory cells located at the plurality of cell locations. Each of the phase change memory cells includes a substrate portion; a landing pad located in the substrate portion; a dielectric portion located outwardly of the substrate portion; a heater element located in the substrate portion outward of the landing pad; a stack including an inner undoped chalcogenide layer outward of the dielectric, a doped chalcogenide layer outward of the inner undoped chalcogenide layer, and an outer undoped chalcogenide layer outward of the doped chalcogenide layer; at least one lateral conductive metal layer associated with the stack; and a top electrode outward of the outer undoped chalcogenide layer. One of the top electrode and the landing pad is coupled to a corresponding one of the bit lines and another of the top electrode and the landing pad is coupled to a corresponding one of the access devices.
In a further aspect, an exemplary method of forming a phase change memory semiconductor structure includes depositing a dielectric outwardly of a substrate having a landing pad located therein; patterning the dielectric with a heater formation cavity; forming a heater element in the heater formation cavity; forming a stack outward of the dielectric, the stack including an inner undoped chalcogenide layer outward of the dielectric, a doped chalcogenide layer outward of the inner undoped chalcogenide layer, and an outer undoped chalcogenide layer outward of the doped chalcogenide layer; and forming at least one lateral conductive metal layer associated with the stack.
As used herein, “facilitating” an action includes performing the action, making the action easier, helping to carry the action out, or causing the action to be performed. Thus, by way of example and not limitation, instructions executing on one processor might facilitate an action carried out by semiconductor fabrication equipment, by sending appropriate data or commands to cause or aid the action to be performed. Where an actor facilitates an action by other than performing the action, the action is nevertheless performed by some entity or combination of entities.
Techniques as disclosed herein can provide substantial beneficial technical effects. Some embodiments may not have these potential advantages and these potential advantages are not necessarily required of all embodiments. By way of example only and without limitation, one or more embodiments may provide one or more of:
PCM cells with improved thermal stability;
PCM cells with improved scaling behavior;
one or more exemplary structures improve one or more of retention, memory window, endurance characterization and PCM resistance drift coefficient.
These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The following drawings are presented by way of example only and without limitation, wherein like reference numerals (when used) indicate corresponding elements throughout the several views, and wherein:
It is to be appreciated that elements in the figures are illustrated for simplicity and clarity. Common but well-understood elements that may be useful or necessary in a commercially feasible embodiment may not be shown in order to facilitate a less hindered view of the illustrated embodiments.
Principles of inventions described herein will be in the context of illustrative embodiments. Moreover, it will become apparent to those skilled in the art given the teachings herein that numerous modifications can be made to the embodiments shown that are within the scope of the claims. That is, no limitations with respect to the embodiments shown and described herein are intended or should be inferred.
One or more embodiments provide techniques for forming and oxygen-free interface dGST cell, for using a dGST with bottom and top GST to avoid oxidation on the heater or bottom liner and top electrode, and/or for providing an optional bottom liner to improve resistance drift without any oxidation process. Furthermore, one or more embodiments provide a structure of a mushroom cell structure to improve endurance and resistance drift and programing current, a WET damage-free GST cell, and/or a pseudo-terminal metal liner inside a GST mushroom cell. One or more embodiments employ a metal with low thermal conductivity and high electrical conductivity (lower than other metals but higher than dielectric). Furthermore, one or more embodiments provide techniques for incorporating pseudo-terminal metal inside of a GST cell, a laminated GST cell with dGST and GST, techniques for forming oxidation-free interface GST, and/or a phase change memory structure with a GST/dGST/GST laminated cell. With regard to the WET damage-free GST cell, the interface between dGST and the bottom heater can be damaged during GST etching (reactive ion etching (ME) followed by WET (dilute hydrofluoric acid (DHF)-based Wet process)). Advantageously, by placing dGST on top of a thin layer of GST, the interface is much stronger than a direct dGST interface, during RIE and WET processes.
In prior art devices, current flows from the bottom electrode 101 to the GST. Prior art devices employ undoped GST. One or more embodiments employ dGST (doped GST; e.g., GST doped with silicon oxide) between very thin layers of GST. Undoped GST is close to crystalline and easily passes current. However, when doped with SiO2, the resistivity (and thus resistance) is much higher and the current is much lower (although the resistivity of dGST moves closer to that of undoped GST as temperature increases). PCM works by passing current in the crystalline state and blocking current in the amorphous state. The use of dGST typically requires a post-sputtering oxygen flow plasma vapor deposition (PVD) step. Typical sputtering includes Germanium, Antimony, and Tellurium with oxygen flow and silicon post-sputtering. During this process, it is undesirable if the metal heater 105 oxidizes. Furthermore, a metal oxide is often undesirably formed between the metal and the dGST.
Consider now an exemplary integration scheme for forming PCM cells with improved thermal stability and scaling behavior.
In the left-most view in the middle row, metal 227 is included. In the middle view in the middle row, metal 227 is included and a metal layer 249 is also formed between layers 231, 233. In the right-most view in the middle row metal 227 is included and a metal layer 249 is also formed between layers 231, 233. Further, the sidewalls, as shown at 251, include side ATE lines such as TiN, TaN (high-resistance), and a-C or Si, Ge, or any semiconductor also on the sidewall, to provide current path and thermal confinement.
In the left-most view in the bottom row, metal 227 is included. In the middle view in the bottom row, metal 227 is included and a metal layer 249 is also formed between layers 231, 233. In the right-most view in the bottom row metal 227 is included and a metal layer 249 is also formed between layers 231, 233. Further, the sidewalls, as shown at 251, include side ATE lines such as TiN, TaN (high-resistance), and a-C or Si, Ge, or any semiconductor also on the sidewall, to provide current path and thermal confinement. In each of the views in the bottom row, the bottom also includes TiN, TaN (high-resistance), and a-C at 253. In particular, the embodiments of the last row include a long (same length as GST/TiN/SiN) projection liner while the embodiments of the top row have a patterned liner.
Furthermore in this regard,
By way of review,
Semiconductor device manufacturing includes various steps of device patterning processes. For example, the manufacturing of a semiconductor chip may start with, for example, a plurality of CAD (computer aided design) generated device patterns, which is then followed by effort to replicate these device patterns in a substrate. The replication process may involve the use of various exposing techniques and a variety of subtractive (etching) and/or additive (deposition) material processing procedures. For example, in a photolithographic process, a layer of photo-resist material may first be applied on top of a substrate, and then be exposed selectively according to a pre-determined device pattern or patterns. Portions of the photo-resist that are exposed to light or other ionizing radiation (e.g., ultraviolet, electron beams, X-rays, etc.) may experience some changes in their solubility to certain solutions. The photo-resist may then be developed in a developer solution, thereby removing the non-irradiated (in a negative resist) or irradiated (in a positive resist) portions of the resist layer, to create a photo-resist pattern or photo-mask. The photo-resist pattern or photo-mask may subsequently be copied or transferred to the substrate underneath the photo-resist pattern.
There are numerous techniques used by those skilled in the art to remove material at various stages of creating a semiconductor structure. As used herein, these processes are referred to generically as “etching”. For example, etching includes techniques of wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE), which are all known techniques to remove select material(s) when forming a semiconductor structure. The Standard Clean 1 (SC1) contains a strong base, typically ammonium hydroxide, and hydrogen peroxide. The SC2 contains a strong acid such as hydrochloric acid and hydrogen peroxide. The techniques and application of etching is well understood by those skilled in the art and, as such, a more detailed description of such processes is not presented herein.
Although the overall fabrication method and the structures formed thereby are novel, certain individual processing steps required to implement the method may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tooling. These techniques and tooling will already be familiar to one having ordinary skill in the relevant arts given the teachings herein. Moreover, one or more of the processing steps and tooling used to fabricate semiconductor devices are also described in a number of readily available publications, including, for example: James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition, Prentice Hall, 2001 and P. H. Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008, which are both hereby incorporated by reference herein. It is emphasized that while some individual processing steps are set forth herein, those steps are merely illustrative, and one skilled in the art may be familiar with several equally suitable alternatives that would be applicable.
It is to be appreciated that the various layers and/or regions shown in the accompanying figures may not be drawn to scale. Furthermore, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure for ease of explanation. This does not imply that the semiconductor layer(s) not explicitly shown are omitted in the actual integrated circuit device.
Given the discussion thus far, it will be appreciated that, in general terms, an exemplary phase change memory semiconductor structure includes a substrate (e.g., low k dielectric, TEOS 201 and NBLoK, SiN, SiCN 207). Also included is a landing pad 203 located in the substrate. As used herein, the “landing pad” refers to the bottom metal under the heater which connects to the bottom Cu wiring. A dielectric 205 is located outwardly of the substrate, and a heater element 211, 213, 215 is located in the substrate outward of the landing pad. A stack includes an inner undoped chalcogenide layer 225 outward of the dielectric, a doped chalcogenide layer 229 or 237, 241, 245 outward of the inner undoped chalcogenide layer, and an outer undoped chalcogenide layer 231 or 247 outward of the doped chalcogenide layer. In a non-limiting example, the chalcogenide includes GST. Also included is at least one lateral conductive metal layer 227 or 249 associated with the stack.
In one or more embodiments, the at least one lateral conductive metal layer 249 is located outward of the outer undoped chalcogenide layer 231, and a projection liner 217 is located in the inner undoped chalcogenide layer 225 outward of the heater element. Some such embodiments further include a second lateral conductive metal layer 227 located between the inner undoped chalcogenide layer and the doped chalcogenide layer. Some such embodiments further include a sidewall layer 251 (e.g., side ATE lines such as TiN, TaN (high-resistance), and a-C or Si, Ge, or any semiconductor also on the sidewall, to provide current path and thermal confinement) on a sidewall of the structure.
In one or more embodiments, the at least one lateral conductive metal layer 227 is located between the inner undoped chalcogenide layer 225 and the doped chalcogenide layer 229. Some such embodiments further include a second lateral conductive metal layer 249 located outward of the outer undoped chalcogenide layer 231. Some such embodiments further include a sidewall layer 251 (e.g., side ATE lines such as TiN, TaN (high-resistance), and a-C or Si, Ge, or any semiconductor also on the sidewall, to provide current path and thermal confinement) on a sidewall of the structure.
In one or more embodiments, the at least one lateral conductive metal layer 227 is located between the inner undoped chalcogenide layer 225 and the doped chalcogenide layer 229, and an all-around projection liner 253 is located between the inner undoped chalcogenide layer and the heater element. Some such embodiments further include a second lateral conductive metal layer 249 located outward of the outer undoped chalcogenide layer 231. Some such embodiments further include a sidewall layer 251 (e.g., side ATE lines such as TiN, TaN (high-resistance), and a-C or Si, Ge, or any semiconductor also on the sidewall, to provide current path and thermal confinement) on a sidewall of the structure.
In general, references to the outer undoped chalcogenide layer 231 are equally applicable to layer 247. Furthermore, references to the at least one lateral conductive metal layer 227 being located between the inner undoped chalcogenide layer 225 and the doped chalcogenide layer 229 are equally applicable to at least one lateral conductive metal layer 227 being located between inner undoped chalcogenide layer 225 and doped chalcogenide layer 237.
In another aspect, referring to
In one or more embodiments, the phase change memory semiconductor array further includes control circuitry 301 coupled to the word lines and the bit lines and configured to cause weights of a neural network to be stored in plurality of phase change memory cells. In one or more embodiments, the weights are thus stored in the cells.
In another aspect, a method of forming a phase change memory semiconductor structure includes (
One or more embodiments further include forming a projection liner 217, 253 outward of the heater element and inward of the stack.
In one or more embodiments, forming the at least one lateral conductive metal layer includes forming the at least one lateral conductive metal layer between the inner undoped chalcogenide layer and the doped chalcogenide layer (see layer 227). Some such embodiments further include forming a second lateral conductive metal layer 249 outward of the outer undoped chalcogenide layer. Some such embodiments further include forming a sidewall layer 251 on a sidewall of the structure (e.g., side ATE lines such as TiN, TaN (high-resistance), and a-C or Si, Ge, or any semiconductor also on the sidewall, to provide current path and thermal confinement).
In one or more embodiments, forming the at least one lateral conductive metal layer includes forming the at least one lateral conductive metal layer between the inner undoped chalcogenide layer and the doped chalcogenide layer (see layer 227).
Those skilled in the art will appreciate that the exemplary structures discussed above can be distributed in raw form (i.e., a single wafer having multiple unpackaged chips), as bare dies, in packaged form, or incorporated as parts of intermediate products or end products that benefit from having PCM cells therein.
An integrated circuit in accordance with aspects of the present inventions can be employed in essentially any application and/or electronic system where PCM cells would be beneficial. Given the teachings of the present disclosure provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments disclosed herein.
The illustrations of embodiments described herein are intended to provide a general understanding of the various embodiments, and they are not intended to serve as a complete description of all the elements and features of apparatus and systems that might make use of the circuits and techniques described herein. Many other embodiments will become apparent to those skilled in the art given the teachings herein; other embodiments are utilized and derived therefrom, such that structural and logical substitutions and changes can be made without departing from the scope of this disclosure. It should also be noted that, in some alternative implementations, some of the steps of the exemplary methods may occur out of the order noted in the figures. For example, two steps shown in succession may, in fact, be executed substantially concurrently, or certain steps may sometimes be executed in the reverse order, depending upon the functionality involved. The drawings are also merely representational and are not drawn to scale. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Embodiments are referred to herein, individually and/or collectively, by the term “embodiment” merely for convenience and without intending to limit the scope of this application to any single embodiment or inventive concept if more than one is, in fact, shown. Thus, although specific embodiments have been illustrated and described herein, it should be understood that an arrangement achieving the same purpose can be substituted for the specific embodiment(s) shown; that is, this disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will become apparent to those of skill in the art given the teachings herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. Terms such as “bottom”, “top”, “above”, “over”, “under” and “below” are used to indicate relative positioning of elements or structures to each other as opposed to relative elevation. If a layer of a structure is described herein as “over” another layer, it will be understood that there may or may not be intermediate elements or layers between the two specified layers. If a layer is described as “directly on” another layer, direct contact of the two layers is indicated. As the term is used herein and in the appended claims, “about” means within plus or minus ten percent.
The corresponding structures, materials, acts, and equivalents of any means or step-plus-function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the various embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit thereof. The embodiments were chosen and described in order to best explain principles and practical applications, and to enable others of ordinary skill in the art to understand the various embodiments with various modifications as are suited to the particular use contemplated.
The abstract is provided to comply with 37 C.F.R. § 1.76(b), which requires an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the appended claims reflect, the claimed subject matter may lie in less than all features of a single embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.
Given the teachings provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques and disclosed embodiments. Although illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that illustrative embodiments are not limited to those precise embodiments, and that various other changes and modifications are made therein by one skilled in the art without departing from the scope of the appended claims.
