Patent Application
20240258254
This nonprovisional application is based on Japanese Patent Application No. 2023-011194 filed on Jan. 27, 2023, with the Japan Patent Office, the entire contents of which are hereby incorporated by reference.
The present disclosure relates to a bonding pad, an integrated circuit element, and an integrated circuit device.
In recent years, in an integrated circuit element included in an integrated circuit, in order to achieve circuit integration and miniaturization, a multilayer structure in which a plurality of wiring layers and insulating layers for electrically insulating the plurality of the wiring layers are laminated has been adopted. Accordingly, the multilayer structure similar to the integrated circuit has been adopted also in a bonding pad of the integrated circuit element in order to simplify a manufacturing process and reduce man-hours.
Japanese Patent Laying-Open No. 2000-195866 discloses a bonding pad including an upper wiring, an intermediate wiring, a lower wiring, an integrated mesh-type tungsten plug electrically connecting the wirings, and a plurality of island-type insulators existing in the integrated mesh-type tungsten plug and surrounded by the integrated mesh-type tungsten plug.
Generally, the bonding pad is subjected to ultrasonic bonding to a conductive member such as a wire. In the bonding pad described in Japanese Patent Laying-Open No. 2000-195866, when the conductive member is subjected to the ultrasonic bonding to the upper wiring, a load due to weighting in a lamination direction of the upper wiring, the intermediate wiring, and the lower wiring is applied to the bonding pad. Moreover, a load due to ultrasonic vibration is applied to the bonding pad in a direction orthogonal to the lamination direction during the ultrasonic bonding.
In the bonding pad described in Japanese Patent Laying-Open No. 2000-195866, since a Young's modulus of tungsten constituting the integrated mesh-type tungsten plug is higher than a Young's modulus of an insulator material constituting the island-type insulator, a structure including the integrated mesh-type tungsten plug and the island-type insulator hardly buffers a stress. Therefore, the stress may concentrate on the integrated mesh-type tungsten plug and cracks may occur during the ultrasonic bonding with the load applied as described above. In a case where the cracks occur in the integrated mesh-type tungsten plug, bondability between the conductive member and the bonding pad may be deteriorated, and the conductive member may be peeled off from the bonding pad similarly to a case where the cracks occur in the island-type insulator formed in the plug.
A main object of the present disclosure is to provide a bonding pad in which cracks hardly occur in each of a plug and an insulator and bondability between a conductive member and the bonding pad is hardly deteriorated as compared with a conventional bonding pad, an integrated circuit element including the bonding pad, and an integrated circuit device including the integrated circuit element.
The bonding pad according to the present disclosure is a bonding pad of the integrated circuit element included in the integrated circuit device. The bonding pad includes a surface electrode layer having a first surface; a resistance layer having a second surface disposed at an interval from the first surface in a first direction orthogonal to the first surface and facing a side opposite to the first surface; a stress buffer layer disposed between the surface electrode layer and the resistance layer in the first direction; and a connecting member connecting the surface electrode layer and the stress buffer layer in the first direction and being in contact with each of the surface electrode layer and the stress buffer layer. The stress buffer layer extends over the entire bonding pad in a direction orthogonal to the first direction. The connecting member includes an insulator that is in contact with the each of the surface electrode layer and the stress buffer layer in the first direction; and at least one plug that is in contact with the insulator in the direction orthogonal to the first direction and electrically connects the surface electrode layer and the stress buffer layer. A thickness of the stress buffer layer in the first direction is larger than a thickness of the surface electrode layer in the first direction.
The above and other objects, features, aspects and advantages of the present invention will become apparent from detailed description of the present invention below to be understood referring to accompanying drawings.
Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that, hereinafter, the same or equivalent units are denoted by the same reference numerals, and redundant description will not be repeated.
As illustrated in
As illustrated in
The each of bonding pads 11 of integrated circuit element 101 is one of bonding pads according to the first embodiment to the fourth embodiment to be described later.
Integrated circuit element 101 further includes a multilayer structure 20. Multilayer structure 20 includes a first wiring layer and a second wiring layer that are laminated at an interval therebetween and electrically connected to bonding pads 11; an insulating layer that is sandwiched between the first wiring layer and the second wiring layer and electrically insulates the first wiring layer and the second wiring layer; and a plug that is embedded in the insulating layer and electrically connects the first wiring layer and the second wiring layer.
Bonding pad 11 according to the first embodiment will be described with reference to
As illustrated in
Bonding pad 11 includes a surface electrode layer 1, a resistance layer 2, a stress buffer layer 3, and a connecting member 4. In bonding pad 11, resistance layer 2, stress buffer layer 3, connecting member 4, and surface electrode layer 1 are laminated in order upward in first direction Z.
Surface electrode layer 1 has first surface 10A. A material constituting surface electrode layer 1 may be any material having conductivity, but includes, for example, aluminum (Al). The material constituting surface electrode layer 1 may be a compound of Al.
As illustrated in
Resistance layer 2 has second surface 10B. A material constituting resistance layer 2 may be any material having a specific resistance higher than a specific resistance of the material constituting surface electrode layer 1, but includes, for example, polysilicon.
Resistance layer 2 extends over the entire bonding pad 11 in, for example, a second direction X and a third direction Y orthogonal to first direction Z, respectively. As viewed from first direction Z, resistance layer 2 is disposed to overlap with the each of first region R1 and second region R2 of first surface 10A. As viewed from first direction Z, resistance layer 2 is disposed to overlap with the entire first surface 10A, for example. Resistance layer 2 is a continuous body continuing in second direction X and third direction Y, respectively.
Stress buffer layer 3 is disposed between surface electrode layer 1 and resistance layer 2 in first direction Z. A lower surface of stress buffer layer 3 is in contact with an upper surface of resistance layer 2. A material constituting stress buffer layer 3 has the conductivity. Stress buffer layer 3 is electrically connected to resistance layer 2.
Stress buffer layer 3 extends over the entire bonding pad 11 in second direction X and third direction Y, respectively. As viewed from first direction Z, stress buffer layer 3 is disposed to overlap with the each of first region R1 and second region R2 of first surface 10A. As viewed from first direction Z, stress buffer layer 3 is disposed to overlap with the entire first surface 10A, for example. Stress buffer layer 3 is a continuous body continuing in second direction X and third direction Y, respectively. Stress buffer layer 3 is, for example, a single layer including one continuous body continuing in first direction Z, second direction X, and third direction Y, respectively.
A rigidity modulus (a shearing modulus) of the material constituting stress buffer layer 3 is lower than a rigidity modulus (a shearing modulus) of a material constituting a plug 42 to be described later. A Young's modulus of the material constituting stress buffer layer 3 is lower than a Young's modulus of the material constituting plug 42 to be described later. The material constituting stress buffer layer 3 may be the same as the material constituting surface electrode layer 1.
As illustrated in
Connecting member 4 is disposed between surface electrode layer 1 and stress buffer layer 3 in first direction Z, and connects surface electrode layer 1 and stress buffer layer 3. Connecting member 4 is in contact with each of surface electrode layer 1 and stress buffer layer 3.
Connecting member 4 includes an insulator 41 and a plurality of plugs 42. Insulator 41 and each of the plurality of plugs 42 are in contact with surface electrode layer 1 and stress buffer layer 3 in first direction Z, respectively. The each of the plurality of plugs 42 electrically connects surface electrode layer 1 and stress buffer layer 3.
The each of the plurality of plugs 42 are disposed at an interval in second direction X and third direction Y, respectively. The each of the plurality of plugs 42 is embedded in insulator 41. Insulator 41 is formed with a plurality of through holes penetrating insulator 41 in first direction Z. The each of the plurality of plugs 42 is formed to fill the plurality of the through holes of insulator 41.
Upper surfaces of insulator 41 and the each of the plurality of plugs 42 are in contact with a lower surface of surface electrode layer 1. Lower surfaces of insulator 41 and the each of the plurality of plugs 42 are in contact with an upper surface of stress buffer layer 3. An inner peripheral surface of each of the plurality of the through holes of insulator 41 is in contact with a side surface of the each of the plurality of plugs 42. From a different point of view, in connecting member 4, insulator 41 and the each of the plurality of plugs 42 are alternately laminated in a direction orthogonal to first direction Z. Connecting member 4 is a multilayer plug including insulator 41 and the plurality of plugs 42 alternately laminated in the direction orthogonal to first direction Z.
A material constituting insulator 41 may be any material having an electrical insulation, but is, for example, an oxide film. A material constituting the each of the plurality of plugs 42 is a material having the conductivity. The material constituting the each of the plurality of plugs 42 includes, for example, tungsten (W).
As illustrated in
As illustrated in
As illustrated in
Although not illustrated, multilayer structure 20 of integrated circuit element 101 is further included. Multilayer structure 20 includes the first wiring layer electrically connected to surface electrode layer 1 of bonding pad 11; the second wiring layer that is laminated at an interval from the first wiring layer in first direction Z and electrically connected to resistance layer 2 of bonding pad 11; the insulating layer that is sandwiched between the first wiring layer and the second wiring layer and electrically insulates the first wiring layer and the second wiring layer; and the plug that is embedded in the insulating layer and electrically connects the first wiring layer and the second wiring layer.
In a method for manufacturing integrated circuit element 101 to be described later, resistance layer 2 and stress buffer layer 3 of bonding pad 11 can be formed in the same process for the second wiring layer and the insulating layer of multilayer structure 20. Connecting member 4 of bonding pad 11 can be formed in the same process for the insulating layer and the plug of multilayer structure 20. Surface electrode layer 1 of bonding pad 11 can be formed in the same process for the first wiring layer of multilayer structure 20.
As described above, in the method for manufacturing integrated circuit element 101, bonding pad 11 can be formed simultaneously with multilayer structure 20. Hereinafter, an example of the method for manufacturing bonding pad 11 will be described.
First, resistance layer 2 and stress buffer layer 3 are formed in order on interlayer insulating film 106. Stress buffer layer 3 is formed on resistance layer 2. Each of resistance layer 2 and stress buffer layer 3 is formed over an entire region where bonding pad 11 is to be formed. In multilayer structure 20, the each of resistance layer 2 and stress buffer layer 3 may have any shape as a lower wiring layer.
Second, connecting member 4 is formed on stress buffer layer 3. In the process for forming connecting member 4, insulator 41 may be formed to embed the plurality of plugs 42 after the plurality of plugs 42 are formed at first. Alternatively, in the process for forming connecting member 4, the plurality of plugs 42 may be formed to fill the plurality of the through holes, after insulator 41 is formed into a film at first and the plurality of the through holes are formed in insulator 41. Connecting member 4 is formed over the entire region where bonding pad 11 is to be formed. In multilayer structure 20, insulating layer and plug may have any shape.
Third, surface electrode layer 1 is formed on connecting member 4. The each of resistance layer 2 and stress buffer layer 3 is formed over the entire region where bonding pad 11 is to be formed. In multilayer structure 20, surface electrode layer 1 may have any shape as an upper wiring layer.
In this way, bonding pad 11 may be formed simultaneously with multilayer structure 20.
Bonding pad 11 includes stress buffer layer 3 that is disposed between surface electrode layer 1 and resistance layer 2 in first direction Z and in contact with resistance layer 2. Stress buffer layer 3 extends over the entire bonding pad 11 in second direction X and third direction Y, respectively. Such stress buffer layer 3 disperses a stress to be generated in bonding pad 11 when wire 104 is subjected to the ultrasonic bonding to first surface 10A, and suppresses concentration of the stress on connecting member 4. Therefore, in bonding pad 11 including stress buffer layer 3, the cracks hardly occur in connecting member 4, and bondability between wire 104 and bonding pad 11 is hardly deteriorated, as compared with the conventional bonding pad described above.
Moreover, in bonding pad 11, thickness T1 of stress buffer layer 3 in first direction Z is larger than thickness T2 of surface electrode layer 1 in first direction Z. Rigidity of bonding pad 11 including such stress buffer layer 3 can be easily increased as compared with rigidity of a bonding pad including a stress buffer layer having a thickness in first direction Z equal to or smaller than the thickness of surface electrode layer 1 in first direction Z. As a result, in bonding pad 11, since rigidity required to withstand the ultrasonic vibration in direction orthogonal to first direction Z can be easily achieved, the cracks hardly occur in connecting member 4, and the bondability between wire 104 and bonding pad 11 is hardly deteriorated.
As illustrated in
Each of first metal layer 31 and second metal layer 32 extends over the entire bonding pad 12 in second direction X and third direction Y. The each of first metal layer 31 and second metal layer 32 is a continuous body continuing in second direction X and third direction Y, respectively. The each of first metal layer 31 and second metal layer 32 is, for example, a single layer including one continuous body continuing in first direction Z, second direction X, and third direction Y, respectively.
Rigidity of a second metal material constituting second metal layer 32 is higher than rigidity of a first metal material constituting first metal layer 31. A Young's modulus of the first metal material constituting first metal layer 31 is lower than a Young's modulus of the second metal material constituting second metal layer 32. A rigidity modulus of the first metal material constituting first metal layer 31 is lower than a rigidity modulus of the second metal material constituting second metal layer 32. The Young's modulus of the first metal material constituting first metal layer 31 is lower than the Young's modulus of the material constituting the each of the plurality of plugs 42. The rigidity modulus of the first metal material constituting first metal layer 31 is lower than the rigidity modulus of the material constituting the each of the plurality of plugs 42.
The second metal material constituting second metal layer 32 is, for example, the same as the material constituting the each of the plurality of plugs 42. Note that, the Young's modulus of the second metal material constituting second metal layer 32 may be lower than the Young's modulus of the material constituting the each of the plurality of plugs 42.
A sum T1 of thicknesses of first metal layer 31 and second metal layer 32 in first direction Z is larger than thickness T2 of surface electrode layer 1 in first direction Z. Sum T1 of the thicknesses of first metal layer 31 and second metal layer 32 in first direction Z is larger than, for example, the thickness of resistance layer 2 in first direction Z. Sum T1 of the thicknesses of first metal layer 31 and second metal layer 32 in first direction Z is larger than, for example, the thickness of connecting member 4 in first direction Z.
The thickness of first metal layer 31 in first direction Z is, for example, larger than the thickness of surface electrode layer 1 in first direction Z. The thickness of second metal layer 32 in first direction Z is larger than, for example, the thickness of first metal layer 31 in first direction Z. The thickness of second metal layer 32 in first direction Z may be equal to or smaller than the thickness of first metal layer 31 in first direction Z.
In bonding pad 12, first metal layer 31 disperses a stress to be generated in bonding pad 12 when wire 104 is subjected to the ultrasonic bonding to first surface 10A, and suppresses the concentration of the stress on connecting member 4. Moreover, second metal layer 32 suppresses excessive deformation of connecting member 4 due to a weighting load in first direction Z to be applied to bonding pad 12 during the ultrasonic bonding above. Therefore, also in bonding pad 12, the cracks hardly occur in connecting member 4, and bondability between wire 104 and bonding pad 12 is hardly deteriorated, as compared with the conventional bonding pad described above.
In bonding pad 12, the second metal material constituting second metal layer 32 may be the same as the material constituting the each of the plurality of plugs 42. In this way, since types of the metal materials included in bonding pad 12 can be reduced, measures against metal contamination are facilitated and manufacturing efficiency is enhanced. Moreover, in this way, it is easy to control a deformation amount of bonding pad 12 due to the weighting load in first direction Z during the ultrasonic bonding above, and it is possible to more effectively suppress a deterioration in the bondability between wire 104 and bonding pad 12.
In bonding pad 12, the rigidity modulus of the second metal material constituting second metal layer 32 may be lower than the rigidity modulus of the material constituting the plurality of plugs 42. In this way, first metal layer 31 and second metal layer 32 can disperse a shear stress to be generated in bonding pad 12 when wire 104 is subjected to the ultrasonic bonding to first surface 10A, and can suppress the concentration of the stress on connecting member 4.
Multilayer structure 20 of integrated circuit element 101 according to second embodiment includes second metal layer 32 similarly to bonding pad 12. In a method for manufacturing integrated circuit element 101 according to the second embodiment, bonding pad 12 can be formed simultaneously with multilayer structure 20.
As illustrated in
Each of first metal layer 31 and insulating layer 33 extends over the entire bonding pad 13 in second direction X and third direction Y. The each of first metal layer 31 and insulating layer 33 is a continuous body continuing in second direction X and third direction Y, respectively. The each of first metal layer 31 and insulating layer 33 is, for example, a single layer including one continuous body continuing in first direction Z, second direction X, and third direction Y, respectively.
The rigidity modulus of the first metal material constituting first metal layer 31 is lower than the rigidity modulus of the material constituting the each of the plurality of plugs 42. The Young's modulus of the first metal material constituting first metal layer 31 is lower than the Young's modulus of the material constituting the each of the plurality of plugs 42.
A material constituting insulating layer 33 may be any material having the electrical insulation, but is, for example, the same as the material constituting insulator 41 of connecting member 4. Insulating layer 33 is, for example, the oxide film. A rigidity modulus of the material constituting insulating layer 33 is lower than the rigidity modulus of the material constituting the each of the plurality of plugs 42. A Young's modulus of the material constituting insulating layer 33 is lower than the Young's modulus of the material constituting the each of the plurality of plugs 42. Note that, the rigidity modulus of the material constituting insulating layer 33 may be lower than the rigidity modulus of the material constituting insulator 41.
A sum T1 of thicknesses of first metal layer 31 and insulating layer 33 in first direction Z is larger than thickness T2 of surface electrode layer 1 in first direction Z. Sum T1 of the thicknesses of first metal layer 31 and insulating layer 33 in first direction Z is larger than, for example, the thickness of resistance layer 2 in first direction Z. Sum T1 of the thicknesses of first metal layer 31 and insulating layer 33 in first direction Z is larger than, for example, the thickness of connecting member 4 in first direction Z.
The thickness of first metal layer 31 in first direction Z is, for example, larger than the thickness of surface electrode layer 1 in first direction Z. The thickness of insulating layer 33 in first direction Z is larger than, for example, the thickness of first metal layer 31 in first direction Z. The thickness of insulating layer 33 in first direction Z may be equal to or smaller than the thickness of first metal layer 31 in first direction Z.
In bonding pad 13, first metal layer 31 and insulating layer 33 disperse a stress to be generated in bonding pad 13 when wire 104 is subjected to the ultrasonic bonding to first surface 10A, and suppresses the concentration of the stress on connecting member 4. Moreover, since first metal layer 31 and insulating layer 33 easily follow the ultrasonic vibration in the direction orthogonal to first direction Z, it is possible to suppress generation of the cracks in connecting member 4 even in a case where energy of the ultrasonic vibration is set high. As a result, in bonding pad 13, the cracks hardly occur in connecting member 4, and bondability between wire 104 and bonding pad 13 is high, as compared with the conventional bonding pad described above.
Multilayer structure 20 of integrated circuit element 101 according to the third embodiment includes insulating layer 33 similarly to bonding pad 13. In a method for manufacturing integrated circuit element 101 according to the third embodiment, bonding pad 13 can be formed simultaneously with multilayer structure 20.
As illustrated in
Insulator 41 includes a first portion 41A disposed inside plug 42 and a second portion 41B disposed outside plug 42. First portion 41A of insulator 41 is a continuous body continuing in second direction X and third direction Y, respectively. First portion 41A of insulator 41 is, for example, a single layer including one continuous body continuing in first direction Z, second direction X, and third direction Y, respectively.
First portion 41A of insulator 41 includes a third portion 41A1 disposed in third region R3 and a fourth portion 41A2 disposed in fourth region R4. Third portion 41A1 and fourth portion 41A2 are configured as a continuous body. Second portion 41B of insulator 41 is disposed in fourth region R4.
As illustrated in
In bonding pad 14, since the bonding interface between first portion 41A of insulator 41 and plug 42 as well as the bonding interface between second portion 41B of insulator 41 and plug 42 are not formed in third region R3, the cracks hardly develop from the bonding interfaces above to insulator 41 as compared with bonding pad 11 in which the bonding interfaces above are also formed in third region R3. Therefore, bondability between wire 104 and bonding pad 14 is higher than the bondability between wire 104 and bonding pad 11.
In a method for manufacturing integrated circuit element 101 according to the fourth embodiment, bonding pad 14 can be formed simultaneously with multilayer structure 20.
As illustrated in
Bonding pads 11 to 14 according to first embodiment to fourth embodiment may include, instead of resistance layer 2, a bottom surface electrode layer made of a material having a specific resistance equivalent to the specific resistance of the material constituting surface electrode layer 1.
Hereinafter, various aspects of the present disclosure will be collectively described as supplementary notes.
A bonding pad of an integrated circuit element included in an integrated circuit device, the bonding pad including:
The bonding pad according to Supplementary Note 1, in which the stress buffer layer includes a first metal layer and a second metal layer laminated on each other in the first direction,
The bonding pad according to Supplementary Note 2, in which the second metal material constituting the second metal layer is a same as the material constituting the at least one plug.
The bonding pad according to Supplementary Note 2, in which a rigidity modulus of the second metal material constituting the second metal layer is lower than a rigidity modulus of the material constituting the at least one plug.
The bonding pad according to Supplementary Note 1, in which the stress buffer layer includes a metal layer and an insulating layer laminated on each other in the first direction,
The bonding pad according to any one of Supplementary Notes 1 to 5, in which the at least one plug includes a plurality of plugs disposed at intervals between each other in the direction orthogonal to the first direction, and
The bonding pad according to any one of Supplementary Notes 1 to 6, in which the first surface includes a first region to which a conductive member constituting a part of the integrated circuit device is bonded, and a second region located outside the first region,
The bonding pad according to any one of Supplementary Notes 1 to 7, in which the thickness of the stress buffer layer in the first direction is greater than or equal to a total value of the thickness of the surface electrode layer in the first direction and a thickness of the connecting member in the first direction.
An integrated circuit element including:
An integrated circuit device including:
Although the embodiments of the present invention have been described, it may be considered that the embodiments disclosed herein are illustrative in all respects and not restrictive. The scope of the present invention is indicated by claims, and it is intended that meanings equivalent to the claims and all modifications within the scope are included.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-011194 | Jan 2023 | JP | national |
