Field
The disclosure relates to methods for applying an electrically conductive material to a through-via.
Technical Background
An interposer can be used to route electrical signals between silicon microchips and organic substrates, to fan out electrical connections between dense-pitch chips and wider-pitch layers underneath, or to connect multiple silicon chips in two or three dimensional packaging architectures. Interposers have a need for electrical conduction through the thickness of the interposer. This can be accomplished using an electrically conductive through-via. The through-via can be filled with an electrically conductive layer using electrolytic plating. However this process requires plating all surfaces of the interposer substrate, both the walls of the through-vias and the planar surfaces of the substrate perpendicular to the through-via walls, as a first step. As a second step, the plating process is continued until the through-vias are filled. It is then necessary to remove the “overburden” layer from the planar surfaces of the substrate. This can be a time consuming and expensive process. Thus, there is a need for a method of applying an electrically conductive material to a through-via that does not result in an overburden layer.
In some embodiments, disclosed herein, a method for producing a conductive through-via can include obtaining a first substrate having a surface; obtaining a second substrate having a first surface, a second surface, and a through-via extending from the first surface to the second surface; applying a seed layer on a surface of a first substrate; forming a surface modification layer on the seed layer or the second substrate; bonding the second substrate to the first substrate with the surface modification layer to create an assembly, wherein the seed layer and the surface modification layer are disposed between the first and second substrates; applying conductive material to the through-via; and removing the second substrate from the assembly after applying the conductive material to the through-via.
In some embodiments, the method can also include applying an adhesive layer on the surface of the first substrate before applying the seed layer such that the adhesive layer is disposed between the first substrate and the seed layer. The adhesive layer can be one of Cr, Ti, Mo, Ni, NiCr, Hf, Zr, Nd, Ta, V and W. The seed layer can be a conductive material selected from the group consisting of copper, silver, tungsten, titanium nitride, titanium tungsten, tantalum nitride, and copper alloys. The seed layer can be applied directly to the surface of the first substrate. The surface modification layer can provide a temporary bond between the seed layer and the second substrate. The method can also include removing a portion of the surface modification layer extending across an opening of the through-via to expose the seed layer, for example by exposing the surface modification layer to an oxygen plasma. The first and second substrates can be glass. The conductive material can be applied to the through-via by electrolytical plating. The through-via can be filled with a conductive material, for example, a metal. The second substrate can be mechanically removed from the assembly. The removing of the second substrate from the assembly does not result in the first or second substrates breaking into two or more pieces.
In some embodiments, a seed layer can be applied to the second substrate. An adhesive layer can be applied to the second substrate prior to applying the seed layer to the second substrate. The seed layer and/or adhesive layer can be applied to the second substrate prior to or after bonding the first and second substrates.
In some embodiments, the surface modification layer formed on the seed layer or the second substrate is a first surface modification layer and a second modification layer is formed on the surface of the first substrate prior to applying the seed layer. In such embodiments, the method can also include removing the first substrate from the seed layer.
It is to be understood that both the foregoing general description and the following detailed description are merely exemplary, and are intended to provide an overview or framework to understanding the nature and character of the claims. Additional features and advantages will be set forth in the detailed description which follows, and in part will be readily apparent to those skilled in the art from that description or recognized by practicing the embodiments as described herein, including the detailed description which follows, the claims, as well as the appended drawings.
The accompanying drawings are included to provide a further understanding, and are incorporated in and constitute a part of this specification. The drawings illustrate one or more embodiment(s), and together with the description serve to explain principles and operation of the various embodiments. These drawings are not to scale.
Reference will now be made in detail to the present preferred embodiment(s), an example of which is/are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.
Definitions
“Optional” or “optionally” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event or circumstance occurs and instances where it does not.
The indefinite article “a” or “an” and its corresponding definite article “the” as used herein means at least one, or one or more, unless specified otherwise.
“Temporary bond” refers to a non-destructive and reversible adhesion between two objects, which bond is sufficient to survive further processing of one or more of the bonded objects, but which bond can be disrupted with, for example, a mechanical force to permit separation of the two objects.
In some embodiments, a substrate, such as an interposer, having one or more through-vias is temporarily bonded to a carrier substrate by a surface modification layer. The carrier substrate provides support to the substrate having the one or more through-vias and can be useful when the substrate is thin as it can prevent the substrate from breaking during processing. Also, the use of the carrier can eliminate the need for plating all the surfaces of the substrate in order to fill the through-vias with an electrically conductive material using an electrolytic process. The carrier can have a seed layer applied thereon as an initiation site for depositing the electrically conductive material during an electrolytic plating process for filling the through-vias. Once the one or more through-vias are filled, the substrate with the one or more through-vias can be removed by breaking the temporary bond. This process can reduce or eliminate the formation of an overburden layer, and therefore the need to remove an overburden layer, from the substrate with the one or more through-vias.
Adhesive layer 106 can adhere seed layer 108 to first substrate 100 and can be any material suitable for accomplishing such. In some embodiments, adhesive layer 106 can be a metal adhesive layer and can include, but is not limited to, Cr, Ti, Mo, Ni, NiCr, Hf, Zr, Nd, Ta, V and W. Adhesive layer 106 can be applied using known techniques, for example sputtering. In some embodiments, adhesive layer 106 can have a thickness in a range from about 10 nm to about 500 nm, or from about 20 nm to about 100 nm.
Seed layer 108 can be an electrically conductive layer, which is relied on as a site for depositing the electrically conductive material that fills one or more through-vias during an electrolytic plating process as describe below. In some embodiments, seed layer 108 can include, but is not limited to, copper, silver, tungsten, titanium nitride, tantalum nitride, titanium tungsten, or copper alloys, such as a copper-tin alloy. In some embodiments, the seed layer material is chosen to impede the growth of grains. Seed layer 108 can be applied using known techniques, for example sputtering. In some embodiments, seed layer 108 can have a thickness in a range from about 50 nm to about 2,000 nm. In some embodiments, an initial seed layer can be formed by sputtering, for example to a thickness of in a range from about 100 nm to about 1,000 nm and then an additional deposition technique, for example, electrolytic plating or electroless plating, can be used to achieve a seed layer of a final desired thickness.
Next, as illustrated in
In some embodiments, surface modification layer 114 provides a temporary bond between first and second substrates 100, 110. In some embodiments, surface modification layer 114 chemically modifies and/or reduces the surface energy of second substrate 110 such that strong covalent or electrostatic bonds between second substrate 110 and seed layer 108 are limited. In some embodiments, first substrate 100 can be a carrier substrate that supports second substrate 110 while second substrate 110 is processed, for example during filling of through-vias 120. The temporary bond provided by surface modification layer 114 can be controlled such that the bond withstands the processing conditions (for example, temperature, pressure, etc.) to which assembly 112 is subjected to during processing of second substrate 110, but so that the bond can be broken after processing without damaging first and/or second substrate 100, 110. For example, in some embodiments, forming of surface modification layer can be controlled to ensure an adhesion energy between first and second substrates 100, 110 in a range from about 50 mJ/m2 to about 2,000 mJ/m2, from about 50 mJ/m2 to about 1,000 mJ/m2, or from about 100 mJ/m2 to about 2,000 mJ/m2. Exemplary surface modifications processes can include, but are not limited to, (1) plasma deposition of a plasma polymerized polymer films (for example, fluoropolymer films) on a surface as described in U.S. Pub. No. 2015/0120498 which is hereby incorporated by reference in its entirety, (2) deposition of a carbonaceous surface modification layer on a surface followed by incorporating polar groups with the carbonaceous surface modification layer as described in Int'l Pub. No. WO 2015/112958, which is hereby incorporated by reference in its entirety, or (3) treating a surface with a plasma selected from a fluoropolymer, the reaction products of a fluorinated etching agent, or a combination thereof as described in Int'l Pub. No. WO 2015/157202, which is hereby incorporated by reference in its entirety. Other suitable surface modification layers can include, but are not limited to, organosilicates, for example, organosilicates containing trimethyl groups; fluorosilanes; organosilicons; organogermaniums; fluoropolymers, including plasma fluoropolymers formed by plasma reaction of an etch gas, for example, CF4 with a polymer former such as, for example, H2, CHF3, C4F8, or CH4; organic plasma polymers, for example those formed from a hydrocarbon, for example, CH4, aliphatic hydrocarbons (for example alkanes, alkenes, or alkynes that have less than 8 carbons), benzene or aromatic hydrocarbons with less than 12 carbons. In some embodiments, surface modification layer 114 may have an elastic modulus of less than or equal to about 20 GPa, less than or equal to about 15 GPa, less than or equal to about 10 GPa, less than or equal to about 5 GPa, or less than or equal to about 1 GPa as measured by a diamond Berkovitch indenter test. As used herein, the “Berkovitch indenter test” includes a test to measure hardness on a surface by indenting the surface with a Berkovitch indenter to form an indent having an indentation depth of at least about 100 nm from the surface. Although surface modification layer 114 is shown as a solid layer between seed layer 108 and second substrate 110, this is merely exemplary. In some embodiments, surface modification layer 114 can cover 100%, less than 100%, from about 1% to 100%, from about 10% to 100%, from about 20% to about 90%, or from about 50% to about 90% of an interface between seed layer 108 and second substrate 110. In some embodiments, surface modification layer 114 can have a thickness in a range from about 0.1 nm to about 100 nm, from about 0.1 nm to about 10 nm, from about 0.1 nm to about 2 nm, from about 0.1 nm to about 1 nm, from about 0.1 nm to about 0.5 nm, or from about 0.1 nm to about 0.2 nm.
Next, as illustrated in
Subsequently, as illustrated in
In some embodiments, surface modification layer 401 chemically modifies and/or reduces the surface energy of first substrate 100 such that strong covalent or electrostatic bonds between first substrate 100 and seed layer 108 are limited. Suitable surface modification layers can include, but are not limited to, organosilicates, for example, organosilicates containing trimethyl groups; fluorosilanes; organosilicons; organogermaniums; fluoropolymers, including plasma fluoropolymers formed by plasma reaction of an etch gas, for example, CF4 with a polymer former such as, for example, H2, CHF3, C4F8, or CH4; organic plasma polymers, for example those formed from a hydrocarbon, for example, CH4, aliphatic hydrocarbons (for example alkanes, alkenes, or alkynes that have less than 8 carbons), benzene or aromatic hydrocarbons with less than 12 carbons.
In other embodiments, surface modification layer 401 can be a material that is insoluble and sufficiently stable in solutions used during interposer fabrication, but is soluble in a solution not used during interposer fabrication. Examples of such a material can include, but are not limited to, novolac resins (phenol-formaldehyde resins with a formaldehyde to phenol molar ratio of less than 1), acrylic polymers, or epoxide polymers.
In still other embodiments, surface modification layer 401 can be a material that is irreversibly changed by a reaction to reduce the adhesion between first substrate 110 and seed layer 108. The reaction can be caused by heat, ultraviolet radiation, microwave irradiation, or other energy source. The reaction can change the structure or conformation of a polymer surface modification layer 401, or release gaseous or liquid by-products from a reaction or state change. Examples of a suitable surface modification layer 401 can include implanting a species on first substrate 100 (for example hydrogen), a helium in silicon layer, an amorphous silicon (a-Si), or a plurality of layers that can be delaminated by a reaction such as having adjacent layers of amorphous silicon and fluorinated silica glass.
Although surface modification layer 401 is shown as a solid layer between seed layer 108 and first substrate 100, this is merely exemplary. In some embodiments, surface modification layer 401 can cover 100%, less than 100%, from about 1% to 100%, from about 10% to 100%, from about 20% to about 90%, or from about 50% to about 90% of an interface between seed layer 108 and first substrate 100. In some embodiments, surface modification layer 401 can have a thickness in a range from about 0.1 nm to about 100 nm, from about 0.1 nm to about 10 nm, from about 0.1 nm to about 2 nm, from about 0.1 nm to about 1 nm, from about 0.1 nm to about 0.5 nm, or from about 0.1 nm to about 0.2 nm.
As mentioned above, surface modification layer 114 between seed layer 108 and second substrate 110 can be optional. In such instances, seed layer 108 and surface modification layer 401 can remain on second substrate 110 and can be removed using traditional techniques, for example chemical mechanical polishing (CMP).
In any of the above embodiments, prior to filling through-vias 120 with conductive material 122, second substrate 110 can be coated with an adhesion layer 530 and separate seed layer 532 (as shown in
Thus, disclosed herein is a bottom-up electrolytic via plating method wherein a first carrier substrate and a second substrate having at least one through-via are temporarily bonded together while the through-hole is filled with a conductive material, and after application of the conductive material, the second substrate can be removed from the assembly by breaking the temporary bond between the first and second substrates.
It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention.
This application claims the benefit of priority under 35 U.S.C. § 119 of U.S. Provisional Application Ser. No. 62/075,326 filed on Nov. 5, 2014 the content of which is relied upon and incorporated herein by reference in its entirety.
Number | Name | Date | Kind |
---|---|---|---|
5814889 | Gaul | Sep 1998 | A |
6472023 | Wu et al. | Oct 2002 | B1 |
6503343 | Tench et al. | Jan 2003 | B1 |
6627066 | Isayama et al. | Sep 2003 | B1 |
6699798 | Rockford | Mar 2004 | B2 |
6703712 | Gilkes et al. | Mar 2004 | B2 |
6802946 | Basol et al. | Oct 2004 | B2 |
6928726 | Zollo et al. | Aug 2005 | B2 |
7220347 | Isono et al. | May 2007 | B2 |
7754061 | Basol | Jul 2010 | B2 |
7863189 | Basker et al. | Jan 2011 | B2 |
8811061 | Tsuji et al. | Aug 2014 | B2 |
8883640 | Patton et al. | Nov 2014 | B1 |
9093506 | Shen | Jul 2015 | B2 |
9231068 | Shen | Jan 2016 | B2 |
9232652 | Fushie et al. | Jan 2016 | B2 |
9240373 | Ebefors et al. | Jan 2016 | B2 |
9240392 | Hurwitz et al. | Jan 2016 | B2 |
9278886 | Boek et al. | Mar 2016 | B2 |
9517963 | Marjanovic et al. | Dec 2016 | B2 |
9607822 | Buckalew | Mar 2017 | B2 |
9806006 | Li et al. | Oct 2017 | B2 |
10383572 | Knickerbocker et al. | Aug 2019 | B2 |
20010024872 | Miyamoto | Sep 2001 | A1 |
20020039464 | Yoshimura et al. | Apr 2002 | A1 |
20030000846 | Rzeznik et al. | Jan 2003 | A1 |
20030089986 | Gilkes et al. | May 2003 | A1 |
20040003894 | Hsu et al. | Jan 2004 | A1 |
20040170753 | Basol | Sep 2004 | A1 |
20040187731 | Wang et al. | Sep 2004 | A1 |
20050121317 | Klocke et al. | Jun 2005 | A1 |
20050151824 | Iwamatsu et al. | Jul 2005 | A1 |
20060046432 | Sankarapillai | Mar 2006 | A1 |
20060046455 | Nitta | Mar 2006 | A1 |
20060081477 | Basol | Apr 2006 | A1 |
20070051635 | Basol | Mar 2007 | A1 |
20070202686 | Dixit | Aug 2007 | A1 |
20080164573 | Basker et al. | Jul 2008 | A1 |
20110284495 | Li et al. | Nov 2011 | A1 |
20120013012 | Sadaka | Jan 2012 | A1 |
20120064717 | Kato et al. | Mar 2012 | A1 |
20120080214 | Weaver et al. | Apr 2012 | A1 |
20120080762 | Foster et al. | Apr 2012 | A1 |
20130062210 | Fushie et al. | Mar 2013 | A1 |
20130299985 | Shen | Nov 2013 | A1 |
20130313121 | Yu | Nov 2013 | A1 |
20140199519 | Schillinger et al. | Jul 2014 | A1 |
20150083469 | Sunohara et al. | Mar 2015 | A1 |
20150102498 | Enicks et al. | Apr 2015 | A1 |
20150115393 | Shen | Apr 2015 | A1 |
20150120498 | Carney et al. | Apr 2015 | A1 |
20150262874 | Van'T Oever et al. | Sep 2015 | A1 |
20150311154 | Sunohara | Oct 2015 | A1 |
20160020146 | Shen | Jan 2016 | A1 |
20160113119 | Cordes | Apr 2016 | A1 |
20160128202 | Bellman et al. | May 2016 | A1 |
20160237571 | Liu et al. | Aug 2016 | A1 |
20160336179 | Mizutani et al. | Nov 2016 | A1 |
20160353584 | Honda et al. | Dec 2016 | A1 |
20170156209 | Wang et al. | Jun 2017 | A1 |
20170194199 | Chang et al. | Jul 2017 | A1 |
20170229565 | Jun et al. | Aug 2017 | A1 |
20170287728 | Dahlberg et al. | Oct 2017 | A1 |
20190024237 | Jayaraman | Jan 2019 | A1 |
Number | Date | Country |
---|---|---|
101226891 | Jul 2008 | CN |
102537064 | Jul 2012 | CN |
102737961 | Oct 2012 | CN |
103199054 | Jul 2013 | CN |
103594627 | Feb 2014 | CN |
104485288 | Apr 2015 | CN |
103474510 | Mar 2016 | CN |
107240624 | Oct 2017 | CN |
2011235532 | Nov 2011 | JP |
1020100043811 | Apr 2010 | KR |
101124784 | Feb 2012 | KR |
101221376 | Jan 2013 | KR |
2014093740 | Jun 2014 | WO |
2015112958 | Jul 2015 | WO |
2015157202 | Oct 2015 | WO |
Entry |
---|
US 9,190,356 B2, 11/2015, Ebefors et al. (withdrawn) |
International Search Report and Written Opinion of the International Searching Authority; PCT/US2015/059126; dated Feb. 9, 2016; 12 Pages. |
“Bottom-up copper electroplating using transfer wafers for fabrication of high aspect-ratio through-silicon-vias”; Song, Chongshen (Institute of Microelectronics, Tsinghua University, Beijing, 100084, China); Wang, Zheyao; Liu, Litian Source: Microelectronic Engineering, v 87, n 3, p. 510-513, Mar. 2010. |
Zoschke et al. “Polyimide based temporary wafer bonding technology for high temperature compliant TSV backside processing and thin device handling”, SUSS Report, Feb. 2012, 11 pgs. |
Andricacos; “Copper On-Chip Interconnectons a Breakthrough in Electrodeposition to Make Better Chips”; The Electrochemical Society Interface, Spring 1999; pp. 32-37. |
Cao et al; “Wafer-Level Package With Simultaneous TSV Connection and Cavity Hermetic Sealing by Solder Bonding for MEMS Device”; IEEE Transactions on Electronics Packaging Manufacturing; vol. 32; No. 3; (2009) pp. 125-132. |
Carano, “Via hole filling technology for high density, high aspect ratio printed wiring boards using a high Tg, low CTE plugging paste,” IPC Printed Circuits Expo, APEX and the Designers Summit, 2007, vol. 3. pp. 1729-1739. |
Demirkiran et al; “Recovering of Copper With Metallic Aluminum”; Trans. Nonferrous Met. Soc. China; 21 (2011) pp. 2778-2782. |
Jayaraman et al; “Methods for Making Electrodes and Providing Electrical Connections in Sensors”; filed as PCT/US2018/067812 dated Dec. 28, 2018; 42 Pages—Listed in ID as ID27927. |
Kunces; “Chemical Deposition of Metallis Films From Aqueous Solutions”; Electroless Plating: Fundamentals and Applications; Chapter 19; pp. 511-517; (1990. |
Kutchoukov et la; “Through-Wafer Interconnect Technology for Silicon”; J. Micromech. Microeng. 14 (2004) pp. 1029-1036. |
Lee et al; “Through-Glass Copper Via Using the Glass Reflow and Seedless Electroplating Processes for Wafer-Level RF MEMS Packaging”; J. Micromech. Microeng.; 23; (2013) 085012 ; 10 Pages. |
Liu et al; “Electroless Nickel Plating on AZ91 Mg Alloy Substrate”; Surface & Coatings Technology; 200 (2006) pp. 5087-5093. |
Moffat et al; “Electrochemical Processing of Interconnects”; Journal of the Electrochemical Society; 160 (12) Y7-Y10 (2013. |
Nguyen et al; “Through-Wafer Copper Electorplating for Three-Dimensional Interconnects”; J. Micromach. Microeng. 12 (2002) pp. 395-399. |
Ogutu et al; “Hybrid Method for Metallization of Glass Interposers”; Journal of the Electrochemical Society; 160 (12) D3228-D3236 (2013. |
Ogutu et al; “Superconformal Filling of High Aspect Ratio Through Glass Vias (TGV) for Interposer Applications Using TNBT and NTBC Additives”; Journal of the Electrochemical Society; 162 (9) D457-D464 (2015. |
Pearson et al; “The Effect of Pulsed Reverse Current on the Polarization Behaviour of Acid Copper Plating Solutions Containing Organic Additives”; Journal of Applied Electrochemistry, 20 (1990) 196-208. |
Vaillancourt et al. “Adhesive Technology: Surface preparation techniques on aluminum,” Worchester Polytechnic Institute (WPI) 2009, 171 pgs. |
Vanysek; “Electrochemical Series”; CRC Handbook of Chemisty and Physics; 92nd Edition 2011-2012; 12 Pages. |
Wolf et al; “High Aspect Ratio TSV Copper Filling With Different Seed Layers”; IEEE; 2008 Electronic Components and Technology Conference; pp. 563-570. |
Xu et al; “Direct Copper Plating on Ultra-Thin Sputtered Cobalt Film in an Alkaline Bath”; Journal of the Electrochemical Society, 160 (12) D3075-D3080 (2013. |
Chinese Patent Application No. 201580072215.7; English Translation of the Office Action dated Jan. 6, 2020; China Patent Office; 13 Pgs. |
English Translation of CN201580072215.7 Office Action dated Jun. 23, 2020; 12 Pages; Chinese Patent Office. |
Number | Date | Country | |
---|---|---|---|
20160128202 A1 | May 2016 | US |
Number | Date | Country | |
---|---|---|---|
62075326 | Nov 2014 | US |