Patent Application
20250081348
Embodiments of the present disclosure generally relate to package assemblies, and in particular package assemblies that include a printed circuit board embedded within a top layer of another printed circuit board.
Continued reduction in end product size of mobile electronic devices such as smart phones and ultrabooks is a driving force for the development of reduced size system in package components, and for increased speed between processing units and memory.
Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to forming a PCB within one or more metal layers of another PCB, which may be referred to as a main PCB. In embodiments, the formed PCB may be referred to as a bridge PCB. In embodiments, the bridge PCB may be formed between two metal layers of the main PCB, and in particular may be formed between the first and the second metal layers of the main PCB.
In embodiments, the bridge PCB may be used to provide high-speed data connections between a first die and a second die that are on the main PCB and that may be both electrically coupled with the bridge PCB. In some embodiments, the first die may be a system on chip (SOC) and the second die may be a memory die. In embodiments, the memory dies may include a high-bandwidth memory (HBM), a double data rate (DDR) memory, or some other memory die. In embodiments, the bridge PCB may be used to route high speed I/O (HSIO) signals between the first die and the second die. In embodiments, the bridge PCB may be used to route only HSIO signals, where power may be routed through the first die and the second die through the metal layers within the main PCB.
In embodiments, the bridge PCB may be manufactured using a modified semi-additive process (mSAP) technique. In embodiments, the mSAP technique may involve a very thin copper layer that is first formed on the surface of PCB material. Any lines that do not need to be retained are covered with a coating, and then the required lines are exposed and are added by electroplating. Then, after removing the coating, the thin copper layer that has not been thickened is removed by micro-etching, and the required circuit is formed. This is in contrast to the subtractive process, where a PCB laminate is covered with a layer of copper foil, the lines that need to be retained are covered with the coating, and the exposed copper foil is removed by etching to form the required lines.
The mSAP technique may be used to achieve a smaller trace width, for example less than 25 μm, within the bridge PCB. These traces may be substantially smaller than the 50 μm trace width in FR4 PCB technologies. In embodiments, this allows a break out of more signals between the 0.4 mm pitch, and may allow a memory die to be placed closer to the SOC die.
In addition, embodiments may increase the maximum available memory speed between the SOC and the memory die. Maximum signal frequency depends on a variety of factors, including signal breakout from the first die and the second die, routing within the PCB, via structure within the main PCB, and overall routing length. In embodiments, by embedding a bridge PCB within the top two metal layers of the main PCB, these factors may be optimized for greater bandwidth performance.
In legacy implementations, where signals between a SOC and a memory die needed to be routed through multiple layers of a main PCB, greater routing length down into lower metal layers of the main PCB for high-speed signal routing is required. In addition, these legacy implementations also require metal layers above and below the high-speed signal routing layers to serve as reference planes to reduce electromagnetic interference to promote signal integrity through the legacy PCB. Furthermore, due to routing constraints, in legacy implementations the distance between the SOC and memory die needs to be increased to prevent HSIO signal interference experienced by the breakout between the first die and the legacy PCB and the second die in the legacy PCB.
In these legacy implementations, for memory on package SoC designs, substrate cost may be increased up to 30% due to memory die placement involving requiring additional area. Achieving a maximum capable memory speed is more critical with FR4 PCBs. The maximum frequency target depends on signal breakout, main routing, via structures to route down to signal layers, routing length and memory component placements in FR4 PCBs where the signal breakout between BGA balls adds impedance constraints as well as limits the amount of signal routing. Break out impedance, via, and the max length routing play vital role for defining the memory speed support due to signal integrity and manufacturing constraints.
In legacy implementations, a maximum of one signal can be made possible for breaking out between the BGA balls with the pitch of 0.4 mm. Therefore, for legacy implementations only based upon on Type-3/Type-4 Stack-up, signal breakout, component placement, layer count and signal routings are planned with signal integrity and fabrication constraints in mind. As a result, a minimum of four layers are required to route HSIO signals and provide reference planes for those signals. In addition, SOC to memory placement in legacy implementations also requires minimum 4 mm to allow the signal breakout and provide space for routing.
Embodiments described herein may also reduce the overall cost of the systems created with the bridge PCB implemented using a mSAP process. Because the resulting bridge PCB will have a fewer number of layers and multiple bridge PCBs can be formed on a single panel, the cost of producing a bridge PCB can be cheaper and more reliable than forming routing layers within a legacy PCB and drilling to connect the routing layers. In embodiments, embedding and mSAP-based bridge PCB into a FR4 PCB (motherboard) has the advantage of eliminating motherboard system integrity and core area constraints. In embodiments, the bridge PCB design may be used for any memory technology configurations.
In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
The description may use perspective-based descriptions such as top/bottom, in/out, over/under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.
The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
The term “coupled with,” along with its derivatives, may be used herein. “Coupled” may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term “directly coupled” may mean that two or more elements are in direct contact.
Various operations may be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent.
As used herein, the term “module” may refer to, be part of, or include an ASIC, an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.
Various Figures herein may depict one or more layers of one or more package assemblies. The layers depicted herein are depicted as examples of relative positions of the layers of the different package assemblies. The layers are depicted for the purposes of explanation, and are not drawn to scale. Therefore, comparative sizes of layers should not be assumed from the Figures, and sizes, thicknesses, or dimensions may be assumed for some embodiments only where specifically indicated or discussed.
Various embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above-described embodiments.
In this legacy example, metal layers L2, L4, and L6 are reference planes, and metal layers L3, L5 are signal layers. Metal layer L7 a power plane. Therefore, to make the system 100 operational, solder balls 114a of SOC 104 are electrically coupled to the power plane L7 in the lower layer of the legacy PCB 102, and the solder ball 116a of the memory 106 is electrically coupled to the power plane L7.
In this implementation, the solder balls 114b of the SOC 104 that conduct the signals are electrically coupled with the signal layers L3 or L5. Similarly, the solder balls 116b of the memory 106 that conduct the signals are electrically coupled with the signal layers L3 or L5. Note that in these legacy implementations, the power plane L7 is furthest from the SOC 104 and the memory 106, to allow the signal layers L3, L5 to be closer and therefore reduce the distance between the SOC 104 and the memory 106 and therefore increase the speed of the signals.
As shown with respect to
In legacy implementations, the dielectric material between the metal layers L1-L8 may be a glass fiber/epoxy material, however different dielectric materials may be used. In addition, manufacturing and material cost in legacy system 100 is a large fraction of the overall cost, including routing cost that requires a vias 117 through the legacy PCB 102 to route the high-speed signals.
In a typical FR4 PCB pitches legacy PCB 102 has fabrication constraints to achieve the trace impedance, routing the signal between SOC 104 component pad that includes solder balls 114b, vias 117, and the like, and signal integrity guideline requirements. As a result, routing high speed memory signals between the SOC 104 and memory 106 may be difficult. Because of these signal integrity and fabrication constraints, placement of the memory 106 and the resulting increase in routing length add trace losses which degrade the signal quality. This leads to lower the speed bin and as a result is unable to achieve maximum capable memory data rates otherwise supported by the SOC 104 and the memory 106.
In embodiments, a layer 203, which may be between top metal layer L1 and metal layer L2, may include a bridge PCB 230. The bridge PCB 230 may be referred to as an Embedded Device Internet Bridge (EDIB). The bridge PCB 230 is explained in further detail with respect to
In embodiments, the SOC 204 may receive power, ground, controller signals, or other electrical connections through the solder balls 214a. In embodiments, the solder balls 214a may be electrically coupled with various metal layers, such as layers L2 or L6, within the main PCB 202. Similarly, the memory 206 may receive power, ground, controller signals, or other electrical connections through the solder balls 216a. In embodiments, the solder balls 216a may be electrically coupled with various metal layers, such as L2 or L6, within the main PCB 202.
The SOC 204 may be electrically coupled through solder balls 214b with the bridge PCB 230, and the memory 206 may be electrically coupled through solder balls 216b with the bridge PCB 230. In embodiments, the solder balls 214a, 214b, 216a, 216b may be similar to solder balls 114a, 114b, 116a, 116b of
In embodiments, the bridge PCB 230 may include solder balls 232, 233 that electrically couple with each other using routings within the bridge PCB 230 (not shown). In embodiments, the solder balls 214b may electrically couple with the solder balls 232 of the bridge PCB 230 using vias 224. In embodiments, the solder balls 216b may electrically couple with the solder balls 233 of the bridge PCB 230 using the vias 226.
In embodiments, the vias 224, 226 may be referred to as openings, and may be implemented as micro vias that may extend through the L1 layer of the main PCB 202, which also may be referred to as the top layer. In embodiments, an electrically conductive material may be placed into all or part of the vias 226 to provide an electrical connection between the solder balls 214b, 216b and the bridge PCB 230. In other embodiments, the bridge PCB 230 may be placed between other layers within the main PCB 202, for example between layers L2 and L3, or between layers L2 and L4, with a portion of L2 removed to accommodate the bridge PCB (not shown).
In embodiments, a thickness of the layer 203 between L1 and L2, may be based upon the thickness of the bridge PCB 230. In embodiments, pads (not shown) may be formed within the L1 layer of the main PCB 202 and used to couple with the SOC 204 and the memory 206. In some of these embodiments, the SOC 204 and the memory 206 may be coupled to the main PCB 202 using direct bonding or hybrid bonding.
In embodiments, the main PCB 202 may also be referred to as a main board, and may be fabricated with typical FR4 material and may be implemented as a FR4 “0-x-0+” stack up. Note that in embodiments, because of the bridge PCB 230 providing HSIO routing, an 8 layer PCB board is not needed and the layers may be reduced because signal routing layers within the legacy PCB, such as legacy PCB 102 of
In embodiments discussed below, one or more bridge PCBs 230 may be associated with multiple SOC 204, and multiple memories 206. When fabricating the system 200, although there may be additional cost inserting the bridge PCB 230 into the layer 203, the resulting memory routing significantly benefits from high-speed signals routing through the bridge PCBs 230. For example, there may be 64 different signals for each channel (2 channels is 128), all at high-speed, and all routed through the bridge PCB 230. The result may be over 300 high speed signals.
In embodiments, the connection pads 332 may be solder balls or micro bumps. The SOC 304, memory 306, bridge PCB 330, solder ball 314b, solder ball 316b, and vias 324, 326 may be similar to SOC 204, memory 206, bridge PCB 230, solder ball 214b, solder ball 216b, and the vias 224, 226 of
The bridge PCB 330 may include a first metal layer 330a, a second metal layer 330b, and a third metal layer 330c. In embodiments, the metal layers 330a, 330b, 330c may be separated by a dielectric material 331, such as a prepeg material. In embodiments, the metal layers 330a, 330b, 330c may have a thickness of around 15 μm, and the dielectric material 331 may have a thickness of around 27 μm. In embodiments, the number of metal layers and/or thickness of the metal layers may vary. In embodiments, the thickness and/or material composition of the dielectric material 331 may also vary. The overall thickness of the bridge PCB 330 may be around 99 μm as shown, however this overall thickness may vary depending upon embodiments. In embodiments, the thickness may be low enough to allow the bridge PCB 330 to be placed between L1 and L2.
In embodiments, the metal layers 330a, 330b, 330c may have various configurations. For example, metal layer 330a and metal layer 330c may route HSIO signals, and metal layer 330b may be a ground plane. In some embodiments, layer L1 may also be a ground plane in order to improve signal integrity within metal layer 330a.
In embodiments, shielding 340, which may be a dielectric, may be placed on one or both sides of the bridge PCB 330. In embodiments, the shielding 340, in addition to providing electromagnetic interference shielding, may also provide additional strength to the bridge PCB 330. This additional strength may be useful while the vias 324, 326 through the metal layer L1 may be formed, for example, during drilling of the vias 324, 326. In embodiments, vias (not shown) may route signals between the connection pads 332 and the metal layers within the bridge PCB 330 that may be used for routing, for example metal layer 330a and metal layer 330c.
In embodiments, the bridge PCB 330 architecture as described with respect to system 300 may result in a 30% substrate cost-reduction as compared to legacy memory on package techniques, may achieve a maximum SOC-capable memory speed, provides flexibility to choose different memory configurations, provides a compact PCB core area, eliminates the PCB SI constraints due to reduced interference, reduces the main PCB layer count by at least two metal layers as discussed above, and enables a thinner system 300 implementation. In addition, embodiments using a bridge PCB 330 may result in a lower cost as compared to type 3 PCBs, because it has more layers Vs 0-x-0+ with the mSAP PCB.
In addition, as discussed above, in embodiments when the bridge PCB 330 is implemented using mSAP technology may enable a breakout of more than one signal between 0.4 mm BGA pitch and may enable the placement of memory 306 as close as ˜150 to 200 μm to the SOC 304. In embodiments, a 0.4 mm BGA pitch may be used for both SOC 304 and memory 306. Also, the memory signal BGA ball 316b may be arranged in such a way to easily breakout the signals and make the 1:1 connection with the SOC BGA ball 314b.
Use of mSAP techniques to create the bridge PCB 330 allows much finer routing structures down to 25 μm line/space. In addition, these techniques offer a significantly better conductor pattern geometry. For high-frequency applications, this may offer significant performance advantages.
Trace 440 shows an example trace between a connection pad 432 within region 404 that may be associated with a SOC such as SOC 204 of
In embodiments, a bridge PCB 530, which may be similar to bridge PCB 230 of
The solder balls 516b of the first DRAM 506 may be coupled with a first group of a second set of solder balls (not shown) of the bridge PCB 530, but which may be similar to solder balls 233 of
Subsequent stages in the process may include attaching metal layers and dielectric layers below metal layer 752. After these attached metal layers and dielectric layers are formed, drilling and/or etching processes may be performed to interconnect the attached metal layers and to provide electrical routing.
At block 802, the process may include creating a first metal layer of a first PCB. In embodiments, the first metal layer may be similar to layer L2 of
At block 804, the process may further include placing a second PCB on the first metal layer of the first PCB. In embodiments, the second PCB may be similar to bridge PCB 230 of
At block 806, the process may further include placing a second metal layer of the first PCB on a top of the second PCB. In embodiments, the second metal layer may be similar to layer L1 of
At block 808, the process may further include forming a plurality of openings that extend through the second metal layer and expose a portion of the second PCB. In embodiments, the plurality of openings may be similar to vias 224, 226 of
In an embodiment, the electronic system 900 is a computer system that includes a system bus 920 to electrically couple the various components of the electronic system 900. The system bus 920 is a single bus or any combination of busses according to various embodiments. The electronic system 900 includes a voltage source 930 that provides power to the integrated circuit 910. In some embodiments, the voltage source 930 supplies current to the integrated circuit 910 through the system bus 920.
The integrated circuit 910 is electrically coupled to the system bus 920 and includes any circuit, or combination of circuits according to an embodiment. In an embodiment, the integrated circuit 910 includes a processor 912 that can be of any type. As used herein, the processor 912 may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, the processor 912 includes, or is coupled with, a bridge printed circuit board embedded within another printed circuit board, as disclosed herein. In an embodiment, SRAM embodiments are found in memory caches of the processor. Other types of circuits that can be included in the integrated circuit 910 are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit 914 for use in wireless devices such as cellular telephones, smart phones, pagers, portable computers, two-way radios, and similar electronic systems, or a communications circuit for servers. In an embodiment, the integrated circuit 910 includes on-die memory 916 such as static random-access memory (SRAM). In an embodiment, the integrated circuit 910 includes embedded on-die memory 916 such as embedded dynamic random-access memory (eDRAM).
In an embodiment, the integrated circuit 910 is complemented with a subsequent integrated circuit 911. Useful embodiments include a dual processor 913 and a dual communications circuit 915 and dual on-die memory 917 such as SRAM. In an embodiment, the dual integrated circuit 910 includes embedded on-die memory 917 such as eDRAM.
In an embodiment, the electronic system 900 also includes an external memory 940 that in turn may include one or more memory elements suitable to the particular application, such as a main memory 942 in the form of RAM, one or more hard drives 944, and/or one or more drives that handle removable media 946, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. The external memory 940 may also be embedded memory 948 such as the first die in a die stack, according to an embodiment.
In an embodiment, the electronic system 900 also includes a display device 950, an audio output 960. In an embodiment, the electronic system 900 includes an input device such as a controller 970 that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system 900. In an embodiment, an input device 970 is a camera. In an embodiment, an input device 970 is a digital sound recorder. In an embodiment, an input device 970 is a camera and a digital sound recorder.
As shown herein, the integrated circuit 910 can be implemented in a number of different embodiments, including a package substrate having a bridge printed circuit board embedded within another printed circuit board, according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes a package substrate having a bridge printed circuit board embedded within another printed circuit board, according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including array contact count, array contact configuration for a microelectronic die embedded in a processor mounting substrate according to any of the several disclosed package substrates having a bridge printed circuit board embedded within another printed circuit board embodiments and their equivalents. A foundation substrate may be included, as represented by the dashed line of
Although certain embodiments have been illustrated and described herein for purposes of description, a wide variety of alternate and/or equivalent embodiments or implementations calculated to achieve the same purposes may be substituted for the embodiments shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that embodiments described herein be limited only by the claims.
Where the disclosure recites “a” or “a first” element or the equivalent thereof, such disclosure includes one or more such elements, neither requiring nor excluding two or more such elements. Further, ordinal indicators (e.g., first, second or third) for identified elements are used to distinguish between the elements, and do not indicate or imply a required or limited number of such elements, nor do they indicate a particular position or order of such elements unless otherwise specifically stated.
Various embodiments may include any suitable combination of the above-described embodiments including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the “and” may be “and/or”). Furthermore, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above-described embodiments.
The above description of illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit embodiments to the precise forms disclosed. While specific embodiments are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the embodiments, as those skilled in the relevant art will recognize.
These modifications may be made to the embodiments in light of the above detailed description. The terms used in the following claims should not be construed to limit the embodiments to the specific implementations disclosed in the specification and the claims. The following claims are to be construed in accordance with established doctrines of claim interpretation.
The following paragraphs describe examples of various embodiments.
Example 1 is an apparatus comprising: a first PCB that includes a plurality of metal layers; a second PCB within the first PCB, wherein the second PCB is between a first metal layer and a second metal layer of the plurality of metal layers of the first PCB; and wherein at least a portion of the first metal layer is above the second PCB, and wherein at least a portion of the second metal layer is below the second PCB.
Example 2 includes the apparatus of example 1, wherein there are no intervening metal layers in the first PCB between the first metal layer of the first PCB and the second metal layer of the first PCB.
Example 3 includes the apparatus of example 2, wherein the first metal layer is a top of the first PCB.
Example 4 includes the apparatus of examples 1, 2, or 3, wherein a first side of the second PCB includes a first insulator layer that is proximate to the first metal layer of the first PCB, and wherein a second side of the second PCB opposite the first side includes a second insulator layer that is proximate to the second metal layer of the first PCB.
Example 5 includes the apparatus of examples 1, 2, 3, or 4, wherein the second PCB is manufactured using a modified semi-additive process (mSAP).
Example 6 includes the apparatus of examples 1, 2, 3, 4, or 5, further comprising a dielectric material between the first metal layer and the second metal layer; and wherein the dielectric material is in direct physical contact with at least a portion of the second PCB.
Example 7 includes the apparatus of examples 1, 2, 3, 4, 5, or 6, further comprising one or more vias that extend through the first metal layer of the first PCB.
Example 8 includes the apparatus of example 7, further comprising electrically conductive material in the one or more vias that electrically couple with the second PCB.
Example 9 includes a system comprising: a first PCB that includes a plurality of metal layers; a second PCB within the first PCB, wherein the second PCB is between a first metal layer and a second metal layer of the plurality of metal layers of the first PCB, wherein at least a portion of the first metal layer is above the second PCB, and wherein at least a portion of the second metal layer is below the second PCB; a plurality of openings that extend through the first metal layer of the first PCB, wherein the plurality of openings are filled with electrically conductive material, and wherein the electrically conductive material in the plurality of openings are electrically coupled with the second PCB; a first die on the first metal layer of the first PCB, wherein the first die is electrically coupled with the electrically conductive material in a first group of the plurality of openings; a second die on the first metal layer of the first PCB, wherein the second die is electrically coupled with the electrically conductive material in a second group of the plurality of openings; and wherein the first die in the second die are electrically coupled through the second PCB.
Example 10 includes the system of example 9, wherein the second PCB includes a plurality of electrically conductive traces to electrically couple the first die in the second die, wherein the plurality of electrically conductive traces have a width of less than 25 μm.
Example 11 includes the system of examples 9 or 10, wherein the second PCB includes a ball grid array (BGA) on a side of the second PCB, wherein the BGA is electrically coupled with the electrically conductive material in the plurality of openings.
Example 12 includes the system of example 11, wherein the BGA has a pitch of 0.4 mm or less.
Example 13 includes the system of examples 9, 10, 11, or 12, wherein the first die is a system on chip (SOC), and wherein the second die is a memory die.
Example 14 includes the system of example 13, wherein a distance between an edge of the second die and an edge of the first die is less than 200 μm.
Example 15 includes the system of examples 9, 10, 11, 12, 13, or 14, wherein the second die is a plurality of second dies, wherein the second group of the plurality of openings is a plurality of second groups of the plurality of openings and wherein each of the plurality of second dies, and wherein each of the plurality of second dies is electrically coupled with the first die through the second PCB.
Example 16 includes the system of examples 9, 10, 11, 12, 13, 14, or 15, wherein high speed input/output (HSIO) signals are routed through the second PCB.
Example 17 includes the system of examples 9, 10, 11, 12, 13, 14, 15, or 16, wherein a total number of the plurality of metal layers of the first PCB is 6 metal layers or fewer.
Example 18 includes the system of examples 9, 10, 11, 12, 13, 14, 15, 16, or 17, wherein the second PCB is manufactured using a modified semi-additive process (mSAP).
Example 19 is a method comprising: creating a first metal layer of a first printed circuit board (PCB); placing a second PCB on the first metal layer of the first PCB; placing a second metal layer of the first PCB on a top of the second PCB; and forming a plurality of openings that extend through the second metal layer and expose a portion of the second PCB.
Example 20 includes the method of example 19, wherein placing the second PCB on the first metal layer of the first PCB further includes at least partially surrounding the second PCB with dielectric material, wherein the dielectric material is on the first metal layer of the first PCB.
