Patent Application
20230352441
This Disclosure relates to a flipchip semiconductor package.
A flipchip semiconductor package generally includes a solder connection between bumps on bond pads of a semiconductor die and bonding feature on a package substrate, such as leads of a leadframe. The bumps generally comprise solder balls or copper pillars. Upon placement of the semiconductor die on the package substrate, there is generally a solder reflow step performed at a temperature of at least 220° C. to form the solder joint.
This Summary is provided to introduce a brief selection of disclosed concepts in a simplified form that are further described below in the Detailed Description including the drawings provided. This Summary is not intended to limit the claimed subject matter's scope.
Disclosed aspects recognize there can be reliability issues on flipchip devices due to non-wet or an insufficient solder joint connection induced by solder flux dry up and solder inactivation during flipchip die attach. This problem can be attributed to a long window of time between die attach and the solder reflow process.
Disclosed aspects include a method of assembling a flipchip semiconductor package, comprising placing a semiconductor die having circuitry electrically coupled to bond pads having a bump thereon generally comprising a solder ball or copper pillar, with solder paste thereon, onto bonding features of a package substrate. Arc welding is utilized using an arc welding apparatus comprising an arm and a biased electrode having a tip spaced apart from the solder paste, wherein electrical current generated by the arc welding melts the solder to provide a solder connection.
Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, wherein:
Example aspects are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this Disclosure.
Although not shown, there is generally under bump metallization (UBM) under the bump 122. Solder flux generally comprises a base solder material and an activator which is the chemical that promotes better wetting of the solder by removing oxides from the solder metal material. The package substrate can also comprise a printed circuit board (PCB), Roughened/Rough Lead Frame (RLF), Molded Interconnect Substrate (MIS), Etched Lead Frame, or a Pre-plated Lead Frame, that provides the bonding features.
There is generally no direct current return path provided for the arc welding apparatus, where the leadframe or other package substrate can instead be grounded indirectly by the holder of the package substrate which is itself grounded for the current to be terminated and a connection to the power supply of the arc welding apparatus to provide a ground for the power supply, and to also serve as a protection for the semiconductor die 120.
Arc welding as used herein takes on its conventional definition being a welding process that is used to join metal to metal by using electricity (displacement current) to create enough heat to melt metal, and the melted metals, when cool, result in a binding together of the respective metals. A welding power supply is used to create an electric arc between a metal stick (tip functioning as an electrode) and the base material to melt the metals at the point of contact. Arc welders can use either direct (DC) or alternating (AC) current.
The bumps can include pillars or sider balls. The method generally excludes a solder reflow step. The method can include flux washing after the application of the electrical current. As noted above, the arc welding apparatus used for the method can include a plurality of biased electrodes, wherein the arc welding simultaneously forms a plurality of the solder connections.
The package substrate can comprise a leadframe, where the bonding features comprise leads. The tip can be positioned at an angle from 15 to 45° relative to a normal drawn from a top surface of the package substrate. The bond pads are generally all positioned along a periphery of the semiconductor die, such as being in a rectangular or circular shape. The electrical current can be in a range from 60 mA to 200 mA and can be applied for a time between 0.5 msec-and 1.3 msec solder paste for best results. Using electrical current outside the range of 60 mA to 200 mA and/or applying the electrical current for a time outside the range of 0.5 msec and 1.3 msec can lead in some cases to partial, incomplete or less satisfactory reflow of solder paste 126.
