The present invention relates generally to fabrication of integrated circuits, and more particularly to the deposition of bump materials within the manufacturing of flip chips.
Integrated circuits (IC) are increasing in complexity. The number of devices incorporated within a single IC is greatly increasing and causing the size and complexity of individual ICs to increase. As a result of increased component density and improved fabrication technology is the realization of system on chip (SoC) applications. Such a system on a chip may include many logic and memory functions within it. For example, the core may include a CPU core, DSP core, DSP book, memory, control circuitry and analog/mixed signal circuitry. These are just examples of the types of systems or components that may be integrated into a signal chip.
Complexities are associated with the realization of SoC designs. Incorporating diverse components previously contained within a single printed circuit board (PCB) involves confronting many design challenges. The components may be designed for different entities using different tools. Other difficulties lie in fabrication. In general, fabrication processes of memory may differ significantly from those associated with logic circuits. For example, speed may be the priority associated with a logic circuit while current leakage of the stored-charge is of priority for memory circuits. Therefore, multi-level interconnect schemes using five to six levels of metal are essential for logic ICs in order to offer improved speed, while memory circuits may need only two to three levels.
In order for the IC to be useful, the IC must have physical connections to the outside world. Two extremes in IC development support different types of interfaces to external devices. Low cost packaging which supports low pin count is achieved with traditional wire bond attached chips. High cost packaging may support high pin count in the case of flip chips. With wire bond attached chips I/O cells are placed at the edge of the die. Bond wire pads placed at the edge of the die outside I/O circuitry further increase the die size. 100051 Advances in device density within the core have made it possible to reduce core size of IC devices. However, reduced I/O pad-pitch (the pitch is typically defined as the repeat distance between adjacent I/O pads) has been hard to achieve because of packaging limitations. Therefore, as a result, IC designs that are I/O intensive tend to have a die size significantly greater than that of the core. This leads to poor utilization of the silicon area. Alternatively flip chip designs may be used for the I/O intensive applications.
Flip chip microelectronic assemblies contain direct electrical connections of face-down electronic components onto sub-straights or circuit boards by means of conductive bumps on IC bond pads. Thus, geometry allows more devices to be incorporated into a single IC. Flip chips offer advantages in size, performance, flexibility, reliability, and cost over other packaging methods. For example eliminating packages and bond wires greatly reduces the required board area by up to 95 percent and also requires far less height. Additionally, flip chips offer improved performance over other assembly methods as eliminating bond wires reduces the latency and capacitance associated with bond wires by significantly shortening the circuit path. This may result in high-speed off chip inner connects. The final metal layer of most IC bond pads is aluminum which provides a satisfactory surface for conventional wire bonding. However, this surface may be inhospitable to most conductive bumps as aluminum forms an oxide immediately upon exposure to air. The formation of wire bond scrubs the insulting oxide to weld with the underlying metal. Bumps on the other hand need an alternative strategy for making reliable electrical connections. Because aluminum is not a readily wettable surface, it may corrode over time if not protected from the environment. The bump on the bond pads typically requires an under-bump metallization (UBM) be placed on the chip bond pad in order to replace. Consequently, successful placement of a flip chip bump requires the removal of the oxidized aluminum surface and placement of a more hospitable material such as an under-bump metallization (UBM). Under-bump metallization generally requires multiple layers of different metals or conductive materials that form an adhesion layer, diffusion barrier layer, and an oxidation barrier layer. This addition of another metal layer typically requires an additional deposition and patterning process. Additional passivation layers may also be required.
Embodiments of the present invention are directed to systems and methods that are further described in the following description and claims. Advantages and features of embodiments of the present invention may become apparent from the description, accompanying drawings and claims.
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numerals indicate like features and wherein:
Preferred embodiments of the present invention are illustrated in the FIGURES, like numerals being used to refer to like and corresponding parts of the various drawings.
The present invention provides a process end flow for a flip chip device that simplifies the end process flow for flip chip devices when compared to existing processes. This process flow, beginning with the deposition of a final metal layer for the IC, also includes the deposition of the UBM layer on top of the metal layer and then the simultaneous patterning of the UBM layer and IC final metal layer, wherein the IC final metal layer is patterned with and automatically aligned to the UBM layer patterning. Such a process flow may eliminate the need for second passivation deposition and patterning, and individually patterning the final metal layer and UBM layer. Removing these steps has the potential to simplify processing, reduce defects and increase yield.
Flip Chip devices utilize direct interconnections in which the IC is mounted upside down onto a modular or printed circuit board. Electrical connections are made via solder bumps or solderless materials such as epoxies or conductive adhesives located over the surfaces of the chip. Since the bumps can be located anywhere on the chip, front chip bonding ensures that the interconnect distance between the chip and package is minimized. The IO density is limited only by the minimum distance between adjacent bond pads.
A typical end process flow for a flip chip device is illustrated in the process flow diagram provided in
The bumping sites on the bond pads of the IC are then prepared for bump. This preparation may include cleaning, removing insulating oxides, and providing a pad metallurgy that will protect the IC while making a good mechanical and electrical connection to the solder bump.
On top of the prepared IC, a UBM layer, which may constitute a stack of metals or conductive materials, is deposited in step 38. The UBM may overlap and protect exposed final metal layer circuitry from corrosion. UBM generally consists of successive layers of metal with functions described by their-names. The “adhesion layer” must adhere well to the bond pad metal (final metal layer) and the surrounding passivation, providing a strong, low-stress mechanical and electrical connection. The “diffusion barrier” layer limits the diffusion of solder into the underlying material. The “solder wettable.” layer offers a wettable surface to the molten solder during assembly, for good bonding of the solder to the underlying metal. A “protective layer” may be required to prevent oxidation of the underlying layer. This UBM layer is patterned in step 40.
Bump material will be deposited in step 42. Although eutectic Sn/Pb and high Pb alloys are the most prevalent bump materials used today, several new alloys are being introduced to the market that include Pb-free systems. Bumps may be formed or placed on the UBM in many ways, including evaporation, electroplating, printing, jetting, stud bumping, and direct. placement. The results of these methods may differ in bump size and spacing (“pitch”), solder components and composition, cost, manufacturing time, equipment required, assembly temperature, and UBM. The bump material is patterned in step 44. In order to form the eutectic solder bump, a reflow process may be performed in step 46.
By selecting a proper etch process able to selectively etch both the UBM layer and the final metal layer, these materials may be etched and patterned in a single step. Such processing eliminates the potential for misalignment by automatically aligning the UBM to final metal layer. This allows the process of individually patterning the final metal layer, as well as depositing and patterning a second passivation layer to be eliminated.
The etch process may be a dry etching method used to achieve high fidelity pattern transfers. This etch may rely on selectivity to avoid significantly etching dielectric layers beneath the removed metal layers. Alternatively, the etch process may rely on accurate end point detection to stop the etching process.
In summary, embodiments of the present invention provide a process end flow for a flip chip device that simplifies the end process flow for flip chip devices. This process flow, beginning with the deposition of a final metal layer for the IC. The deposition of the UBM layer follows on top of the metal layer. Then, the simultaneous patterning of the UBM layer and IC final metal layer is contemplated, wherein the IC final metal layer is patterned with and automatically aligned to the UBM layer patterning. Such a process flow may eliminate the need for a second passivation deposition and patterning and the process of individually patterning the final metal layer.
Simplifying the process flow by removing steps may increase processing throughput, decrease processing time and potentially result in improved yields. These improved yields may arise from decreased defectivity. Additionally, by etching the UBM and final metal layer together, potential alignment errors are eliminated.
As one of average skill in the art will appreciate, the term “substantially” or “approximately”, as may be used herein, provides an industry-accepted tolerance to its corresponding term. Such an industry-accepted tolerance ranges from less than one percent to twenty percent and corresponds to, but is not limited to, component values, integrated circuit process variations, temperature variations, rise and fall times, and/or thermal noise. As one of average skill in the art will further appreciate, the term “operably coupled”, as may be used herein, includes direct coupling and indirect coupling via another component, element, circuit, or module where, for indirect coupling, the intervening component, element, circuit, or module does not modify the information of a signal but may adjust its current level, voltage level, and/or power level. As one of average skill in the art will also appreciate, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two elements in the same manner as “operably coupled”. As one of average skill in the art will further appreciate, the term “compares favorably”, as may be used herein, indicates that a comparison between two or more elements, items, signals, etc., provides a desired relationship. For example, when the desired relationship is that signal 1 has a greater magnitude than signal 2, a favorable comparison may be achieved when the magnitude of signal 1 is greater than that of signal 2 or when the magnitude of signal 2 is less than that of signal 1.
Although the present invention is described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as described by the appended claims.