Claims
- 1. A central processing unit on a semiconductor substrate, comprising:
- an instruction queue of 32-bit length and fetching two instructions, each of 16-bit fixed length, from an instruction memory in a single instruction fetch operation, wherein each instruction of 16-bit fixed length has an operation code field whose contents define an operation of the subject instruction;
- a decoder coupled to the instruction queue and decoding one instruction selected from the two instructions in the instruction queue, and generating control signals based on a decoding result of the selected instruction; and
- an execution unit coupled to receive the control signals from the decoder and executing an operation based on the control signals.
- 2. A central processing unit according to claim 1, further comprising:
- a data bus of 32-bit width coupled to the instruction queue, the data bus transmitting the two instructions of 16-bit fixed length to the instruction queue from the instruction memory in the single instruction fetch operation.
- 3. A central processing unit according to claim 2, further comprising:
- a multiplexer coupled to the instruction queue and selectively providing one of the two instructions of 16-bit fixed length in the instruction queue to the decoder.
- 4. A central processing unit according to claim 3, wherein the execution unit comprises:
- general purpose registers, each of 32-bit length;
- a program counter of 32-bit length; and
- an arithmetic logic unit.
- 5. A central processing unit according to claim 3, further comprising:
- an instruction register coupled between the multiplexer and the decoder to latch the selected instruction provided from the multiplexer.
- 6. A CPU on a semiconductor substrate, comprising:
- a data bus of 32-bit width;
- an instruction fetch block including:
- an instruction buffer coupled to the data bus and being capable of fetching two instructions, each of 16-bit fixed length, from an instruction memory via the data bus in a single instruction fetch operation, wherein each instruction of 16-bit fixed length has an operation code field whose contents define an operation thereof; and
- a multiplexer coupled to the instruction buffer and selectively providing one of the two instructions fetched in the instruction buffer;
- a decoder coupled to receive the one instruction, the decoder generating control signals based on a decoding result of the one instruction; and
- an execution unit coupled to receive the control signals from the decoder and executing an operation based on the control signals.
- 7. A central processing unit according to claim 6, wherein the execution unit comprises:
- general purpose registers, each of 32-bit length;
- a program counter of 32-bit length, which stores an address to be fetched; and
- an arithmetic logic unit.
- 8. A central processing unit according to claim 6, wherein the instruction fetch block further comprises:
- an instruction register, coupled between the multiplexer and the decoder, latching the one instruction provided from the multiplexer.
Priority Claims (2)
Number |
Date |
Country |
Kind |
3-178739 |
Jun 1991 |
JPX |
|
4-154525 |
May 1992 |
JPX |
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Parent Case Info
This application is a continuation application of application U.S. Ser. No. 08/898,994, filed Jul. 23, 1997; which was a continuation application of U.S. Ser. No. 08/478,730, filed Jun. 7, 1995; which was a continuation application of U.S. Ser. No. 07/897,457, filed Jun. 10, 1992, now abandoned.
US Referenced Citations (12)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0368332A2 |
May 1990 |
EPX |
0427245A3 |
May 1991 |
EPX |
0472025A2 |
Feb 1992 |
EPX |
Non-Patent Literature Citations (5)
Entry |
Taka, D., RISC Systems, 1990, pp. 49-71. |
"i860 microprocessor internal architecture" Microprocessors and Microsystems, V. 14, No. 12, Mar. 1990, pp. 89-96. |
"Cache Organization to Maximize Fetch Bandwidth," IBM Technical Disclosure Bulletin, V.32, No. 2, Jul. 1989, pp. 62-64. |
M68000, 16/32-Bit Microprogrammers's Reference Manual, 1984, pp. 72, 77, 80. |
Osborne, 16-bit Microprocessor Handbook, 1971, pp. 7-30 to 7-38. |
Continuations (3)
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Number |
Date |
Country |
Parent |
898994 |
Jul 1997 |
|
Parent |
478730 |
Jun 1995 |
|
Parent |
897457 |
Jun 1992 |
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