Patent Application
20230036590
The present application claims priority from Japanese application JP 2021-126744, filed on Aug. 2, 2021, the contents of which is hereby incorporated by reference into this application.
The present invention relates to a charged particle beam scanning module, a charged particle beam device, and a computer.
A charged particle beam device is a device that acquires information about a sample by irradiating the sample with charged particles and detecting secondary electrons. The charged particle beam device includes a charged particle beam scanning module for scanning the sample with a charged particle beam.
In the charged particle beam scanning module, a digital signal from a scanning controller is converted into an analog signal by a digital-to-analog conversion circuit (DAC circuit), and a charged particle beam is deflected in accordance with the analog signal and is radiated to a desired position of the sample.
An error may occur at the time of converting the digital signal in the DAC circuit. This error includes an integral non-linearity error (hereinafter referred to as an “INL error”). The INL error occurs due to, for example, a temporal change, a temperature change, and other environmental changes. The INL error influences linearity of a relationship between a time and an irradiation position during scanning a sample with the charged particle beam, and the INL error appears as, for example, a change (expansion and contraction or the like) in a dimension on an image. Therefore, a measurement error of the dimension may be different depending on a position of the sample, and uniformity in the image may be impaired.
As a technique for correcting an irradiation error of a charged particle beam, for example, JP-A-2004-87483 (Patent Literature 1) discloses a configuration for correcting deflection of a charged particle beam using an interferometer.
A configuration shown in
The ADC circuit converts an analog signal into a digital signal and feeds back the digital signal to a scanning controller. The scanning controller corrects an error of the digital signal based on a difference between the digital signal output to the DAC circuit and the digital signal input from the ADC circuit.
The technique in the related art has a problem in that it is difficult to correct the INL error in the DAC circuit in real time.
For example, the configuration disclosed in Patent Literature 1 corrects the deflection of the charged particle beam as a result, but does not correct the INL error of the DAC circuit.
In the configuration shown in
In order to solve such problems, an object of the present invention is to provide a charged particle beam scanning module, a charged particle beam device, and a computer that can correct an INL error in a DAC circuit in real time.
An example of a charged particle beam scanning module according to the present invention includes
a scanning controller configured to output a scanning digital signal of a charged particle beam,
a DAC circuit configured to convert the scanning digital signal into a scanning analog signal and output the scanning analog signal, and
an ADC circuit configured to convert the scanning analog signal into an evaluation digital signal.
A sampling frequency at which the DAC circuit samples the scanning digital signal is a first frequency,
a sampling frequency at which the ADC circuit samples the scanning analog signal is a second frequency smaller than the first frequency, and
the scanning controller determines an output characteristic of the DAC circuit by evaluating the scanning digital signal and the evaluation digital signal.
An example of a charged particle beam device according to the present invention includes a charged particle beam scanning module.
The charged particle beam scanning module includes
A sampling frequency at which the DAC circuit samples the scanning digital signal is a first frequency,
a sampling frequency at which the ADC circuit samples the scanning analog signal is a second frequency smaller than the first frequency, and
the scanning controller determines an output characteristic of the DAC circuit by evaluating the scanning digital signal and the evaluation digital signal.
The charged particle beam device further includes
a charged particle source configured to generate the charged particle beam,
a detector configured to detect secondary electrons generated in response to irradiation on a sample using the charged particle beam, and
a sample image generation device configured to generate a sample image based on the detected secondary electrons.
An example of a computer according to the present invention can communicate with a charged particle beam device.
The charged particle beam device includes a charged particle beam scanning module.
The charged particle beam scanning module includes
A sampling frequency at which the DAC circuit samples the scanning digital signal is a first frequency,
a sampling frequency at which the ADC circuit samples the scanning analog signal is a second frequency smaller than the first frequency, and
the scanning controller determines an output characteristic of the DAC circuit by evaluating the scanning digital signal and the evaluation digital signal.
The charged particle beam device further includes
The computer includes a storage medium configured to store information, and a processor.
The processor receives the sample image and information indicating the output characteristic from the charged particle beam device.
According to the technique of the present invention, an INL error in the DAC circuit can be corrected in real time.
Embodiments of the present invention will be described below with reference to accompanying drawings.
Although a horizontal axis of the graph represents time, it can also be considered that the horizontal axis represents an input of a DAC circuit. A vertical axis represents an output of the DAC circuit. The output of the DAC circuit increases with time in first scanning along an axis direction (for example, the X axis direction). An ideal output 12 is indicated by a broken line. The ideal output 12 matches an input, that is, a digital signal from a scanning controller, and the ideal output 12 linearly increases. Although the digital signal is actually a fine step-shaped signal, the digital signal is shown as a signal of a straight line in
An actual output 13 of the DAC circuit is represented by a solid line in the graph, and includes an INL error. For example, when measuring the dimension L1, it is ideal that an output of the DAC circuit changes by Δvi(1), but the output of the DAC circuit actually changes by Δvr(1) due to an error. In general, Δvi(1)≠Δvr(1). Similarly, when measuring the dimension L2, an ideal variation is Δvi(1), but an actual variation is Δvr(2). In general, Δvi(2)≠Δvr(2). These errors appear as deflection errors of the charged particle beam and influence the measurement of the dimension L1.
An electron source 101 (a charged particle source) generates an electron beam 103 (a charged particle beam). The electron beam 103 is extracted by an extraction electrode 102, is accelerated by an acceleration electrode (not shown), is condensed by a condenser lens 104 which is one form of a focusing lens, and then is one-dimensionally or two-dimensionally scanned on the sample 10 by a deflector 105. The electron beam 103 is decelerated by a negative voltage applied to an electrode incorporated in a sample stage 108, is focused by a lens action of an objective lens 106, and is radiated onto the sample 10.
When the sample 10 is irradiated with the electron beam 103, electrons 110 such as secondary electrons and backscattered electrons are emitted from an irradiated portion. The emitted electrons 110 are accelerated in a direction of the electron source 101 by an acceleration action based on the negative voltage applied to the sample, collide with a conversion electrode 112, and generate secondary electrons 111. The secondary electrons 111 emitted from the conversion electrode 112 are captured by a detector 113. In this manner, the detector 113 detects the secondary electrons generated in response to the irradiation on the sample 10 using the electron beam 103. An output of the detector 113 changes in accordance with an amount of the secondary electrons captured by the detector 113. Luminance of a display device (not shown) changes in accordance with the output. For example, in the case of forming a two-dimensional image, a deflection signal to the deflector 105 and the output of the detector 113 are synchronized to form an image of a scanning region.
The charged particle beam device 100 shown in
Although
A control device 120 is configured with, for example, a computer, and includes a processor 121 and a memory 122. The memory 122 is a storage medium that stores information. The storage medium may be configured with, for example, a main memory, a flash memory, a hard disk drive (HDD), a magnetoresistive memory (MRAM), or the like. The memory 122 may store a program, and the processor 121 may execute the program so that the control device 120 implements functions and functional units described in the present embodiment.
The control device 120 has, for example, the following functions:
The control device 120 includes an SEM control device that mainly controls an optical condition of the SEM and a signal processing device that performs a signal processing on a detection signal obtained by the detector 113. The control device 120 includes a charged particle beam scanning module (which will be described later with reference to
A computer 130 is connected to the charged particle beam device 100. The computer 130 includes a processor 131 and a memory 132, and can communicate with the charged particle beam device 100. The memory 132 is a storage medium that stores information. The storage medium may be configured with, for example, a main memory, a flash memory, a hard disk drive (HDD), a magnetoresistive memory (MRAM), or the like. The memory 132 may store a program, and the processor 131 may execute the program so that the computer 130 implements functions and functional units described in the present embodiment.
The deflector of an electric field type and the deflector of a magnetic field type may be used in combination. Further, a specific configuration of the deflector is not limited to the above-described configuration, and for example, any known configuration may be used.
The scanning controller 201 is configured with, for example, a computer, and includes a processor 201a and a memory 201b. The memory 201b is a storage medium that stores information. The storage medium may be configured with, for example, a main memory, a flash memory, a hard disk drive (HDD), a magnetoresistive memory (MRAM), or the like. The memory 201b may store a program, and the processor 201a may execute the program so that the scanning controller 201 implements functions and functional units described in the present embodiment.
The scanning controller 201 generates and outputs a scanning digital signal D1 of a charged particle beam. The scanning digital signal D1 is a beam control signal, and represents a deflection amount of the charged particle beam in a specific axis direction (for example, the X axis direction or the Y axis direction), that is, corresponds to an irradiation position. The scanning digital signal D1 has accuracy of, for example, 26 bits.
The DAC circuit 202 receives the scanning digital signal D1, converts the scanning digital signal D1 into a scanning analog signal A1, and outputs the scanning analog signal A1. The DAC circuit 202 is, for example, a DAC circuit of ultra-high accuracy, and is capable of coping with accuracy of 26 bits. As a more specific example, upper 14 bits and lower 12 bits of the 26 bits may be converted into analog signals, and results may be added to output a final scanning analog signal A1. The scanning analog signal A1 includes an INL error of the DAC circuit 202 as described above.
The amplifier circuit 203 amplifies the scanning analog signal A1 to generate an amplified scanning analog signal (hereinafter referred to as an “amplified analog signal A2”), and supplies the amplified analog signal A2 to the deflector 105. That is, the scanning analog signal A1 is amplified by the amplifier circuit 203 and then is supplied to the deflector 105 of the charged particle beam. The amplified analog signal A2 is represented by, for example, a voltage or a current.
The deflector 105 deflects a charged particle beam based on the amplified analog signal A2 from the amplifier circuit 203.
The VGA circuit 205 is a variable gain amplifier circuit, adjusts the scanning analog signal A1 in accordance with a dynamic range of the ADC circuit 207, and outputs an adjusted scanning analog signal (hereinafter referred to as an “adjusted analog signal A3”).
The sampling circuit 206 is, for example, a sample and hold circuit. The sampling circuit 206 holds the adjusted analog signal A3 at a predetermined sampling time, and outputs a held scanning analog signal (hereinafter referred to as a “held analog signal A4”) to the ADC circuit 207. That is, the sampling circuit 206 continues to output the held analog signal A4 corresponding to the adjusted analog signal A3 at a time point designated by a hold instruction signal output from the timing device 208 while maintaining the held analog signal A4 at the same value for a predetermined time.
The scanning analog signal A1, the amplified analog signal A2, the adjusted analog signal A3, and the held analog signal A4 are all scanning analog signals, and are signals of the same quality in that the signals include an INL error.
The ADC circuit 207 converts the held analog signal A4 into an evaluation digital signal D2. The evaluation digital signal D2 is substantially a signal in which an INL error is added to the scanning digital signal D1, and can be used for evaluation of the INL error. As a specific example, the INL error can be evaluated based on a difference between the scanning digital signal D1 and the evaluation digital signal D2. The ADC circuit 207 has accuracy corresponding to the accuracy of the DAC circuit 202. The ADC circuit 207 is, for example, an ADC circuit of ultra-high accuracy, and is capable of coping with accuracy of 26 bits.
The timing device 208 supplies a timing signal such that the scanning controller 201, the DAC circuit 202, the sampling circuit 206, the ADC circuit 207, and the like appropriately operate in synchronization with one another.
A sampling cycle T1 represents a cycle in which the DAC circuit 202 samples the scanning digital signal D1. A sampling frequency (a first frequency) is proportional to a reciprocal of the sampling cycle T1, and for example, when the sampling cycle T1 is a [sec], the sampling frequency is 1/a [Hz].
The sampling cycle T1 may be, for example, a time defined as a time during which an input signal needs to be maintained constant in the specification of the DAC circuit 202. Alternatively, the sampling cycle T1 may be a time during which an input value for the DAC circuit 202 is actually maintained constant.
A sampling cycle T2 represents a cycle in which the ADC circuit 207 samples the held analog signal A4. A sampling frequency (a second frequency) is proportional to a reciprocal of the sampling cycle T2, and for example, when the sampling cycle T2 is b [sec], the sampling frequency is 1/b [Hz].
The sampling cycle T2 may be, for example, a time defined as a time during which an input signal needs to be maintained constant in the specification of the ADC circuit 207. Alternatively, the sampling cycle T2 may be a time during which an input value for the ADC circuit 207 is actually maintained constant.
The sampling circuit 206 receives the adjusted analog signal A3 and the hold instruction signal output from the timing device 208 at the same cycle as the sampling cycle T2, that is, at the second frequency, and continues to output the held analog signal A4 corresponding thereto. As described above, since a scanning analog signal to be converted by the ADC circuit 207 is the held analog signal A4 output from the sampling circuit 206, a value of the signal is maintained for at least a time required for a conversion operation of the ADC circuit 207.
The sampling cycle T2 of the ADC circuit 207 is longer than the sampling cycle T1 of the DAC circuit 202. That is, the second frequency is smaller than the first frequency. In general, a conversion operation of the ADC circuit 207 takes a longer time than a conversion operation of the DAC circuit 202. As described above, the second frequency is designed to be smaller than the first frequency, so that a time required for the conversion operation of the ADC circuit 207 can be ensured.
(1) to (6) in
Although the sampling cycle T2 is shorter than the repetition cycle TX in the example shown in
The charged particle beam scanning module 200 according to the present embodiment can scan a sample with a charged particle beam and generate the evaluation digital signal D2 in parallel. Here, as shown in
In the example shown in
Since the sampling cycle T2 is different from the repetition cycle TX and is different from, for example, an integer multiple of the repetition cycle TX and an integer fraction of the repetition cycle TX, the initial sampling times (1), (3), and (5) in respective repetition cycles TX respectively correspond to different values of the scanning digital signal D1. Similarly, the second time sampling times (2), (4), and (6) in respective repetition cycles TX respectively correspond to different values of the scanning digital signal D1. A difference among the sampling times in
As described above, since the scanning controller 201 generates the scanning digital signal D1 which is repeated at the third frequency (corresponding to the repetition cycle TX) different from the second frequency (corresponding to the sampling cycle T2), it is possible to perform sampling at a higher frequency (at a substantial shorter interval I1) in accordance with a difference between the third frequency and the second frequency.
Here, it can be said that a relationship between the scanning digital signal D1 and the scanning analog signal A1 represents an output characteristic of the DAC circuit 202. For example, when a value at a time (1) in
In this manner, the scanning controller 201 can determine the output characteristic of the DAC circuit 202 based on the scanning digital signal D1 and the scanning analog signal A1 (more strictly, based on the evaluation digital signal D2 corresponding to the scanning analog signal A1). That is, the scanning controller 201 can determine the output characteristic of the DAC circuit 202 by evaluating the scanning digital signal D1 and the evaluation digital signal D2.
For example, an expression format of information indicating the output characteristic can be designed freely, and the information may be expressed as a table in which a value of the scanning digital signal D1 and a value of the scanning analog signal A1 or the evaluation digital signal D2 are associated with each other. Alternatively, for example, the information may be expressed as a table in which the value of the scanning digital signal D1 and a difference between the scanning digital signal D1 and the evaluation digital signal D2 are associated with each other.
Since one measurement cycle of one output characteristic, that is, a cycle required to measure all values corresponding to times (1) to (6) shown in
The determined output characteristic of the DAC circuit 202 can be used to correct an INL error in the DAC circuit 202. In the present embodiment, the scanning controller 201 corrects an output of the DAC circuit 202 based on the output characteristic of the DAC circuit 202.
Next, for example, a charged particle beam for imaging is used to perform scanning as a normal measurement operation (step S2). This scanning is performed using the corrected scanning analog signal A1. For example, the scanning controller 201 determines a correction value for correcting the scanning analog signal A1 based on the output characteristic (a first output characteristic) acquired before step S2, and corrects the scanning analog signal A1 in accordance with the correction value.
As a specific method of implementing the correction, for example, the DAC circuit 202 may adjust and output the scanning analog signal A1 in accordance with an instruction from the scanning controller 201, or an appropriate circuit (not shown) for correcting the scanning analog signal A1 output from the DAC circuit 202 may be separately provided.
The output characteristic of the DAC circuit 202 is measured in parallel with the normal measurement operation (step S2), that is, in real time (step S3). That is, the INL error is measured, and a measurement result is stored in the memory 201b. In other words, the scanning controller 201 causes the ADC circuit 207 to output the corrected scanning analog signal A1 in parallel with the determination of the output characteristic of the DAC circuit 202.
In parallel with the operations, the scanning controller 201 determines the INL error (step S4). For example, it is determined whether a difference (a varying range) between the corrected INL error and an INL error in a newly measured output characteristic (a second output characteristic) is larger than a predetermined threshold. That is, a difference between the above-described first output characteristic and the second output characteristic determined after the first output characteristic is calculated, and it is determined whether the difference is larger than a predetermined threshold.
A method of calculating the varying range can be appropriately designed by a person skilled in the art. For example, the varying range can be expressed using an absolute value of a difference between the scanning digital signal D1 and the evaluation digital signal D2 or using a square of the difference.
When it is determined in step S4 that the difference is larger than the predetermined threshold, the scanning controller 201 updates the correction value (step S5). For example, a correction value is newly calculated based on the newly measured output characteristic (the second output characteristic), the correction value is updated according to the newly calculated correction value, and an image acquired thereafter is corrected based on the updated new correction value. The new correction value serves as a comparison reference when step S4 is performed subsequently. A specific method of using the correction value can be appropriately designed by a person skilled in the art, and can be, for example, a method to be described in second to fourth embodiments which will be described later.
When it is determined in step S4 that the varying range does not exceed the threshold, step S5 is not performed.
Step S4 can be performed, for example, at a predetermined interval. This interval can be set within a range of, for example, 1 second to 10 seconds. Alternatively, step S4 can be performed each time a measurement position or an imaging position changes.
According to such an operation, a correction value of the INL error in the DAC circuit 202 can be updated at an appropriate timing using the output characteristic of the DAC circuit 202 acquired in real time. Accordingly, for example, an appropriate correction can be performed in accordance with both an INL error (which varies in a unit of several seconds) depending on temperature and a temporal change (which varies in a unit of several days) of the DAC circuit 202.
As described above, according to the charged particle beam scanning module and the charged particle beam device of the first embodiment, since the output characteristic of the DAC circuit 202 can be determined in parallel with the scanning using the charged particle beam, the INL error in the DAC circuit 202 can be corrected in real time. As a result, it is possible to achieve both highly accurate scanning using the charged particle beam and high throughput of imaging.
The second embodiment is different from the first embodiment in that the correction of the INL error is performed based on a sample image. Hereinafter, description of portions common to those of the first embodiment may be omitted.
In the second embodiment, the scanning controller 201 transmits a captured sample image and information indicating the output characteristic to the computer 130 (
The processor 131 acquires a measured length value by measuring a dimension of a pattern (length measurement target pattern) appearing in a specific part of the sample image based on the received sample image. Thereafter, the processor 131 corrects the measured length value based on the output characteristic of the DAC circuit 202.
For example, the output characteristic has the contents shown in
L(n)com=A×L(n)m×Δvr(n)/Δvi(n)
A is an adjustment coefficient and represents an optical condition or the like. Δvr(n) represents an actual deflection voltage amount in the n-th pattern, that is, represents an amount of a voltage changed when a charged particle beam is deflected from one end of the pattern to the other end of the pattern. Δvi(n) represents an ideal deflection voltage amount (or an expected deflection voltage amount) in the n-th pattern, that is, represents an amount of a voltage to be originally changed when a charged particle beam is deflected from one end of the pattern to the other end of the pattern.
In the present embodiment, it can be said that the output characteristic of the DAC circuit 202 represents a relationship between Δvr(n) and Δvi(n) at a position corresponding to each pattern. A value of vr(n) can be obtained with high accuracy by designing the equivalent interval I1 shown in
As described above, in the second embodiment, the charged particle beam scanning module 200 receives information about secondary electrons generated in response to irradiation on a sample using a charged particle beam, generates a sample image based on the information, and transmits the sample image to the computer 130. The processor 131 of the computer 130 receives the sample image, measures a dimension (a measured length value) of the sample based on the sample image, and corrects the measured length value based on the output characteristic of the DAC circuit 202. In this manner, a measurement based on the sample image and a correction based on the output characteristic can be combined to perform a measurement with high accuracy.
As described above, according to the second embodiment, it is possible to correct a variation in a length value measurement result of a pattern, that is, it is possible to correct expansion and contraction of a measured length value due to an INL error.
The correction in the second embodiment is not necessarily performed by the processor 131 or the computer 130, and may be performed by the charged particle beam scanning module 200 (for example, the scanning controller 201) or the charged particle beam device 100 (for example, the control device 120). In this case, the scanning controller 201 does not need to transmit the sample image and the information indicating the output characteristic to the computer 130.
The third embodiment is different from the second embodiment in that a correction is performed in a plurality of axis directions. Hereinafter, description of portions common to those of the first or the second embodiment may be omitted.
A method of acquiring the output characteristics in the two directions in parallel can be appropriately designed by a person skilled in the art based on the description of the first embodiment, a known technique, and the like. For example, scanning in the X direction is performed at a certain Y position, and then scanning in the X direction is performed at a next Y position obtained by moving the Y position by a certain unit. By repeating this operation and scanning the Y position from a minimum value to a maximum value, the output characteristic in the Y direction can be acquired in parallel with the output characteristic in the X direction.
For example, for a vector representing a pixel position, an accurate position 402 may be measured as a position 401 including an error due to an influence of an INL error.
Similar to the second embodiment, the processor 131 of the computer 130 receives information about secondary electrons generated in response to irradiation on a sample using a charged particle beam, stores the information in the memory 132, and generates a sample image based on the information.
The processor 131 receives information indicating the output characteristics of the DAC circuit 202. For example, the output characteristic is determined for each of the X direction and the Y direction, and the information indicating the output characteristics includes information indicating the output characteristic in the X direction and information indicating the output characteristic in the Y direction. The processor 131 corrects the sample image based on an output characteristic. For example, a luminance or a pixel position in the X direction is corrected based on the output characteristic in the X direction, and a luminance or a pixel position in the Y direction is corrected based on the output characteristic in the Y direction.
A specific calculation processing for a correction can be appropriately designed by a person skilled in the art, and an example of such a calculation processing will be described as follows. A distance xr in the X direction and a distance yr in the Y direction from a predetermined reference point (for example, an origin in the image) to the position 401 (xr, yr) including an error are corrected in the same manner as that in the second embodiment, and the accurate position 402 (xi, yi) is calculated as a corrected position. Then, a luminance value of a pixel at the accurate position 402 (xi, yi) is matched with a luminance value measured at the position 401 (xr, yr) including the error. Such a processing is repeated for all measurement positions (or all pixel positions). An appropriate interpolation processing may be performed. In this manner, the sample image is corrected.
The processor 131 outputs the corrected sample image. For example, as an output form, the corrected sample image output from the processor 131 may be stored in the memory 132, may be displayed on a display device (not shown), or may be transmitted to another computer via a communication network.
According to such a correction, for example, in a case where a rectangular pattern of the sample 10 is imaged in a manner of being inclined as in an actually measured shape 403, it is possible to two-dimensionally correct the inclination and acquire an accurate sample image.
The correction in the third embodiment is not necessarily performed by the processor 131 or the computer 130, and may be performed by the charged particle beam scanning module 200 (for example, the scanning controller 201) or the charged particle beam device 100 (for example, the control device 120). In this case, the scanning controller 201 does not need to transmit the sample image and the information indicating the output characteristics to the computer 130.
The fourth embodiment is different from the second embodiment in that a correction is performed in a plurality of axis directions and a sample image and positional deviation information are output. Hereinafter, description of portions common to any one of the first to third embodiments may be omitted.
Similar to the second and the third embodiments, the processor 131 of the computer 130 receives information about secondary electrons generated in response to irradiation on a sample using a charged particle beam, stores the information in the memory 132, and generates a sample image based on the information. Then, the processor 131 generates positional deviation information in the X direction and positional deviation information in the Y direction at a predetermined position (for example, all pixel positions) of the sample image based on the output characteristic in the X direction and the output characteristic in the Y direction.
In
The processor 131 outputs the positional deviation information in the X direction and the positional deviation information in the Y direction. The processor 131 outputs a sample image (that is, a sample image before a correction). For example, as an output form, the sample image output from the processor 131 may be stored in the memory 132, may be displayed on a display device (not shown), or may be transmitted to another computer via a communication network.
In this manner, the positional deviation information can be used in any form and the degree of freedom is increased, by outputting the sample image and the positional deviation information as a set (that is, in combination). For example, a user who has acquired the sample image and the positional deviation information may measure a length based on the sample image and correct a length measurement result based on the positional deviation information as in the first embodiment, or may correct the sample image and measure a length based on the corrected sample image as in the third embodiment.
The correction in the fourth embodiment is not necessarily performed by the processor 131 or the computer 130, and may be performed by the charged particle beam scanning module 200 (for example, the scanning controller 201) or the charged particle beam device 100 (for example, the control device 120). In this case, the scanning controller 201 does not need to transmit the sample image and the information indicating the output characteristics to the computer 130.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-126744 | Aug 2021 | JP | national |
