CHIP PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME

Abstract

A chip packaging structure and a method for fabricating the same are provided. The chip package structure includes a first chip, a second chip, a conductive substrate, a dielectric layer, a vertical conductive structure, a dam and a metal shielding layer. The conductive substrate includes a substrate, vias and electrodes. The vias penetrate through the substrate, and a part of the vias is disposed in a first die-bonding region and a second die-bonding region. The electrodes extend from the first board surface to the second board surface through the vias. The dielectric layer is formed on the substrate to cover a lower electrode portion of each of the electrodes. The vertical conductive structure is formed to be partially embedded into the dielectric layer and provide an electrical path between the first and second die-bonding regions. The dam is formed to surround the first and the second die-bonding regions.

Description

FIELD OF THE DISCLOSURE

The present disclosure relates to a chip package structure and a method for fabricating the same, and more particularly to a chip package structure and a method for fabricating the same that integrate processes of three-dimensional printing and substrate metallization.

BACKGROUND OF THE DISCLOSURE

In the existing package structure, molded cavities are often used to make adjustments for various product specifications. However, in order to form cavities with different specifications, different molds need to be provided in the molding process, which is expensive and time consuming.

In addition, lots of complex processes may be involved before the production of the cavities is complete, including application of dry film or wet photoresist, lithography, electroplating, sputtering or vapor deposition of metal layers, etching of metal wires, and the like, steps of which are not only complicated, but also difficult to perform. Furthermore, limitations on the aspect ratio and issues relating to structural integrity also need to be considered to avoid collapsing of the cavity when the package structure is encapsulated with adhesives.

Therefore, improving the structure and process of the package structure has become one of the important issues to be addressed in the art.

SUMMARY OF THE DISCLOSURE

In response to the above-referenced technical inadequacies, the present disclosure provides a chip package structure that integrates three-dimensional printing and substrate metallization processes and a method for fabricating the same.

In one aspect, the present disclosure provides a method for fabricating a chip package structure, and the method includes: providing a conductive substrate, in which the conductive substrate includes a substrate having a first board surface and a second board surface opposite to each other, a plurality of vias penetrating through the first board surface and the second board surface, in which at least a part of the plurality of vias is disposed in a first die-bonding region for arranging a chip, and a plurality of electrodes extending from the first board surface to the second board surface through the plurality of vias, in which each of the plurality of electrodes includes an upper electrode portion and a lower electrode portion, the upper electrode part covers the first board surface, and the lower electrode partially covers the second board surface; performing a first deposition process to deposit a first metal seed layer on the first board surface and the plurality of electrodes; performing a first lithography process to cover a first photoresist layer on the first seed layer, such that the first photoresist layer overlaps with the first die-bonding region; performing a first etching process to remove a to-be-etched portion of the first metal seed layer that is not covered by the first photoresist layer; performing a three-dimensional (3D) printing-molding process to form at least one dam surrounding the first die-bonding region with a 3D printing material on the first board surface, in which the at least one dam has a height higher than a height of the chip; performing a second deposition process to deposit and cover a metal shielding layer on the first plate surface, the at least one dam and the first photoresist layer; performing a photoresist removal process to remove the first photoresist layer and a portion of the metal shielding layer that overlaps with the first photoresist layer; and performing a second etching process to remove the first metal seed layer to form the chip package structure.

In another aspect, the present disclosure provides a chip package structure, which includes a conductive substrate, at least one dam and a metal shielding layer. The conductive substrate includes a substrate, a plurality of vias and a plurality of electrodes. The substrate has a first board surface and a second board surface opposite to each other. The plurality of vias penetrate through the first board surface and the second board surface, and at least a part of the plurality of vias is disposed in a first die-bonding region for arranging a chip. The plurality of electrodes extend from the first board surface to the second board surface through the plurality of vias, each of the plurality of electrodes includes an upper electrode portion and a lower electrode portion, the upper electrode part covers the first board surface, and the lower electrode partially covers the second board surface. The at least one dam is formed to surround the first die-bonding region and formed on the first board surface, and the at least one dam has a height higher than a height of the chip.

In yet another aspect, the present disclosure provides a chip package structure, which includes a first chip, a second chip, a conductive substrate, a dielectric layer, a vertical conductive structure, at least one dam, and a metal shielding layer. The conductive substrate includes a substrate, a plurality of vias, and a plurality of electrodes. The substrate has a first board surface and a second board surface opposite to each other. The plurality of vias penetrate through the first board surface and the second board surface, in which at least a part of the plurality of vias is disposed in a first die-bonding region of the substrate on which the first chip is to be arranged and a second die-bonding region of the substrate on which the second chip is to be arranged. The plurality of electrodes extend from the first board surface to the second board surface through the plurality of vias, in which each of the plurality of electrodes includes an upper electrode portion and a lower electrode portion, the upper electrode part covers the first board surface, and the lower electrode portion partially covers the second board surface. The dielectric layer is formed on the second board surface to cover the lower electrode portion of each of the electrodes. The vertical conductive structure is formed to be partially embedded into the dielectric layer and provide an electrical path between the first die-bonding region and the second die-bonding region. At least one dam is formed to surround the first die-bonding region and formed on the first board surface, in which the at least one dam has a height higher than a height of the first chip and the second chip. The metal shielding layer covers the at least one dam and a part of the first board surface that do not overlap with the plurality of electrodes.

These and other aspects of the present disclosure will become apparent from the following description of the embodiment taken in conjunction with the following drawings and their captions, although variations and modifications therein may be affected without departing from the spirit and scope of the novel concepts of the disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The described embodiments may be better understood by reference to the following description and the accompanying drawings, in which:

FIG. 1 is a flowchart of a method for fabricating a chip package structure according to a first embodiment of the present disclosure;

FIG. 2 is a flowchart showing steps for forming a conductive substrate according to the first embodiment of the present disclosure;

FIG. 3 is a schematic diagram of the conductive substrate according to the first embodiment of the present disclosure;

FIG. 4 is a schematic diagram showing a process of step S101 according to the first embodiment of the present disclosure;

FIG. 5 is a schematic diagram showing processes of steps S102 and S103 according to the first embodiment of the present disclosure;

FIG. 6 is a schematic diagram showing a process of step S104 according to the first embodiment of the present disclosure;

FIG. 7 is a schematic diagram showing processes of steps S11 and S12 according to the first embodiment of the present disclosure;

FIG. 8 is a schematic diagram of the process of step S13 according to the first embodiment of the present disclosure;

FIG. 9 is a schematic diagram showing a process of step S14 according to the first embodiment of the present disclosure;

FIG. 10 is a flowchart showing steps for forming a dam according to the first embodiment of the present disclosure;

FIGS. 11A to 11D are schematic views of various cross-sections of the dam according to the first embodiment of the present disclosure;

FIG. 12 is a schematic diagram showing a process of step S15 according to the first embodiment of the present disclosure;

FIG. 13 is a schematic diagram showing a process of step S16 according to the first embodiment of the present disclosure;

FIG. 14 is a schematic diagram showing a process of step S17 according to the first embodiment of the present disclosure;

FIG. 15 is a schematic diagram showing steps S18 and S19 according to the first embodiment of the present disclosure;

FIG. 16 is a partial flowchart of a method for fabricating a chip package structure according to a second embodiment of the present disclosure;

FIG. 17 is a schematic diagram showing a conductive substrate covered with a first metal seed layer according to the second embodiment of the present disclosure;

FIG. 18 is a schematic diagram showing a process of step S110 according to the second embodiment of the present disclosure;

FIG. 19 is a schematic diagram of processes of steps S111 and S112 according to the second embodiment of the present disclosure;

FIG. 20 is a schematic diagram showing a process after steps S12 to S17 are performed according to the second embodiment of the present disclosure;

FIG. 21 is a schematic diagram of a chip package structure according to a third embodiment of the present disclosure; and

FIG. 22 is a schematic diagram of a chip package structure according to a fourth embodiment of the present disclosure.

FIG. 23 is a schematic diagram of a chip package structure according to a fifth embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

The present disclosure is more particularly described in the following examples that are intended as illustrative only since numerous modifications and variations therein will be apparent to those skilled in the art. Like numbers in the drawings indicate like components throughout the views. As used in the description herein and throughout the claims that follow, unless the context clearly dictates otherwise, the meaning of “a”, “an”, and “the” includes plural reference, and the meaning of “in” includes “in” and “on”. Titles or subtitles can be used herein for the convenience of a reader, which shall have no influence on the scope of the present disclosure.

The terms used herein generally have their ordinary meanings in the art. In the case of conflict, the present document, including any definitions given herein, will prevail. The same thing can be expressed in more than one way. Alternative language and synonyms can be used for any term(s) discussed herein, and no special significance is to be placed upon whether a term is elaborated or discussed herein. A recital of one or more synonyms does not exclude the use of other synonyms. The use of examples anywhere in this specification including examples of any terms is illustrative only, and in no way limits the scope and meaning of the present disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given herein. Numbering terms such as “first”, “second” or “third” can be used to describe various components, signals or the like, which are for distinguishing one component/signal from another one only, and are not intended to, nor should be construed to impose any substantive limitations on the components, signals or the like.

First Embodiment

FIG. 1 is a flowchart of a method for fabricating a chip package structure according to a first embodiment of the present disclosure. FIG. 2 is a flowchart showing steps for forming a conductive substrate according to the first embodiment of the present disclosure.

Reference is made to FIG. 1, one aspect of the present disclosure is to provide a method for fabricating a chip package structure, and the method includes the following steps:

Step S10: providing a conductive substrate.

FIG. 3 is a schematic diagram of the conductive substrate according to the first embodiment of the present disclosure. Referring to FIG. 3, the conductive substrate 100 includes a substrate 1, a plurality of vias 2 and a plurality of electrodes 3. The substrate 1 can be, for example, a ceramic substrate made of aluminum oxide or aluminum nitride, and has a first board surface 11 and a second board surface 12 opposite to each other. The plurality of vias 2 penetrate through the first board surface 11 and the second board surface 12, and at least a part of the plurality of vias 2 is disposed in a first die-bonding region 111 for arranging a chip.

The plurality of electrodes 3 are extended from the first board surface 11 to the second board surface 12 through the plurality of vias 2, respectively. Each of the plurality of electrodes 3 includes an upper electrode portion 31 and a lower electrode portion 32, the upper electrode portion 31 covers a portion of the first board surface 11, and the lower electrode part 32 covers a portion of the second board surface 12.

Before performing step S10, the following steps for forming the conductive substrate 100 are first described. However, in the present disclosure, it is not limited to fabricate the conductive substrate in this way.

Reference is made to FIG. 2, the manufacturing method provided by the present disclosure can include the following steps for forming the conductive substrate 100:

Step S100: providing a substrate.

Step S101: performing a third deposition process to deposit a second metal seed layer on the first board surface and the second board surface, and on inner surfaces of the plurality of vias. Reference is made to FIG. 4, which is a schematic diagram showing a process of step S101 according to the first embodiment of the present disclosure. As shown in FIG. 4, the vias 2 can be formed on the (ceramic) substrate 1 by using a laser drilling process, and the third deposition process can be, for example, vacuum evaporation, ion plating, or sputtering process, so as to deposit a second metal seed layer 4 on surfaces of the substrate 1 and on the inner surfaces 21 of the vias 2. The second metal seed layer 4 can be, for example, a conductive metal seed layer, such as a copper seed layer, which can be used to provide a suitable conductive layer in subsequent electroplating processes. It should be noted that the so-called third deposition process refers to being separated from first and second deposition processes described hereinafter, and is not intent to limit a sequence of the processes to be performed with.

Step S102: performing a second lithography process to dispose a second photoresist layer and a third photoresist layer on the first board surface and the second board surface, respectively, so as to define a plurality of to-be-plated portions.

Step S103: performing a first electroplating process to dispose a first conductive metal layer on the plurality of to-be-plated portions.

FIG. 5 is a schematic diagram showing processes of steps S102 and S103 according to the first embodiment of the present disclosure. As shown in FIG. 5, the above steps are used to metallize the substrate 1 to form electrodes for the chip formed in subsequent steps. Therefore, in step S102, a photoresist layer can be exposed and developed to carve geometric pattern structures on the photoresist layer, so as to form a photoresist layer 51 and a photoresist layer 52 as shown in FIG. 5.

It should be noted that the photoresist layer 51 is disposed on the first board surface 11 to define a to-be-plated portion 511 where the upper electrode portions 31 of the electrodes 3 are to be formed, and the photoresist layer 52 is disposed on the second board surface 12 to define a to-be-plated portion 521 where the lower electrode portions 32 of the electrodes 3 are to be formed. The electroplating process is then performed to form a conductive metal layer 6 on the surfaces of the substrate 1 and the inner surfaces 21 of the vias 2 on which the second metal seed layer 4 has been formed. It should be noted that the first conductive metal layer 6 is made of a conductive metal material that is the same as that of the second metal seed layer 4, so there is no obvious layered structure. However, the above is merely an example, and is not meant to limit the scope of the present disclosure. In other words, the first conductive metal layer 6 can also use a conductive metal material different from that of the second metal seed layer 4.

Step S104: removing the second photoresist layer, the third photoresist layer, and a portion of the first metal seed layer that is covered by the second photoresist layer and the third photoresist layer, so as to form a plurality of initial electrodes.

FIG. 6 is a schematic diagram showing a process of step S104 according to the first embodiment of the present disclosure. As shown in FIG. 6, the photoresist layers 51, 52 and the first metal seed layer 4 in FIG. 5 can be removed by etching and photoresist removal processes to form portions covered by the photoresist layers 51, 52, so as to form initial electrodes 3′ in FIG. 6. It should be noted that the initial electrodes 3′ are formed by the first conductive metal layer 6 and the second metal seed layer 4.

Step S105: performing an electroless plating process to dispose a second conductive metal layer on portions of the plurality of initial electrodes that are exposed on the first board surface, so as to form the plurality of electrodes and the conductive substrate including the plurality of electrodes. It should be noted that the so-called electroless plating is also called the chemical plating, which is a surface treatment process for depositing alloys on a surface of a substrate body using an autocatalytic reaction, which is different from the electroplating process mentioned in the above step S103.

Reference is made to FIG. 3 again, the second conductive metal layer 7 can be formed on a portion of the initial electrode 3′ that is exposed and covers the first board surface 11. Therefore, the second conductive metal layer 7 and the initial electrodes 3′ exposed on the first board surface 11 can collectively form the upper electrode portions 31 of the electrodes 3. It should be noted that the second conductive metal layer 7 can include a first metal layer on a surface of the initial electrode 3′ and a second metal layer on the first metal layer, and the first and second metal layers can be a metal composite layer composed of nickel/gold in sequence. The gold layer can be used to prevent an oxidation of the nickel layer to improve durability of the electrode 3. In one embodiment of the present disclosure, a preferred thickness of the first metal layer is 5 μm, and a preferred thickness of the second metal layer is 0.025 μm.

Reference is made to FIG. 1 again, the method proceeds to step S11: performing a first deposition process to deposit a first metal seed layer on the first board surface and the plurality of electrodes.

FIG. 7 is a schematic diagram showing processes of steps S11 and S12 according to the first embodiment of the present disclosure. As shown in FIG. 7, similar to the third deposition process, the first deposition process can be performed to deposit a first metal seed layer 8 on the first surface 11 of the (ceramic) substrate 1 and the electrodes by, for example, vacuum evaporation, ion plating, or sputtering process. The first metal seed layer 8 can be, for example, a conductive metal seed layer, such as a copper seed layer, which can be used to provide proper protection for the electrodes 3 in subsequent processes.

Step S12: performing a first lithography process to cover a first photoresist layer on the first seed layer, such that the first photoresist layer overlap with the first die-bonding region.

As shown in FIG. 7, in step S12, a photoresist layer can be first exposed and developed to carve a geometric figure structure on the photoresist layer to form the photoresist layer 53 shown in FIG. 7. The photoresist layer 53 is disposed on the first board surface 11, and is also formed for the purpose of protecting the electrodes 3 in the subsequent processes.

Step S13: performing a first etching process to remove a to-be-etched portion of the first metal seed layer that is not covered by the first photoresist layer.

Reference is made to FIG. 8, which is a schematic diagram of the process of step S13 according to the first embodiment of the present disclosure. As shown in FIG. 8, in step S13, a to-be-etched portion 81 of the first metal seed layer 8 that is not covered by the photoresist layer 53 can be removed, so as to expose a portion of the first board surface 11 to serve as a reserved area for a dam formed in subsequent steps.

Step S14: performing a three-dimensional (3D) printing-molding process to form at least one dam surrounding the first die-bonding region with a 3D printing material on the first board surface. In detail, in order to form a cavity for packaging, a dam 6 is formed to surround the first die-bonding region 111 and has a height higher than that of a chip to be disposed in the first die-bonding region 111.

It should be noted that the 3D printing process in this step includes a 3D printing process and a light curing process. The 3D printing process utilizes a printing principle similar to that of an inkjet printer. A photosensitive resin or silicone material is sprayed on a printing area through a nozzle, and then irradiated and pre-cured by ultraviolet (UV) light. In this way, 3D printed material layers are stacked and shaped repeatedly, and are finally heat-cured to enhance structural reliability. Due to the smooth and delicate surface of the finished product, light curing technology is suitable for making high-precision and complex objects, so it is suitable for packaging technology.

Reference is made to FIGS. 9 and 10, FIG. 9 is a schematic diagram showing a process of step S14 according to the first embodiment of the present disclosure, and FIG. 10 is a flowchart showing steps for forming a dam according to the first embodiment of the present disclosure.

As shown in FIG. 10, a dam 9 can include a plurality of printing layers 91, 92, . . . , 9n, and the step of performing the 3D printing-molding process to form the dam 9 further includes the following steps:

Step S140: performing a printing step to print the 3D printing material in a printing area with a nozzle of a 3D printing device, so as to form one of the plurality of printing layers.

Step S141: performing a curing step to cure the printed printing layer by irradiation with a light source.

Next, the printing step S140 and the curing step S141 are repeatedly performed to form the pre-shaped dam 9.

Step S142: in response to a predetermined number of layers being reached, heating and curing the pre-shaped dam.

For example, as shown in FIG. 9, the printing layer 91 can be formed first by using the nozzle of the 3D printing equipment, the printing layer 91 is pre-cured by irradiating the printing layer 91 with the UV light source, and then the same steps are performed for the printing layer 92 until a desired dam structure is achieved. For example, after the printing layer 9n is formed as the last layer, the overall pre-shaped dam 9 is heated and cured. It should be noted that, from a top view, each of the printing layers 91, 92, . . . , 9n is formed to surround the first die-bonding region 111 at a center of the first board surface 11. Therefore, by using a layer-by-layer stacking method, compared with the dispensing method used in the existing packaging technology, not only the collapse issues can be avoided, but also a cross-sectional shape of the dam 9 can be precisely controlled to make it closer to a target shape.

It is worth noting that a distance between the dam 9 and the first die-bonding region 111 only needs to be kept at least 100 μm, so as to prevent the 3D printing material used during the 3D printing process from being sprayed into the first die-bonding region 111. That is, a distance between the first die-bonding region 111 and a vertical projection of the dam 9 projected onto the first board surface 11 is at least greater than 100 μm. In addition, when the substrate 1 is made of materials such as AlN or Al₂O₃, under the same exposure energy, since AlN or Al₂O₃ has high reflectivity, a dam structure with higher strength can be achieved.

Reference is made to FIGS. 11A to 11D, FIGS. 11A to 11D are schematic views of various cross-sections of the dam according to the first embodiment of the present disclosure. In this embodiment, the dam 9 can have a cross-section formed by a combination of one or more of a rectangle, a triangle, a half circle, a half ellipse, and a trapezoid. For example, as shown in FIG. 11A, the cross-section of the dam 9 is an isosceles trapezoid, and the trapezoid is basically composed of a rectangle and a triangle; as shown in FIG. 11B, the cross-section of the dam 9 combines an isosceles trapezoid combined with a rectangle; as shown in FIG. 11C, the cross-section of the dam 9 combines an isosceles trapezoid with a semicircle; and as shown in FIG. 11D, the cross-section of the dam 9 is composed of two rectangles with different sizes. Therefore, it is conceivable that the dam 9 can be provided with a multi-layer stepped and inclined surface design, and thus the dam 9 is suitable for glass packaging. The dam 9 can also be applied to the substrate 1 of different materials, such as glass substrate or silicon wafer, so it can be applied to CMOS image sensor (CIS) packages.

On the other hand, since 3D printing technology and light curing technology are integrated in this embodiment to manufacture the dam 9, compared to an injection molding technology using liquid crystal polymer, the layer-by-layer stacking method can be utilized to achieve more arbitrary patterns and to exceed a limitation of aspect ratio of the existing process (which cannot reach 10, for example). Therefore, the method of the present disclosure provides better flexibility in designing the package structure, while providing numerous functionalities for components in the cavity. In one preferred embodiment of the present disclosure, the height of the dam body 9 can be within a range from 50 to 1000 μm.

In addition, in FIG. 9, the dams 9 on both sides of the first die-bonding region 111 can be integrally formed, or can be a plurality of dams formed by integrating multiple 3D printing and light curing processes, and the number of the dams 9 or the number of processes used to form the dams 9 are not limited in the present disclosure.

Reference is made to FIG. 1 again, the method proceeds to step S15: performing a second deposition process to deposit and cover a metal shielding layer on the first plate surface, the at least one dam and the first photoresist layer.

Reference is made to FIG. 12, and FIG. 12 is a schematic diagram showing a process of step S15 according to the first embodiment of the present disclosure. As shown in FIG. 12, the second deposition process can be performed to deposit a metal shielding layer 10 on the first board surface 11, the dam 9 and the photoresist layer 53 by, for example, vacuum evaporation, ion plating, or sputtering process. In the embodiment where the chip to be packaged is a light emitting diode chip or other light emitting device, a material with high reflectivity can be selected to form the metal shielding layer 10 to improve an overall light emitting efficiency of the light emitting device. For example, a material such as silver, aluminum, gold, titanium/aluminum composite metal, nickel-gold composite metal combined with silver or nickel-palladium-gold composite metal combined with silver can be used to form the metal shielding layer 10, and the metal shielding layer 10 made of such material can be provided with reflectance more than 90% in wavelengths such as ultraviolet (200-400 nm), ultraviolet A (320-400 nm), ultraviolet B (280-320 nm), ultraviolet C (200-280 nm) and infrared (700-1000 nm).

On the other hand, when the metal shielding layer 10 is formed on the dam 9, which can be provided with anti-ultraviolet capability by utilizing the high reflectance of the metal shielding layer 10, so as to protect the dam 9 and improve its durability. Furthermore, the formed metal shielding layer 10 can enhance heat resistance and chemical resistance of the dam 9 when the dam 9 made of epoxy resin is subjected to high temperature processes applied to the chip. The metal shielding layer 10 also provides an airtight capability to address issues such as cracks and outgassing.

Step S16: performing a photoresist removal process to remove the first photoresist layer and a portion of the metal shielding layer that overlaps with the first photoresist layer.

Reference is made to FIG. 13, which is a schematic diagram showing a process of step S16 according to the first embodiment of the present disclosure. As shown in FIG. 13, the photoresist layer 53 can be removed together with a portion of the metal shielding layer 10 that covers the photoresist layer 53.

Step S17: performing a second etching process to remove the first metal seed layer to form the chip package structure.

Reference is made to FIG. 14, which is a schematic diagram showing a process of step S17 according to the first embodiment of the present disclosure. In detail, as shown in FIG. 14, chemical etching can be used to remove the first metal seed layer 8 to expose the electrodes 3. Therefore, it can be seen that the first metal seed layer 8 can be used to protect the electrodes 3 during the processes in which the dam 9 and the metal shielding layer 10 are formed. In this step, the metal shielding layer 10 can be further electrically insulated from the electrodes 3 in the first die-bonding region 111 to form the chip package structure 200.

Step S18: performing a die-bonding process to place a chip in the first die-bonding region, and electrical connect the chip with the electrodes in the first die-bonding region.

Step S19: performing a packaging process to dispose and fix a package cover to the metal shielding layer to form a chip package. The package cover CR, the dam 9 (covered with the metal shielding layer 10) and the conductive substrate 100 jointly define an enclosed space that surrounds the chip CP.

For example, reference can be made to FIG. 15, which is a schematic diagram showing steps S18 and S19 according to the first embodiment of the present disclosure. As shown in FIG. 15, the chip CP can be picked up and placed on the conductive substrate 100 by controlling a robot arm, and the chip CP can be electrically connected with the electrodes 3 (for example, by welding). After electrical connections are completed, the package cover CR is picked up by a robotic arm and bonded to the dam 9 covered with the metal shielding layer 10 to form the chip package 300. Since the method for encapsulating the chip CP and the package cover CR is known to those skilled in the art, the description thereof will be omitted hereinafter. In this embodiment, a transparent cover (e.g., a glass substrate) can be used as the package cover CR, but this embodiment is not limited thereto.

It should be noted that an inner surface 901 of the dam 9 facing the chip CP is inclined at a predetermined angle A1 relative to the conductive substrate 100, such that the metal shielding layer 10 on the inner surface 901 is also inclined relative to the conductive substrate 100 at the predetermined angle A1, therefore in a case that the chip CP is the light emitting diode chip, the emitting efficiency can be improved.

Second Embodiment

FIG. 16 is a partial flowchart of a method for fabricating a chip package structure according to a second embodiment of the present disclosure, and FIG. 17 is a schematic diagram showing a conductive substrate covered with a first metal seed layer according to the second embodiment of the present disclosure. As shown in FIGS. 16 and 17, the conductive substrate 100′ of this embodiment can include a plurality of electrodes 3″, some of which are disposed in the first die-bonding region 111 and some of which are disposed outside the first die-bonding region 111. It should be noted that, in this embodiment, the details of the processes used are basically similar to those of the first embodiment, so repeated descriptions will be omitted hereinafter, and only differences from the first embodiment are emphasized.

As shown in FIG. 16, the method for fabricating the chip package structure further includes performing the following steps before performing step S12 of the first lithography process, that is, after the first metal seed layer 8 is deposited on the conductive substrate 100′:

Step S110: performing a third lithography process to cover a fourth photoresist layer on the first metal seed layer while only exposing a plurality of wire regions not above the electrodes in the first die-bonding region.

FIG. 18 is a schematic diagram showing a process of step S110 according to the second embodiment of the present disclosure. As shown in FIG. 18, it should be noted that a wire region 82 can further provide additional electrical paths in the subsequently formed dam to the electrodes 3″ that are not used for the chip (i.e., outside the first die-bonding region 111). For the above purpose, the first metal seed layer 8 is exposed in the wire region 82 to reserve a suitable conductive layer for the subsequent electroplating process used to form required circuits.

Step S111: performing a second electroplating process to form a third conductive metal layer on the first metal seed layer and the fourth photoresist layer, and in the plurality of wire regions.

Step S112: removing the fourth photoresist layer and a portion of the third conductive metal layer that covers the fourth photoresist layer, so as to form a plurality of vertical wire structures on the electrodes that are not in the first die-bonding region.

FIG. 19 is a schematic diagram of processes of steps S111 and S112 according to the second embodiment of the present disclosure. After steps S111 and S112, a structure shown in FIG. 19 is formed. A plurality of vertical wire structures 84 are formed on the electrodes 3″ that are not in the first die-bonding region 111. It should be noted that the third conductive metal layer that forms the vertical wire structures 84 can be made of the same or different conductive metal material as the first metal seed layer 8, and the present disclosure is not limited thereto.

FIG. 20 is a schematic diagram showing a process after steps S12 to S17 are performed according to the second embodiment of the present disclosure. After step S112 is performed, the method for fabricating the chip package structure returns to steps S12 to S17 in FIG. 1, and a structure shown in FIG. 20 is formed. In this embodiment, when the dam 9 is formed on the electrodes 3″ having the vertical wire structures 84, the dam 9 can directly cover the vertical wire structures 84 completely, and then a brushing process is performed before the dam 9 is cured to remove a portion of the dam 9 that covers the vertical wire structures 84, so as to expose a portion (e.g., a top) of the vertical wire structure 84, such that when the metal shielding layer 10 is formed in the second deposition process of step S15, it can be electrically connected with the corresponding vertical wire structure 84. Therefore, the chip package structure and the method for fabricating the same provided by the present embodiment can also realize vertically integrated packaging and shorten conductive paths provided by the wires.

Third Embodiment

Reference is made to FIG. 21, which is a schematic diagram of a chip package structure according to a third embodiment of the present disclosure. As shown in FIG. 21, the first board surface 11 includes a first die-bonding region 111, a second die-bonding region 112 and a third die-bonding region 113, chips CP1, CP2 and CP3 are disposed in the first die-bonding region 111, the second die-bonding region 112 and the third die-bonding region 113, respectively. The conductive substrate 100 further includes a circuit layer 13 disposed on the first board surface 11, and the circuit layer 13 includes a first circuit portion 131 and a second circuit portion 132.

It should be noted that, in the present embodiment, the dam 9 is different from the chip packaging structures of the first embodiment and the second embodiment in terms of application requirements. Therefore, a metal shielding layer may not be formed on the surface of the dam 9.

The first circuit portion 131 is used to provide a plurality of first conductive paths between the second die-bonding region 112 and the electrodes 3 in the first die-bonding region 111, for example, conductive paths between the electrodes 3 and a plurality of electrical contacts C1 of the chip CP2. On the other hand, the second circuit portion 132 can be used to provide a plurality of second conductive paths to the third die-bonding region 113, such as conductive paths for a plurality of electrical contacts C2 of the chip CP3. A part of the dam 9 can be disposed on the first circuit portion 131, and another part of the dam 9 can be used as an insulating layer between the first circuit portion 131 and the second circuit portion 132.

Therefore, in this embodiment, the dam 9 on the first circuit portion 131 can be in direct contact with an adhesive material AD, and since the dam 9 and the package cover body can be bonded by the adhesive material AD, a bonding force between the dam 9 and the package cover can be enhanced in subsequent steps for forming the package cover (such as the package cover CR of FIG. 15).

Fourth Embodiment

Reference is made to FIG. 22, which is a schematic diagram of a chip package structure according to a fourth embodiment of the present disclosure. As shown in FIG. 22, the first board surface 11 includes a first die-bonding region 111 and a fourth die-bonding region 114, and the conductive substrate 100 further includes a circuit layer 13 disposed on the first board surface 11. Chips CP1 and CP4 are disposed in the first die-bonding region 111 and the fourth die-bonding region 114, respectively, and the circuit layer 13 includes a third circuit portion 133. It should be noted that, in the present embodiment, the dam 9 is different from the chip packaging structures of the first embodiment and the second embodiment in terms of application requirements. Therefore, a metal shielding layer 10 can only be formed on the surface of the dam 9.

In this embodiment, the third circuit portion 133 is used to provide a plurality of third conductive paths between the electrodes (e.g., electrical contacts C3) in the fourth die-bonding region 114 and the electrodes 3 under the dam 9. In addition, the package cover CR further includes a bridging conductive layer M1 that is in contact with the metal shielding layer, for electrically connecting the metal shielding layer 10 on a part of the dam 9 (for example, a top surface of the dam 9 on the left) with the metal shielding layer 10 on another part (e.g., the top surface of the dam 9 on the right side).

Therefore, in this embodiment, a vertical transmission path for the circuits and a horizontal transmission path bypassing the chip CP1 can be achieved, and the circuit layer 13 under the dam 9 can be protected by insulating properties of the dam 9.

Fifth Embodiment

Reference is made to FIG. 23, which is a schematic diagram of a chip package structure according to a fifth embodiment of the present disclosure. As shown in FIG. 23, the fifth embodiment of the present disclosure provides a chip package structure 400, which includes chips CP1, CP2 and CP3, a conductive substrate 41, a dielectric layer 42, a plurality of dams D1 to D4, a conductive metal layer 44, a metal shielding layer 46 and vertical conductive structures VC1 and VC2.

The conductive substrate 41 includes a substrate 410, a plurality of vias V1 to V6 and electrodes E1 to E6.

The substrate 410 has a first board surface S1 and a second board surface S2 opposite to each other. The vias V1 to V6 penetrating through the first board surface S1 and the second board surface S2. The vias V1 and V2 are disposed in a first die-bonding region DB1 on which the chip CP1 is to be arranged, the vias V3 and V2 are disposed in a second die-bonding region DB2 on which the chip CP2 is to be arranged, and the vias V5 and V6 are disposed in a third die-bonding region DB3 on which the chip CP3 is to be arranged.

In the present embodiment, the substrate 410 can be made of materials such as AlN or Al2O3, so as to achieve the dams D1 to D4 with higher strength as mentioned above.

The electrodes E1 to E6 extend from the first board surface S1 to the second board surface S2 through the vias V1 to V6, respectively, and each of the electrodes E1 to E6 can be formed by steps S100 to S105 mentioned in FIG. 2.

Furthermore, the conductive metal layer 44 can be formed on a portion of each of the electrodes E1 to E6 that is exposed and covers the first board surface S1, and the conductive metal layer 44 can be a metal composite layer composed of nickel/gold in sequence. The gold layer can be used to prevent an oxidation of the nickel layer to improve durability of the electrodes E1 to E6.

Specifically, each of the electrodes E1 to E6 has an upper electrode portion and a lower electrode portion. Taking the electrode E1 as an example, the upper electrode portion partially covers the first board surface S1, and the lower electrode portion partially covers the second board surface S2.

Moreover, the dielectric layer 42 is formed on the second board surface S2 to cover the lower electrode portion of each of the electrodes E1 to E6, and can be made of non-conductive materials for electrical insulation.

The vertical conductive structure VC1 can be further formed to be partially embedded into the dielectric layer 42, thereby providing an electrical path between the first die-bonding region DB1 and the second die-bonding region DB2. Similarly, the vertical conductive structure VC2 can be further formed to be partially embedded into the dielectric layer 42, thereby providing an electrical path between the second die-bonding region DB2 and the third die-bonding region DB3.

More specifically, vias V7 to V10 can be provided in the dielectric layer 42. The via V7, V8, V9 and V10 are formed to correspond to the electrodes E1, E3, E4 and E6, respectively, and penetrate through a lower surface of the dielectric layer 42, thereby exposing a part of the lower electrode portion of each of the electrode E1, E3, E4 and E6.

The vertical conductive structure VC1 can include metal conductors mc1 and mc2 respectively formed in the vias V7 and V8, and a metal sheet mt1 formed on the lower surface of the dielectric layer 42. The metal sheet mt1 is used to electrically connect the metal conductor mc1 with the metal conductor mc2, thereby establishing the electrical path between the first die-bonding region DB1 and the second die-bonding region DB2.

Similarly, the vertical conductive structure VC2 can include metal conductors mc3 and mc4 respectively formed in the vias V9 and V10, and a metal sheet mt2 formed on the lower surface of the dielectric layer 42. The metal sheet mt2 is used to electrically connect the metal conductor mc3 with the metal conductor mc4, thereby establishing the electrical path between the second die-bonding region DB2 and the second die-bonding region DB3.

It should be noted that the metal sheets mt1 and mt2 and the metal conductor mc1 to mc4 can be made of the same or different conductive metal material as the electrodes E1 to E6, such as such as copper, silver, aluminum, gold, titanium/aluminum composite metal, nickel-gold composite metal combined with silver or nickel-palladium-gold composite metal combined with silver, and the present disclosure is not limited thereto.

Moreover, the dams D1 to D4 are formed on the first board surface S1, in which the dams D1 and D2 are formed to surround the first die-bonding region DB1, the dams D2 and D3 are formed to surround the second die-bonding region DB2, and the dams D3 and D4 are formed to surround the third die-bonding region DB3.

It should be noted that the dams D1 and D2 can be integrally formed in one piece, so as to serve as an enclosed square dam that surrounds the first die-bonding region DB1 when viewed from the top of the chip package structure 400. Similarly, the dams D2 and D3 can be integrally formed in one piece, and the dams D3 and D4 can be integrally formed in one piece, and even the dams D1 to D4 can be integrally formed in one piece, the present disclosure is not limited thereto. Specifically, the dams D1 to D4 have a height higher than heights of the chip CP1, CP2 and CP3.

In some embodiments, the dams D1 to D4 can each have a cross section formed by a combination of one or more of a rectangle, a triangle, a half circle, a half ellipse, and a trapezoid. For example, inner side surfaces of the dams D1 and D2 facing the first chip CP1 or inner side surfaces of the dams D3 and D4 facing the second chip CP2 are inclined at a predetermined angle relative to the conductive substrate 41, such that the metal shielding layer 46 on the inner side surfaces can be also inclined relative to the conductive substrate 46 at the predetermined angle.

The metal shielding layer 46 covers the dams D1 to D4, and the metal shielding layer 46 can enhance heat resistance and chemical resistance of the dams D1 to D4 when the dams D1 to D4 made of epoxy resin are subjected to high temperature processes applied to the chips CP1, CP2 and CP3. The chips CP1, CP2 and CP3 can be light emitting diode chips. Therefore, the metal shielding layer 46 can be made of a material with high reflectance, so as to enhance light-emitting efficiency of the chips CP1, CP2, and CP3.

Although the metal shielding layer 46 is only formed on surfaces of the dams D1 to D4, in some embodiments, the metal shielding layer 46 can further covers a part of the first board surface S1 that does not overlap with the electrodes E1 to E6, and the present disclosure is not limited thereto.

Although not shown in FIG. 23, a package cover (e.g., a transparent cover) can be provided as mentioned in the previous embodiment, which can be disposed and fixed on the metal shielding layer 46, thereby forming the package cover, the dams D1 to D4 and the conductive substrate 41 jointly define enclosed spaces respectively surrounding the first chip CP1 and the second chip CP2.

Therefore, by utilizing the vertical conductive structures VC1 and VC2, series connections among the chips CP1, CP2 and CP3 can be vertically implemented, which increases a density of LED chips within a limited area. Therefore, for a light source with multiple LED chips, a light divergence issue can be addressed to enable the light source to generate more concentrated lights, thereby improving the overall brightness. When the chip package structure 400 is utilized in a vehicle headlight, the overall effective power of an LED light source module can be further improved.

Beneficial Effects of the Embodiments

In conclusion, in the package structure and the method for fabricating the same provided by the present disclosure, the 3D printing technology and the light curing technology are integrated to manufacture the dam. Therefore, by using a layer-by-layer stacking method, compared with the dispensing method used in the existing packaging technology, not only the collapse issues can be avoided, but also a cross-sectional shape of the dam can be precisely controlled to make it closer to a target shape. On the other hand, compared to an injection molding technology using liquid crystal polymer, the layer-by-layer stacking method can be utilized to achieve more arbitrary patterns and to exceed a limitation of aspect ratio of the existing process. Therefore, the method of the present disclosure provides better flexibility in designing the package structure, while providing numerous functionalities for components in the cavity.

In addition, for the light-emitting diode chip, a material with high reflectivity can be used to form the metal shielding layer, so as to improve an overall emitting efficiency of the light-emitting device chip, and the metal shielding layer made of such material can be provided with light reflectance more than 90% in ultraviolet and infrared wavelengths. Furthermore, the dam can be provided with anti-ultraviolet capability by utilizing the high reflectance of the metal shielding layer, so as to protect the dam and improve its durability. Moreover, the formed metal shielding layer can enhance heat resistance and chemical resistance of the dam when the dam made of epoxy resin is subjected to high temperature processes applied to the chip. The metal shielding layer also provides an airtight capability to address issues such as cracks and outgassing.

Moreover, by utilizing vertical conductive structures, series connections among the chips can be vertically implemented, which increases a density of LED chips within a limited area. For a light source with multiple LED chips, a light divergence issue can be addressed to enable the light source to generate more concentrated lights, thereby improving the overall brightness. When the chip package structure provided by the present disclosure is utilized in a vehicle headlight, the overall effective power of an LED light source module can be further improved.

The foregoing description of the exemplary embodiments of the disclosure has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching.

The embodiments were chosen and described in order to explain the principles of the disclosure and their practical application so as to enable others skilled in the art to utilize the disclosure and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the present disclosure pertains without departing from its spirit and scope.

Claims

1. A chip package structure, comprising: a first chip and a second chip;a conductive substrate, including: a substrate having a first board surface and a second board surface opposite to each other;a plurality of vias penetrating through the first board surface and the second board surface, wherein at least a part of the plurality of vias is disposed in a first die-bonding region of the substrate on which the first chip is to be arranged and a second die-bonding region of the substrate on which the second chip is to be arranged; anda plurality of electrodes extending from the first board surface to the second board surface through the plurality of vias, wherein each of the plurality of electrodes includes an upper electrode portion and a lower electrode portion, the upper electrode part covers the first board surface, and the lower electrode portion partially covers the second board surface;a dielectric layer formed on the second board surface to cover the lower electrode portion of each of the electrodes;a vertical conductive structure formed to be partially embedded into the dielectric layer and provide an electrical path between the first die-bonding region and the second die-bonding region;at least one dam formed to surround the first die-bonding region and formed on the first board surface, wherein the at least one dam has a height higher than a height of the first chip and the second chip; anda metal shielding layer covers the at least one dam and a part of the first board surface that do not overlap with the plurality of electrodes.

2. The chip package structure according to claim 1, wherein a first via is formed in the dielectric layer to correspond to a first electrode of the plurality of electrodes in the first die-bonding region, and a second via is provided in the dielectric layer to correspond to a second electrode of the plurality of electrodes in the second die-bonding region.

3. The chip package structure according to claim 2, wherein the first via and the second via penetrate through a lower surface of the dielectric layer, there by exposing a part of the lower electrode portion of each of the first electrode and the second electrode.

4. The chip package structure according to claim 3, wherein the first vertical conductive structure includes: a first metal conductor and a second metal conductor formed in the first via and the second via, respectively; anda metal sheet formed on the lower surface of the dielectric layer to electrically connect the first metal conductor with the second metal conductor, so as to establish the electrical path between the first die-bonding region and the second die-bonding region.

5. The chip package structure according to claim 4, wherein the at least one dam includes a plurality of printing layers, and each of the printing layers is formed by performing a printing step and a curing step.

6. The chip package structure according to claim 4, wherein the at least one dam has a cross section formed by a combination of one or more of a rectangle, a triangle, a half circle, a half ellipse, and a trapezoid.

7. The chip package structure according to claim 4, wherein the height of the at least one dam is within a range from 50 to 1000 μm, and a distance between the first die-bonding region and a vertical projection of the at least one dam projected onto the first board surface is at least greater than 100 μm.

8. The chip package structure according to claim 4, wherein the first chip disposed in the first die-bonding region is electrically connected to the electrodes in the first die-bonding region, and the second chip disposed in the second die-bonding region is electrically connected to the electrodes in the second die-bonding region; and a package cover disposed and fixed on the metal shielding layer,wherein the package cover, the at least one dam and the conductive substrate jointly define a first enclosed space surrounding the first chip and a second enclosed space surrounding the second chip.

9. The chip package structure according to claim 8, wherein the first chip and the second chip are light-emitting diode chips.

10. The chip package structure according to claim 8, wherein an inner side surface of the at least one dam facing the first chip or the second chip is inclined at a predetermined angle relative to the conductive substrate, such that the metal shielding layer on the inner side surface is also inclined relative to the conductive substrate at the predetermined angle, and the package cover is a transparent cover.