The present invention relates generally to integrated circuit devices, and more particularly to test circuits for integrated circuit devices for characterizing transistors therein.
Integrated circuit devices can include circuit sections, such as memory circuits, that can be designed for high performance operations. Memory circuits, such as static random access memory (SRAMs) typically have a number of memory cells arranged into one or more arrays composed of multiple transistors. The performance characteristics and yield of the circuit sections in the integrated circuit can be affected by variations in the electrical characteristics of the transistors, such as threshold voltages, current drive, etc., and circuit characteristics, such as offset voltages.
While it is desirable to test transistor characteristics and circuit characteristics within memory cells and other circuit sections of the integrated circuit, data input/output (I/O) paths can introduce leakage currents that can make it very difficult to achieve high fidelity measurements.
Various embodiments will now be described in detail with reference to a number of drawings. The embodiments show integrated circuit device test circuits and methods that can reduce leakage currents in a data input/output (I/O) path and thereby enable accurate testing (including characterization) of circuit elements within the device.
In the various embodiments below, like items are referred to by the same reference character but the leading digits corresponding to the figure number.
Referring now to
In some embodiments, a section node 112 can be a node within a memory section of an integrated circuit device. For example, a section node 112 can include any of: a bit line or transistor gate, source, or drain within a selected memory cell. In addition or alternatively, a section node 112 can include nodes within circuits positioned between a memory cell array and input/outputs (I/Os) of a memory section. For example, a memory section node 112 can include any of: a sense amplifier circuit sense node, a transistor within a sense amplifier circuit, or switching circuits in an I/O path (e.g. column multiplexer, column select signals, etc.). It is noted that there can be intervening circuits between a section node 112 and a test element 102. It is also noted that while node 114 is referred to as an “output” node, it can serve to input data to a memory section in some embodiments.
A test element 102 can have two modes of operation, a standard mode and a low leakage cutoff mode.
The arrangement of
Referring back to
In contrast, test element 302-0 is in the low leakage cutoff mode. A voltage Vsig, which can be the same as, or substantially the same as Vtest, can be applied to intermediate node 308-0 through test switch 310-0. Consequently, there can be little or no leakage current (Ileak=0) flowing to output node 314 from test element 302-0 to interfere with current Imeas.
While FIGS. 1A/B and 3 have shown test elements with one first switch and one test switch, alternate embodiments can include multiple first switches per one test switch. One such embodiment is shown in
In
Output node 414 can be driven with a voltage that is the same, or substantially the same, as voltage Vtest at intermediate node 408-0.
Test elements according to embodiments shown herein can be formed with any circuit elements suitable for achieving desired reductions in leakage current at an output node. Some embodiments can form test elements with transistors appropriate to the manufacturing process. In particular embodiments, test elements can be formed with insulated gate field effect transistors (e.g., MOS transistors).
In
In one embodiment, signals SELECT/SELECTN can be boosted voltage signals in a test mode. For example, in a non-boosted mode, SELECT can be driven to a high power supply voltage (VDD) and SELECTN can be driven to a low power supply voltage (e.g., VSS). However, in a test mode of operation, signal SELECT can be driven to boosted voltage (e.g., VPP>VDD). In addition or alternatively, signal SELECTN can be driven to a boosted voltage (e.g., VBB<VSS). Such boosted signal levels can enable lower impedance when switches are conductive, and less leakage when switches are non-conductive, as compared to the non-boosted mode of operation.
It is understood that while
It is also noted that in an alternate embodiment, any of switches 504, 506, or 510 can be formed by one transistor, rather than as CMOS pass gates, which can receive boosted signals at its gate.
In designing IC devices, is desirable to utilize as little substrate area as possible to increase economies of scale and/or reduce signal routing lengths. Compact area implementations of test elements will now be described.
Referring now to
A first MUX layer 730-0 can include multiple test elements 702-0 to -m, each of which can take the form of any of the test elements shown herein, or equivalents. Each of test elements 702-0/1 can be coupled to an output node 714-0/1, which is coupled to, or which can be coupled to, test circuit 718.
A second MUX layer 730-1 can include a number of column MUXes 732-00 to 732-1n. Column MUXes can selectively couple bit lines (two shown as 734-0/1) of a memory section 746 to first MUX layer 730-0. In some embodiments, column MUXes (732-00 to -1n) can include test elements as described herein, or equivalents. However, in other embodiments, column MUXes (732-00 to -1n) can include conventional MUX circuits.
It is understood that first and second MUX layers (730-0 and 730-1) can enable signal paths in response to column select data, which can be generated from a memory address, or the like.
In the embodiment shown, a memory section 746 can include bit line pairs (one shown as 734-0/1) coupled to a number of memory cells (one shown as 736). Memory cells 736 can be coupled to a corresponding bit line pair 734-0/1 by operation of a word line 738 driven by a word line driver 740. In the particular embodiment shown, a memory cell 736 can be a six-transistor (6T) static random access memory (SRAM) cell, having two p-channel transistors P0/P1 cross-coupled between storage nodes 748-0/1, two n-channel transistors N2/N3 cross-coupled between storage nodes 748-0/1, and two access transistors N0/N1 that can couple storage nodes 748-0/1 to bit lines 734-0/1. Memory cells (e.g., 736) can be coupled between a high array power supply voltage node 744 and a low array power supply voltage node 742.
A word line driver 740 can drive a word line 738 between a high voltage VDDWL and a low voltage VSSWL. A voltage VDDWL can be substantially higher than a high array supply voltage VDDAR, and VSSWL can be substantially lower than VSSAR. A boosted low voltage VSSWL can force access transistors N0/N1 to very low leakage states. A boosted high voltage VDDWL can eliminate any voltage threshold drop across access transistors N0/N1, and place such transistors into very low impedance states to improve current/voltage readings in test operations.
A test circuit 718 can include a switch network 718-0, voltage sources 718-1, a current measuring circuit 718-2, and a sequencer 718-3. A switch network 718-0 can couple test output nodes 714-0/1 to various sections within test circuit 718. Voltage sources 718-1 can provide various test voltages for application to output nodes 714-0/1. Such test voltages can be constant voltages, variable voltages (e.g., a sweep over a range), or differential voltages for application between a pair of output nodes 714-0/1. A current measuring circuit 718-2 can measure a current flowing through an output node 714-0/1. A sequencer 718-3 can execute a test sequence by applying test voltages, and optionally control signals to the device 700. The sequencer 718-3 can also execute test sequences that include generating addresses for the memory section 746 that enable accesses to a selected cell in the memory section 746, and thereby enable the execution of test sequences and the application of test voltages to the selected cell.
In a standard mode of operation, all test elements 702-0 to -m can be placed in a standard mode of operation, enabling read and/or write paths to memory cells 736 via bit lines.
In a test mode of operation, two of test elements 702-0 to -m can be placed in a standard mode of operation, while remaining test elements can be placed in the low leakage cutoff mode. The two test elements in the standard mode can enable test circuit 718 to apply test conditions to memory section 746. Test conditions according to particular embodiments will be described in more detail below.
Referring now to
A column select layer 848 can include column select circuits 860-0 to -k that couple bit lines (e.g., 834-0/1) to MUX layers (830-0/1) based on column select values.
While embodiments can include various types of sense amplifiers, in the particular embodiment of
In an arrangement like that of
Embodiments of the invention can include memory sections having memory cells organized into banks. One such embodiment is shown in
A test column decoder 968 can enable and disable test elements within column MUXes (932-00 to -Mx) and/or bank selectors (902-0 to -M) to enable test modes of operation.
Accordingly, circuit elements within any of the banks can be tested as described herein, or equivalents.
A test circuit 1018 can apply test conditions to a memory array 1070 and derive test results from memory array 1070 through test elements 1002. In the embodiment shown, a test circuit 1018 can also control word line driver 1040 and substrate control circuit 1072. As noted above, a test circuit 1018 may, or may not, be part of IC device 1000.
Having described IC devices with test elements that can enable accurate testing of circuit devices, particular test operations according to embodiments will now be described.
In the test operation, a word line 1138 can be driven to a level that enables pass transistors N0/N1. Such a word line voltage can be substantially higher than an array high supply voltage VDDAR. In the particular embodiment shown, a word line 1138 can be driven to 1.2V while VDDAR=0.6V.
A first test voltage can be applied to a gate of TUT P0 through test element 1102-0 and access transistor N0. Thus, test element 1102-0 can be in a standard state, allowing a signal path to output node 1114-0. In contrast, any test elements (i.e., 1102-1) coupled to the same output node 1114-0 can be in a low leakage cutoff mode, thus an intermediate node within such test elements can be driven to a voltage that can match that at output node 1114-0. In the particular embodiment shown, bit line 1134-0 can be driven to 0V, thus non-selected test element 1102-1 can apply 0V to its intermediate node.
A second “sweeping” test voltage can be applied to a drain of TUT P0 through test element 1102-2 and access device N1. Thus, test element 1102-2 can be in a standard mode while test element (i.e., 1102-3) coupled to the same output node 1114-1 can be in a low leakage cutoff mode. A sweeping voltage can vary over time, enabling multiple current (Imeas) values to be acquired. Non-selected test element 1102-3 can apply substantially the same sweeping voltage to its internal node. In the particular embodiment shown, bit line 1134-1 can be swept between 0V and 0.5V, and a resulting current (Imeas) can be measured at various points, thus providing an accurate characterization of TUT P0.
It is understood that the other p-channel load transistor P1 can be tested in the same fashion as P0 by swapping the test voltages applied to the bit lines.
In the test operation, a word line 1138 can be driven as in
A first sweeping voltage can be applied to a gate of TUT P0 through test element 1102-0 and access transistor N0. In addition, a low array power supply voltage VSSAR can be swept in the same fashion. Selected test element 1102-0 can be in a standard state, while non-selected test elements (e.g., 1102-1) coupled to a same output node 1114-0 can be in a low leakage cutoff mode, and receive the same, or substantially same sweeping voltage. In the embodiment shown, a sweeping voltage can be between 0.6 and 0 V.
A second test voltage can be applied to a drain of TUT P0 through test element 1102-2 and access device N1. Selected test element 1102-2 can be in a standard mode and non-selected test elements (i.e., 1102-3) can be in a low leakage cutoff mode and receive substantially the same voltage. In the particular embodiment shown, bit line 1134-1 can receive 0.6V.
Current (Imeas) through bit line 1134-1 can be measured to provide accurate characterization of TUT P0.
It is understood that the other p-channel load transistor P1 can be tested in the same fashion as P0 by swapping the test voltages applied to the bit lines.
In the test operation, a word line 1138 can be driven to a test level which gives a desired current response based on the drain-source voltage (VDS) applied to TUT N0. In the particular embodiment shown, a word line 1138 can be driven to 0.6V. An array high supply voltage VDDAR can be 1.2V.
A first sweeping voltage can be applied to a drain of transistor N0 by way of bit line 1134-0. A selected test element 1102-0 can be in a standard state, while non-selected test elements (e.g., 1102-1) can be coupled to receive the same, or substantially the same, sweeping voltage. In the embodiment shown, a sweeping voltage can be between 0.6 and 0 V.
A second test voltage can be applied to a gate of transistor N3 to ensure N3 provides a current path to VSSAR for TUT N0. Selected test element 1102-2 can be in a standard mode and non-selected test elements (i.e., 1102-3) can be in a low leakage cutoff mode. In the particular embodiment shown, bit line 1134-1 and non-selected test element 1102-3 can receive 1.2V.
Current (Imeas) through bit line 1134-0 can be measured to provide accurate characterization of TUT N0.
It is understood that the other access transistor N1 can be tested in the same fashion as N0 by swapping the test voltages applied to the bit lines.
In the test operation, a word line 1138 can be driven to a test level that enables access transistors N0/N1. In the particular embodiment shown, a word line 1138 can be driven to 1.2V. An array high supply voltage VDDAR can be 0.6V. A substrate voltage for transistors P0/1 (VPsub) can be driven to 1.6V.
A first test voltage can be applied to a gate of transistor N2 through access transistor N0. Selected test element 1102-0 can be in a standard mode, while non-selected test elements (e.g., 1102-1) can be in the low leakage cutoff mode.
A second sweeping test voltage can be applied to a drain of transistor N2 through access transistor N1 to generate a current Imeas that varies according to the VDS of TUT N2. In the particular embodiment shown, such sweeping voltage can be between 0.2 and 0.6 V.
It is noted that body biases (VNsub) can be applied to the TUT (e.g., N2/N3) to raise threshold voltages of such devices. This can reduce unwanted currents in the memory cell 1136. In the particular embodiment shown, such biases can be between 0 and 0.4 V.
It is understood that the other n-channel pull-down transistor N3 can be tested in the same fashion as N2 by swapping the test voltages applied to the bit lines.
It is noted that in the testing operations shown in
Test operations such as those described herein can result in high fidelity characterization of transistors within a tested portion of an IC device. In some embodiments, current accuracy can be within 1% using appropriate biasing conditions.
It is noted that a threshold voltage (Vt) can be value established according to well understood techniques. For example, a threshold voltage can be a Vgs at which a drain-to-source current (IDS) has a predetermined value for a given drain-to-source voltage (VDS).
As noted above, while embodiments having memory sections can test transistors within memory cells, for some architectures (e.g.,
Referring now to
A column MUX/precharge section 1332 can be coupled between bit lines (BIT/BITN) and sense nodes 1350-0/1. In response to a precharge signal (prebitn), column MUX/precharge section 1332 can precharge bit lines (BIT/BITN) to a precharge potential. In response to column select data (csel), column MUX/precharge section 1332 can couple a bit line pair (BIT/BITN) to sense nodes 1350-0/1.
A sense amplifier (SA) 1352 can sense a data value on a selected bit line pair (BIT/BITN). In a sense operation, prior to sensing a data value, sense nodes 1350-0/1 can be precharged to a SA precharge voltage by activation of SA precharge signal (presan). When sensing a data value, bit line precharge circuits in 1332 can be disabled. A memory cell can be coupled to a bit line pair (BIT/BITN), and the bit line pair coupled to sense nodes 1350-0/1 by operation of column MUX/precharge section 1332. According to a data value stored in the memory cell, a differential voltage can develop across a bit line pair (BIT/BITN), and hence across sense nodes 1350-0/1. When sense amplifier enable signals (sae/saen) are activated, the sense nodes 1350-0/1 can be driven to opposing voltages based on the differential voltage.
Unlike a conventional sense amplifier, SA 1352 of
An I/O section 1374 can output data (dout) based on potentials across sense nodes 1350-0/1, or can drive data on sense nodes 1350-0/1 in response to input data (din). In particular, in response to an active read enable signal (renable), a data output (dout) will be driven based on a potential between sense nodes 1350-0/1. In response to an active write enable signal (wenable), sense nodes 1350-0/1 will be driven to different voltages according to an input data value (din).
A test section 1302 can include test elements as described herein, or equivalents. Such test elements can be enabled in response to a test enable signal (dbsel). When enabled, test voltages can be driven on outputs 1314-0/1 and/or current flowing through outputs 1314-0/1 can be measured. Further, signal paths for such test values can be very low leakage signals paths as described above.
Referring to
A column MUX/precharge section 1432 can include bit line precharge circuits 1476-0 to -3 and column select circuits 1478-0 to -3, each of which can be coupled to a corresponding bit line pair bit<n>, bitn<n> (where n=0 to 3). In response to an active precharge signal prebitn, precharge circuits (1476-0 to -3) can precharge their respective bit lines bit<n>/bitn<n> to a precharge voltage VDDpc. In response to particular column select signals csel<n>, cseln<n> (where n=0 to 3), a column select circuit (1476-0 to -3) can couple its bit line pair to sense nodes 1450-0/1.
Referring to
SA 1552 can include SA precharge circuits 1580-0/1, p-channel sense transistors P4/P5 and n-channel sense transistors N7/N8 cross-coupled between sense nodes 1550-0/1, a first enable transistor P6 coupled between a first enable node 1582-0 and a high power supply node VDD, a second enable transistor N9 coupled between a second enable node 1582-1 and a low power supply voltage VSS, a first test transistor N10 coupled between first enable node 1582-0 and a low power supply voltage VSS, and a second test transistor P7 coupled between second enable node 1582-1 and a high power supply voltage VDD.
SA precharge circuits 1580-0/1 can be commonly controlled according to signal presan. When signal presan is active (low), SA precharge circuits 1580-0/1 can precharge sense nodes 1550-0/1 and enable nodes 1582-0/1 to a SA precharge voltage (Vbias). Enable transistor P6 can be controlled according to signal saen to connect or isolate first enable node 1582-0 from supply voltage VDD. Similarly, enable transistor N9 can be controlled according to signal sae to connect or isolate second enable node 1582-1 from supply voltage VSS. Test transistor N10 can be controlled according to signal ntest to disable sense transistors P4/P5 and enable the testing of sense transistor N7 or N8 by coupling first enable node 1582-0 to VSS. Test transistor P7 can be controlled according to signal ptestn to disable sense transistors N7/N8 and enable the testing of sense transistor P4 or P5 by coupling second enable node 1582-1 to VDD.
Having described various sections of an IC device (i.e.,
Referring now to
Referring again to
Referring again to
Referring once again to
Referring now to
Referring now to
Signal csel can be disabled (csel=0), isolating bit lines BL/BLN from sense nodes 1350-0/1. In the embodiment shown, prebitn=1, disabling bit line precharge circuits 1476-0/1. Signal dbsel can be active (dbsel=1) enabling test elements within test section 1302. In addition, wenable=0, disabling write amplifiers within I/O section 1374. However, renable=1, enabling I/O section 1374 to drive dout based on voltages between sense nodes 1350-0/1.
While
An Offset test for IC device 1800 can start with precharge devices P8/P9 being disabled (prch=1). A reasonably large differential voltage can be generated across sense nodes 1850-0/1. SA 1852 can be activated (saen=0/1 pulse) to generate an output value. Such actions can be repeated with reduced differential values, as described for
An Offset test for IC device 1900 can occur in a like fashion to that of
Integrated circuit devices according to embodiments shown herein, and equivalents, may provide improved characterization of device elements by providing high fidelity test paths to various internal nodes of the device.
In very particular SRAM embodiments, transistors within individual memory cells can be characterized. In addition or alternatively, transistors within sense amplifiers and/or a sense amplifier offset voltage can be accurately characterized. Such data can enable circuits and threshold levels to be optimized to actual transistor response, as opposed to being constructed with “guard-band” responses designed to accommodate a wide range of variation in transistor and/or SA response.
In alternative embodiments, the test elements 102 can be used for measurement and characterization of analog circuits, such as a comparator in a flash analog to digital converter. Thus, the various embodiments and test operation described above can also be used to determine as-fabricated offsets in such analog circuits.
It should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
It is also understood that the embodiments of the invention may be practiced in the absence of an element and/or step not specifically disclosed. That is, an inventive feature of the invention may be elimination of an element.
Accordingly, while the various aspects of the particular embodiments set forth herein have been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention.
Number | Name | Date | Kind |
---|---|---|---|
3958266 | Athanas | May 1976 | A |
4000504 | Berger | Dec 1976 | A |
4021835 | Etoh et al. | May 1977 | A |
4242691 | Kotani et al. | Dec 1980 | A |
4276095 | Beilstein, Jr. et al. | Jun 1981 | A |
4315781 | Henderson | Feb 1982 | A |
4518926 | Swanson | May 1985 | A |
4559091 | Allen et al. | Dec 1985 | A |
4578128 | Mundt et al. | Mar 1986 | A |
4617066 | Vasudev | Oct 1986 | A |
4662061 | Malhi | May 1987 | A |
4761384 | Neppl et al. | Aug 1988 | A |
4780748 | Cunningham et al. | Oct 1988 | A |
4819043 | Yazawa et al. | Apr 1989 | A |
4885477 | Bird et al. | Dec 1989 | A |
4908681 | Nishida et al. | Mar 1990 | A |
4945254 | Robbins | Jul 1990 | A |
4956311 | Liou et al. | Sep 1990 | A |
5034337 | Mosher et al. | Jul 1991 | A |
5144378 | Hikosaka | Sep 1992 | A |
5156989 | Williams et al. | Oct 1992 | A |
5156990 | Mitchell | Oct 1992 | A |
5166765 | Lee et al. | Nov 1992 | A |
5208473 | Komori et al. | May 1993 | A |
5294821 | Iwamatsu | Mar 1994 | A |
5298763 | Shen et al. | Mar 1994 | A |
5369288 | Usuki | Nov 1994 | A |
5373186 | Schubert et al. | Dec 1994 | A |
5384476 | Nishizawa et al. | Jan 1995 | A |
5426328 | Yilmaz et al. | Jun 1995 | A |
5438270 | Harper et al. | Aug 1995 | A |
5444008 | Han et al. | Aug 1995 | A |
5552332 | Tseng et al. | Sep 1996 | A |
5559368 | Hu et al. | Sep 1996 | A |
5608253 | Liu et al. | Mar 1997 | A |
5622880 | Burr et al. | Apr 1997 | A |
5624863 | Helm et al. | Apr 1997 | A |
5625568 | Edwards et al. | Apr 1997 | A |
5641980 | Yamaguchi et al. | Jun 1997 | A |
5663583 | Matloubian et al. | Sep 1997 | A |
5712501 | Davies et al. | Jan 1998 | A |
5719422 | Burr et al. | Feb 1998 | A |
5726488 | Watanabe et al. | Mar 1998 | A |
5726562 | Mizuno | Mar 1998 | A |
5731626 | Eaglesham et al. | Mar 1998 | A |
5736419 | Naem | Apr 1998 | A |
5753555 | Hada | May 1998 | A |
5754826 | Gamal et al. | May 1998 | A |
5756365 | Kakumu | May 1998 | A |
5763921 | Okumura et al. | Jun 1998 | A |
5780899 | Hu et al. | Jul 1998 | A |
5841716 | Iwaki | Nov 1998 | A |
5847419 | Imai et al. | Dec 1998 | A |
5856003 | Chiu | Jan 1999 | A |
5861334 | Rho | Jan 1999 | A |
5877049 | Liu et al. | Mar 1999 | A |
5885876 | Dennen | Mar 1999 | A |
5889315 | Farrenkopf et al. | Mar 1999 | A |
5895954 | Yasumura et al. | Apr 1999 | A |
5899714 | Farrenkopf et al. | May 1999 | A |
5918129 | Fulford, Jr. et al. | Jun 1999 | A |
5923067 | Voldman | Jul 1999 | A |
5923987 | Burr | Jul 1999 | A |
5936868 | Hall | Aug 1999 | A |
5946214 | Heavlin | Aug 1999 | A |
5985705 | Seliskar | Nov 1999 | A |
5989963 | Luning et al. | Nov 1999 | A |
5999466 | Marr et al. | Dec 1999 | A |
6001695 | Wu | Dec 1999 | A |
6020227 | Bulucea | Feb 2000 | A |
6043139 | Eaglesham et al. | Mar 2000 | A |
6060345 | Hause et al. | May 2000 | A |
6060364 | Maszara et al. | May 2000 | A |
6066533 | Yu | May 2000 | A |
6072217 | Burr | Jun 2000 | A |
6087210 | Sohn | Jul 2000 | A |
6087691 | Hamamoto | Jul 2000 | A |
6088518 | Hsu | Jul 2000 | A |
6091286 | Blauschild | Jul 2000 | A |
6096611 | Wu | Aug 2000 | A |
6103562 | Son et al. | Aug 2000 | A |
6121153 | Kikkawa | Sep 2000 | A |
6147383 | Kuroda | Nov 2000 | A |
6153920 | Gossmann et al. | Nov 2000 | A |
6157073 | Lehongres | Dec 2000 | A |
6160746 | Park et al. | Dec 2000 | A |
6175582 | Naito et al. | Jan 2001 | B1 |
6184112 | Maszara et al. | Feb 2001 | B1 |
6190979 | Radens et al. | Feb 2001 | B1 |
6194259 | Nayak et al. | Feb 2001 | B1 |
6198157 | Ishida et al. | Mar 2001 | B1 |
6218892 | Soumyanath et al. | Apr 2001 | B1 |
6218895 | De et al. | Apr 2001 | B1 |
6221724 | Yu et al. | Apr 2001 | B1 |
6229188 | Aoki et al. | May 2001 | B1 |
6232164 | Tsai et al. | May 2001 | B1 |
6235597 | Miles | May 2001 | B1 |
6245618 | An et al. | Jun 2001 | B1 |
6249468 | Kan et al. | Jun 2001 | B1 |
6268640 | Park et al. | Jul 2001 | B1 |
6271070 | Kotani et al. | Aug 2001 | B2 |
6271551 | Schmitz et al. | Aug 2001 | B1 |
6288429 | Iwata et al. | Sep 2001 | B1 |
6297132 | Zhang et al. | Oct 2001 | B1 |
6300177 | Sundaresan et al. | Oct 2001 | B1 |
6313489 | Letavic et al. | Nov 2001 | B1 |
6319799 | Ouyang et al. | Nov 2001 | B1 |
6320222 | Forbes et al. | Nov 2001 | B1 |
6323525 | Noguchi et al. | Nov 2001 | B1 |
6326666 | Bernstein et al. | Dec 2001 | B1 |
6335233 | Cho et al. | Jan 2002 | B1 |
6358806 | Puchner | Mar 2002 | B1 |
6380019 | Yu et al. | Apr 2002 | B1 |
6391752 | Colinge et al. | May 2002 | B1 |
6426260 | Hshieh | Jul 2002 | B1 |
6426279 | Huster et al. | Jul 2002 | B1 |
6432754 | Assaderaghi et al. | Aug 2002 | B1 |
6444550 | Hao et al. | Sep 2002 | B1 |
6444551 | Ku et al. | Sep 2002 | B1 |
6449749 | Stine | Sep 2002 | B1 |
6461920 | Shirahata | Oct 2002 | B1 |
6461928 | Rodder | Oct 2002 | B2 |
6472278 | Marshall et al. | Oct 2002 | B1 |
6482714 | Hieda et al. | Nov 2002 | B1 |
6489224 | Burr | Dec 2002 | B1 |
6492232 | Tang et al. | Dec 2002 | B1 |
6500739 | Wang et al. | Dec 2002 | B1 |
6503801 | Rouse et al. | Jan 2003 | B1 |
6503805 | Wang et al. | Jan 2003 | B2 |
6506640 | Ishida et al. | Jan 2003 | B1 |
6518623 | Oda et al. | Feb 2003 | B1 |
6521470 | Lin et al. | Feb 2003 | B1 |
6534373 | Yu | Mar 2003 | B1 |
6541328 | Whang et al. | Apr 2003 | B2 |
6541829 | Nishinohara et al. | Apr 2003 | B2 |
6548842 | Bulucea et al. | Apr 2003 | B1 |
6551885 | Yu | Apr 2003 | B1 |
6552377 | Yu | Apr 2003 | B1 |
6560141 | Osada et al. | May 2003 | B2 |
6573129 | Hoke et al. | Jun 2003 | B2 |
6576535 | Drobny et al. | Jun 2003 | B2 |
6600200 | Lustig et al. | Jul 2003 | B1 |
6620671 | Wang et al. | Sep 2003 | B1 |
6624488 | Kim | Sep 2003 | B1 |
6627473 | Oikawa et al. | Sep 2003 | B1 |
6630710 | Augusto | Oct 2003 | B1 |
6660605 | Liu | Dec 2003 | B1 |
6662350 | Fried et al. | Dec 2003 | B2 |
6667200 | Sohn et al. | Dec 2003 | B2 |
6670260 | Yu et al. | Dec 2003 | B1 |
6693333 | Yu | Feb 2004 | B1 |
6730568 | Sohn | May 2004 | B2 |
6737724 | Hieda et al. | May 2004 | B2 |
6743291 | Ang et al. | Jun 2004 | B2 |
6743684 | Liu | Jun 2004 | B2 |
6751519 | Satya et al. | Jun 2004 | B1 |
6753230 | Sohn et al. | Jun 2004 | B2 |
6760900 | Rategh et al. | Jul 2004 | B2 |
6770944 | Nishinohara et al. | Aug 2004 | B2 |
6787424 | Yu | Sep 2004 | B1 |
6797553 | Adkisson et al. | Sep 2004 | B2 |
6797602 | Kluth et al. | Sep 2004 | B1 |
6797994 | Hoke et al. | Sep 2004 | B1 |
6808004 | Kamm et al. | Oct 2004 | B2 |
6808994 | Wang | Oct 2004 | B1 |
6813750 | Usami et al. | Nov 2004 | B2 |
6821825 | Todd et al. | Nov 2004 | B2 |
6821852 | Rhodes | Nov 2004 | B2 |
6822297 | Nandakumar et al. | Nov 2004 | B2 |
6831292 | Currie et al. | Dec 2004 | B2 |
6835639 | Rotondaro et al. | Dec 2004 | B2 |
6852602 | Kanzawa et al. | Feb 2005 | B2 |
6852603 | Chakravarthi et al. | Feb 2005 | B2 |
6881641 | Wieczorek et al. | Apr 2005 | B2 |
6881987 | Sohn | Apr 2005 | B2 |
6891439 | Jachne et al. | May 2005 | B2 |
6893947 | Martinez et al. | May 2005 | B2 |
6900519 | Cantell et al. | May 2005 | B2 |
6901564 | Stine et al. | May 2005 | B2 |
6916698 | Mocuta et al. | Jul 2005 | B2 |
6917192 | Xin-LeBlanc et al. | Jul 2005 | B1 |
6917237 | Tschanz et al. | Jul 2005 | B1 |
6927463 | Iwata et al. | Aug 2005 | B2 |
6928128 | Sidiropoulos | Aug 2005 | B1 |
6930007 | Bu et al. | Aug 2005 | B2 |
6930360 | Yamauchi et al. | Aug 2005 | B2 |
6957163 | Ando | Oct 2005 | B2 |
6963090 | Passlack et al. | Nov 2005 | B2 |
6995397 | Yamashita et al. | Feb 2006 | B2 |
7002214 | Boyd et al. | Feb 2006 | B1 |
7008836 | Algotsson et al. | Mar 2006 | B2 |
7013359 | Li | Mar 2006 | B1 |
7015546 | Herr et al. | Mar 2006 | B2 |
7015741 | Tschanz et al. | Mar 2006 | B2 |
7022559 | Barnak et al. | Apr 2006 | B2 |
7036098 | Eleyan et al. | Apr 2006 | B2 |
7038258 | Liu et al. | May 2006 | B2 |
7039881 | Regan | May 2006 | B2 |
7045456 | Murto et al. | May 2006 | B2 |
7057216 | Ouyang et al. | Jun 2006 | B2 |
7061058 | Chakravarthi et al. | Jun 2006 | B2 |
7064039 | Liu | Jun 2006 | B2 |
7064399 | Babcock et al. | Jun 2006 | B2 |
7071103 | Chan et al. | Jul 2006 | B2 |
7078325 | Curello et al. | Jul 2006 | B2 |
7078776 | Nishinohara et al. | Jul 2006 | B2 |
7089513 | Bard et al. | Aug 2006 | B2 |
7089515 | Hanafi et al. | Aug 2006 | B2 |
7091093 | Noda et al. | Aug 2006 | B1 |
7105399 | Dakshina-Murthy et al. | Sep 2006 | B1 |
7109099 | Tan et al. | Sep 2006 | B2 |
7119381 | Passlack | Oct 2006 | B2 |
7122411 | Mouli | Oct 2006 | B2 |
7127687 | Signore | Oct 2006 | B1 |
7132323 | Haensch et al. | Nov 2006 | B2 |
7169675 | Tan et al. | Jan 2007 | B2 |
7170120 | Datta et al. | Jan 2007 | B2 |
7176137 | Perng et al. | Feb 2007 | B2 |
7186598 | Yamauchi et al. | Mar 2007 | B2 |
7189627 | Wu et al. | Mar 2007 | B2 |
7199430 | Babcock et al. | Apr 2007 | B2 |
7202517 | Dixit et al. | Apr 2007 | B2 |
7208354 | Bauer | Apr 2007 | B2 |
7211871 | Cho | May 2007 | B2 |
7221021 | Wu et al. | May 2007 | B2 |
7223646 | Miyashita et al. | May 2007 | B2 |
7226833 | White et al. | Jun 2007 | B2 |
7226843 | Weber et al. | Jun 2007 | B2 |
7230680 | Fujisawa et al. | Jun 2007 | B2 |
7235822 | Li | Jun 2007 | B2 |
7256639 | Koniaris et al. | Aug 2007 | B1 |
7259428 | Inaba | Aug 2007 | B2 |
7260562 | Czajkowski et al. | Aug 2007 | B2 |
7294877 | Rueckes et al. | Nov 2007 | B2 |
7297994 | Wieczorek et al. | Nov 2007 | B2 |
7301208 | Handa et al. | Nov 2007 | B2 |
7304350 | Misaki | Dec 2007 | B2 |
7307471 | Gammie et al. | Dec 2007 | B2 |
7312500 | Miyashita et al. | Dec 2007 | B2 |
7323754 | Ema et al. | Jan 2008 | B2 |
7332439 | Lindert et al. | Feb 2008 | B2 |
7333379 | Ramadurai et al. | Feb 2008 | B2 |
7348629 | Chu et al. | Mar 2008 | B2 |
7354833 | Liaw | Apr 2008 | B2 |
7380225 | Joshi et al. | May 2008 | B2 |
7385864 | Loh et al. | Jun 2008 | B2 |
7398497 | Sato et al. | Jul 2008 | B2 |
7402207 | Besser et al. | Jul 2008 | B1 |
7402872 | Murthy et al. | Jul 2008 | B2 |
7416605 | Zollner et al. | Aug 2008 | B2 |
7427788 | Li et al. | Sep 2008 | B2 |
7442971 | Wirbeleit et al. | Oct 2008 | B2 |
7449733 | Inaba et al. | Nov 2008 | B2 |
7462908 | Bol et al. | Dec 2008 | B2 |
7469164 | Du-Nour | Dec 2008 | B2 |
7470593 | Rouh et al. | Dec 2008 | B2 |
7474132 | Cheng | Jan 2009 | B2 |
7485536 | Jin et al. | Feb 2009 | B2 |
7487474 | Ciplickas et al. | Feb 2009 | B2 |
7491988 | Tolchinsky et al. | Feb 2009 | B2 |
7494861 | Chu et al. | Feb 2009 | B2 |
7496862 | Chang et al. | Feb 2009 | B2 |
7496867 | Turner et al. | Feb 2009 | B2 |
7498637 | Yamaoka et al. | Mar 2009 | B2 |
7501324 | Babcock et al. | Mar 2009 | B2 |
7503020 | Allen et al. | Mar 2009 | B2 |
7507999 | Kusumoto et al. | Mar 2009 | B2 |
7514766 | Yoshida | Apr 2009 | B2 |
7521323 | Surdeanu et al. | Apr 2009 | B2 |
7531393 | Doyle et al. | May 2009 | B2 |
7531836 | Liu et al. | May 2009 | B2 |
7538364 | Twynam | May 2009 | B2 |
7538412 | Schulze et al. | May 2009 | B2 |
7562233 | Sheng et al. | Jul 2009 | B1 |
7564105 | Chi et al. | Jul 2009 | B2 |
7566600 | Mouli | Jul 2009 | B2 |
7569456 | Ko et al. | Aug 2009 | B2 |
7586322 | Xu et al. | Sep 2009 | B1 |
7592241 | Takao | Sep 2009 | B2 |
7595243 | Bulucea et al. | Sep 2009 | B1 |
7598142 | Ranade et al. | Oct 2009 | B2 |
7605041 | Ema et al. | Oct 2009 | B2 |
7605060 | Meunier-Beillard et al. | Oct 2009 | B2 |
7605429 | Bernstein et al. | Oct 2009 | B2 |
7608496 | Chu | Oct 2009 | B2 |
7615802 | Elpelt et al. | Nov 2009 | B2 |
7622341 | Chudzik et al. | Nov 2009 | B2 |
7638380 | Pearce | Dec 2009 | B2 |
7642140 | Bae et al. | Jan 2010 | B2 |
7644377 | Saxe et al. | Jan 2010 | B1 |
7645665 | Kubo et al. | Jan 2010 | B2 |
7651920 | Siprak | Jan 2010 | B2 |
7655523 | Babcock et al. | Feb 2010 | B2 |
7673273 | Madurawe et al. | Mar 2010 | B2 |
7675126 | Cho | Mar 2010 | B2 |
7675317 | Perisetty | Mar 2010 | B2 |
7678638 | Chu et al. | Mar 2010 | B2 |
7681628 | Joshi et al. | Mar 2010 | B2 |
7682887 | Dokumaci et al. | Mar 2010 | B2 |
7683442 | Burr et al. | Mar 2010 | B1 |
7696000 | Liu et al. | Apr 2010 | B2 |
7704822 | Jeong | Apr 2010 | B2 |
7704844 | Zhu et al. | Apr 2010 | B2 |
7709828 | Braithwaite et al. | May 2010 | B2 |
7723750 | Zhu et al. | May 2010 | B2 |
7737472 | Kondo et al. | Jun 2010 | B2 |
7741138 | Cho | Jun 2010 | B2 |
7741200 | Cho et al. | Jun 2010 | B2 |
7745270 | Shah et al. | Jun 2010 | B2 |
7750374 | Capasso et al. | Jul 2010 | B2 |
7750381 | Hokazono et al. | Jul 2010 | B2 |
7750405 | Nowak | Jul 2010 | B2 |
7750682 | Bernstein et al. | Jul 2010 | B2 |
7755144 | Li et al. | Jul 2010 | B2 |
7755146 | Helm et al. | Jul 2010 | B2 |
7759206 | Luo et al. | Jul 2010 | B2 |
7759714 | Itoh et al. | Jul 2010 | B2 |
7761820 | Berger et al. | Jul 2010 | B2 |
7795677 | Bangsaruntip et al. | Sep 2010 | B2 |
7808045 | Kawahara et al. | Oct 2010 | B2 |
7808410 | Kim et al. | Oct 2010 | B2 |
7811873 | Mochizuki | Oct 2010 | B2 |
7811881 | Cheng et al. | Oct 2010 | B2 |
7818702 | Mandelman et al. | Oct 2010 | B2 |
7821066 | Lebby et al. | Oct 2010 | B2 |
7829402 | Matocha et al. | Nov 2010 | B2 |
7831873 | Trimberger et al. | Nov 2010 | B1 |
7846822 | Seebauer et al. | Dec 2010 | B2 |
7855118 | Hoentschel et al. | Dec 2010 | B2 |
7859013 | Chen et al. | Dec 2010 | B2 |
7863163 | Bauer | Jan 2011 | B2 |
7867835 | Lee et al. | Jan 2011 | B2 |
7883977 | Babcock et al. | Feb 2011 | B2 |
7888205 | Hemer et al. | Feb 2011 | B2 |
7888747 | Hokazono | Feb 2011 | B2 |
7895546 | Lahner et al. | Feb 2011 | B2 |
7897495 | Ye et al. | Mar 2011 | B2 |
7906413 | Cardone et al. | Mar 2011 | B2 |
7906813 | Kato | Mar 2011 | B2 |
7910419 | Fenouillet-Beranger et al. | Mar 2011 | B2 |
7919791 | Flynn et al. | Apr 2011 | B2 |
7926018 | Moroz et al. | Apr 2011 | B2 |
7935984 | Nakano | May 2011 | B2 |
7941776 | Majumder et al. | May 2011 | B2 |
7945800 | Gomm et al. | May 2011 | B2 |
7948008 | Liu et al. | May 2011 | B2 |
7952147 | Ueno et al. | May 2011 | B2 |
7960232 | King et al. | Jun 2011 | B2 |
7960238 | Kohli et al. | Jun 2011 | B2 |
7968400 | Cai | Jun 2011 | B2 |
7968411 | Williford | Jun 2011 | B2 |
7968440 | Seebauer | Jun 2011 | B2 |
7968459 | Bedell et al. | Jun 2011 | B2 |
7989900 | Haensch et al. | Aug 2011 | B2 |
7994573 | Pan | Aug 2011 | B2 |
8004024 | Furukawa et al. | Aug 2011 | B2 |
8012827 | Yu et al. | Sep 2011 | B2 |
8029620 | Kim et al. | Oct 2011 | B2 |
8039332 | Bernard et al. | Oct 2011 | B2 |
8046598 | Lee | Oct 2011 | B2 |
8048791 | Hargrove et al. | Nov 2011 | B2 |
8048810 | Tsai et al. | Nov 2011 | B2 |
8051340 | Cranford, Jr. et al. | Nov 2011 | B2 |
8053340 | Colombeau et al. | Nov 2011 | B2 |
8063466 | Kurita | Nov 2011 | B2 |
8067279 | Sadra et al. | Nov 2011 | B2 |
8067280 | Wang et al. | Nov 2011 | B2 |
8067302 | Li | Nov 2011 | B2 |
8076719 | Zeng et al. | Dec 2011 | B2 |
8097529 | Krull et al. | Jan 2012 | B2 |
8103983 | Agarwal et al. | Jan 2012 | B2 |
8105891 | Yeh et al. | Jan 2012 | B2 |
8106424 | Schruefer | Jan 2012 | B2 |
8106481 | Rao | Jan 2012 | B2 |
8110487 | Griebenow et al. | Feb 2012 | B2 |
8114761 | Mandrekar et al. | Feb 2012 | B2 |
8119482 | Bhalla et al. | Feb 2012 | B2 |
8120069 | Hynecek | Feb 2012 | B2 |
8129246 | Babcock et al. | Mar 2012 | B2 |
8129797 | Chen et al. | Mar 2012 | B2 |
8134159 | Hokazono | Mar 2012 | B2 |
8143120 | Kerr et al. | Mar 2012 | B2 |
8143124 | Challa et al. | Mar 2012 | B2 |
8143678 | Kim et al. | Mar 2012 | B2 |
8148774 | Mori et al. | Apr 2012 | B2 |
8163619 | Yang et al. | Apr 2012 | B2 |
8169002 | Chang et al. | May 2012 | B2 |
8170857 | Joshi et al. | May 2012 | B2 |
8173499 | Chung et al. | May 2012 | B2 |
8173502 | Yan et al. | May 2012 | B2 |
8176461 | Trimberger | May 2012 | B1 |
8178430 | Kim et al. | May 2012 | B2 |
8179530 | Levy et al. | May 2012 | B2 |
8183096 | Wirbeleit | May 2012 | B2 |
8183107 | Mathur et al. | May 2012 | B2 |
8185865 | Gupta et al. | May 2012 | B2 |
8187959 | Pawlak et al. | May 2012 | B2 |
8188542 | Yoo et al. | May 2012 | B2 |
8196545 | Kurosawa | Jun 2012 | B2 |
8201122 | Dewey, III et al. | Jun 2012 | B2 |
8214190 | Joshi et al. | Jul 2012 | B2 |
8217423 | Liu et al. | Jul 2012 | B2 |
8225255 | Ouyang et al. | Jul 2012 | B2 |
8227307 | Chen et al. | Jul 2012 | B2 |
8236661 | Dennard et al. | Aug 2012 | B2 |
8239803 | Kobayashi | Aug 2012 | B2 |
8247300 | Babcock et al. | Aug 2012 | B2 |
8255843 | Chen et al. | Aug 2012 | B2 |
8258026 | Bulucea | Sep 2012 | B2 |
8266567 | El Yahyaoui et al. | Sep 2012 | B2 |
8286180 | Foo | Oct 2012 | B2 |
8288798 | Passlack | Oct 2012 | B2 |
8299562 | Li et al. | Oct 2012 | B2 |
8324059 | Guo et al. | Dec 2012 | B2 |
20010014495 | Yu | Aug 2001 | A1 |
20020042184 | Nandakumar et al. | Apr 2002 | A1 |
20030006415 | Yokogawa et al. | Jan 2003 | A1 |
20030047763 | Hieda et al. | Mar 2003 | A1 |
20030122203 | Nishinohara et al. | Jul 2003 | A1 |
20030173626 | Burr | Sep 2003 | A1 |
20030183856 | Wieczorek et al. | Oct 2003 | A1 |
20030215992 | Sohn et al. | Nov 2003 | A1 |
20040075118 | Heinemann et al. | Apr 2004 | A1 |
20040075143 | Bae et al. | Apr 2004 | A1 |
20040084731 | Matsuda et al. | May 2004 | A1 |
20040087090 | Grudowski et al. | May 2004 | A1 |
20040126947 | Sohn | Jul 2004 | A1 |
20040175893 | Vatus et al. | Sep 2004 | A1 |
20040180488 | Lee | Sep 2004 | A1 |
20050106824 | Alberto et al. | May 2005 | A1 |
20050116282 | Pattanayak et al. | Jun 2005 | A1 |
20050250289 | Babcock et al. | Nov 2005 | A1 |
20050280075 | Ema et al. | Dec 2005 | A1 |
20060022270 | Boyd et al. | Feb 2006 | A1 |
20060049464 | Rao | Mar 2006 | A1 |
20060068555 | Zhu et al. | Mar 2006 | A1 |
20060068586 | Pain | Mar 2006 | A1 |
20060071278 | Takao | Apr 2006 | A1 |
20060154428 | Dokumaci | Jul 2006 | A1 |
20060197158 | Babcock et al. | Sep 2006 | A1 |
20060203581 | Joshi et al. | Sep 2006 | A1 |
20060220114 | Miyashita et al. | Oct 2006 | A1 |
20060223248 | Venugopal et al. | Oct 2006 | A1 |
20070040222 | Van Camp et al. | Feb 2007 | A1 |
20070117326 | Tan et al. | May 2007 | A1 |
20070158790 | Rao | Jul 2007 | A1 |
20070212861 | Chidambarrao et al. | Sep 2007 | A1 |
20070238253 | Tucker | Oct 2007 | A1 |
20080067589 | Ito et al. | Mar 2008 | A1 |
20080108208 | Arevalo et al. | May 2008 | A1 |
20080169493 | Lee et al. | Jul 2008 | A1 |
20080169516 | Chung | Jul 2008 | A1 |
20080197439 | Goerlach et al. | Aug 2008 | A1 |
20080227250 | Ranade et al. | Sep 2008 | A1 |
20080237661 | Ranade et al. | Oct 2008 | A1 |
20080258198 | Bojarczuk et al. | Oct 2008 | A1 |
20080272409 | Sonkusale et al. | Nov 2008 | A1 |
20090057746 | Sugll et al. | Mar 2009 | A1 |
20090108350 | Cai et al. | Apr 2009 | A1 |
20090134468 | Tsuchiya et al. | May 2009 | A1 |
20090224319 | Kohli | Sep 2009 | A1 |
20090302388 | Cai et al. | Dec 2009 | A1 |
20090309140 | Khamankar et al. | Dec 2009 | A1 |
20090311837 | Kapoor | Dec 2009 | A1 |
20090321849 | Miyamura et al. | Dec 2009 | A1 |
20100012988 | Yang et al. | Jan 2010 | A1 |
20100038724 | Anderson et al. | Feb 2010 | A1 |
20100100856 | Mittal | Apr 2010 | A1 |
20100148153 | Hudait et al. | Jun 2010 | A1 |
20100149854 | Vora | Jun 2010 | A1 |
20100187641 | Zhu et al. | Jul 2010 | A1 |
20100207182 | Paschal | Aug 2010 | A1 |
20100270600 | Inukai et al. | Oct 2010 | A1 |
20110059588 | Kang | Mar 2011 | A1 |
20110073961 | Dennard et al. | Mar 2011 | A1 |
20110074498 | Thompson et al. | Mar 2011 | A1 |
20110079860 | Verhulst | Apr 2011 | A1 |
20110079861 | Shifren et al. | Apr 2011 | A1 |
20110095811 | Chi et al. | Apr 2011 | A1 |
20110147828 | Murthy et al. | Jun 2011 | A1 |
20110169082 | Zhu et al. | Jul 2011 | A1 |
20110175170 | Wang et al. | Jul 2011 | A1 |
20110180880 | Chudzik et al. | Jul 2011 | A1 |
20110193164 | Zhu | Aug 2011 | A1 |
20110212590 | Wu et al. | Sep 2011 | A1 |
20110230039 | Mowry et al. | Sep 2011 | A1 |
20110242921 | Tran et al. | Oct 2011 | A1 |
20110248352 | Shifren et al. | Oct 2011 | A1 |
20110294278 | Eguchi et al. | Dec 2011 | A1 |
20110309447 | Arghavani et al. | Dec 2011 | A1 |
20120021594 | Gurtej et al. | Jan 2012 | A1 |
20120034745 | Colombeau et al. | Feb 2012 | A1 |
20120065920 | Nagumo et al. | Mar 2012 | A1 |
20120108050 | Chen et al. | May 2012 | A1 |
20120132998 | Kwon et al. | May 2012 | A1 |
20120138953 | Cai et al. | Jun 2012 | A1 |
20120146155 | Hoentschel et al. | Jun 2012 | A1 |
20120167025 | Gillespie et al. | Jun 2012 | A1 |
20120187491 | Zhu et al. | Jul 2012 | A1 |
20120190177 | Kim et al. | Jul 2012 | A1 |
20120223363 | Kronholz et al. | Sep 2012 | A1 |
Number | Date | Country |
---|---|---|
0274278 | Jul 1988 | EP |
0312237 | Apr 1989 | EP |
0531621 | Mar 1993 | EP |
0683515 | Nov 1995 | EP |
0889502 | Jan 1999 | EP |
1450394 | Aug 2004 | EP |
59193066 | Jan 1984 | JP |
4186774 | Mar 1992 | JP |
8288508 | Jan 1996 | JP |
8153873 | Jun 1996 | JP |
2004087671 | Mar 2004 | JP |
10-0794094 | Jul 2003 | KR |
2011062788 | May 2011 | WO |
Entry |
---|
Banerjee et al., “Compensating Non-Optical Effects using Electrically-Driven Optical Proximity Correction”, Proc. of SPIE, vol. 7275, 2009. |
Cheng et al., “Extremely Thin SOI (ETSOI) CMOS with Record Low Variability for Low Power System-on-Chip Applications”, IEDM 2009, Dec. 2009. |
Cheng et al., “Fully Depleted Extremely Thin SOI Technology Fabricated by a Novel Integration Scheme Featuring Implant-Free, Zero-Silicon-Loss, and Faceted Raised Source/Drain”, 2009 Symposium on VLSI Technology Digest of Technical Papers, 2009. |
Drennan et al., “Implications of Proximity Effects for Analog Design”, Custom Integrated Circuits Conference, 2006, CICC '06, IEEE, Sep. 10-13, 2006, pp. 169-176. |
Hook et al., “Lateral Ion Implant Straggle and Mask Proximity Effect”, IEEE Transactions on Electron Devices, vol. 50, No. 9, Sep. 2003. |
Hori et al., “A 0.1 um CMOS with a Step Channel Profile Formed by Ultra High Vacuum CVD and In-Situ Doped Ions”, IEDM 1993, May 12, 1993. |
Matsuhashi et al., “High-Performance Double-Layer Epitaxial-Channel PMOSFET Compatible with a Single Gate CMOSFET”, 1996 Symposium on VLSI Technology Digest of Technical Papers, 1996. |
Shao et al., “Boron diffusion in silicon: the anomalies and control by point defect engineering”, Materials Science and Engineering R 42 (2003), Nov. 2003, pp. 65-114. |
Sheu et al., “Modeling the Well-Edge Proximity Effect in Highly Scaled MOSFETs”, IEEE Transactions on Electron Devices, vol. 53, No. 11, Nov. 2006, pp. 2792-2798. |
English Abstract of JP2004087671 submitted herewith. |
English Abstract of JP4186774 submitted herewith. |
English Abstract of JP59193066 submitted herewith. |
English Abstract of JP8153873 submitted herewith. |
English Abstract of JP8288508 submitted herewith. |
English Translation of JP8288508 submitted herewith. |
Abiko, H et al., “A Channel Engineering Combined with Channel Epitaxy Optimization and TED Suppression for 0.15 μm n-n Gate CMOS Technology”, 1995 Symposium on VLSI Technology Digest of Technical Papers, 1995, pp. 23-24. |
Chau, R et al., “A 50nm Depleted-Substrate CMOS Transistor (DST)”, Electron Device Meeting 2001, IEDM Technical Digest, IEEE International, 2001, pp. 29.1.1-29.1.4. |
Ducroquet, F et al. “Fully Depleted Silicon-On-Insulator nMOSFETs with Tensile Strained High Carbon Content Si1-yCy Channel”, 2006, ECS 210th Meeting, Abstract 1033. |
Ernst, T et al., “Nanoscaled MOSFET Transistors on Strained Si, SiGe, Ge Layers: Some Integration and Electrical Properties Features”, 2006, ECS Trans. 2006, vol. 3, Issue 7, pp. 947-961. |
Goesele, U et al., Diffusion Engineering by Carbon in Silicon, 2000, Mat. Res. Soc. Symp. vol. 610. |
Hokazono, A et al., “Steep Channel & Halo Profiles Utilizing Boron-Diffusion-Barrier Layers (Si:C) for 32 nm Node and Beyond”, 2008, 2008 Symposium on VLSI Technology Digest of Technical Papers, pp. 112-113. |
Hokazono, A et al., “Steep Channel Profiles in n/pMOS Controlled by Boron-Doped Si:C Layers for Continual Bulk-CMOS Scaling”, 2009, IEDM09-676 Symposium, pp. 29.1.1-29.1.4. |
Holland, OW and Thomas, DK “A Method to Improve Activation of Implanted Dopants in SiC”, 2001, Oak Ridge National Laboratory, Oak Ridge, TN. |
Kotaki, H., et al., “Novel Bulk Dynamic Threshold Voltage MOSFET (B-DTMOS) with Advanced Isolation (SITOS) and Gate to Shallow-Well Contact (SSS-C) Processes for Ultra Low Power Dual Gate CMOS”, 1996, IEDM 96, pp. 459-462. |
Lavéant, P. “Incorporation, Diffusion and Agglomeration of Carbon in Silicon”, 2002, Solid State Phenomena, vols. 82-84, pp. 189-194. |
Noda, K et al., “A 0.1-μm Delta-Doped MOSFET Fabricated with Post-Low-Energy Implanting Selective Epitaxy”, Apr. 1998, IEEE Transactions on Electron Devices, vol. 45, No. 4, pp. 809-814. |
Ohguro, T et al., “An 0.18-μm CMOS for Mixed Digital and Analog Aplications with Zero-Volt-Vth Epitaxial-Channel MOSFET's”, Jul. 1999, IEEE Transactions on Electron Devices, vol. 46, No. 7, pp. 1378-1383. |
Pinacho, R et al., “Carbon in Silicon: Modeling of Diffusion and Clustering Mechanisms”, Aug. 2002, Journal of Applied Physics, vol. 92, No. 3, pp. 1582-1588. |
Robertson, LS et al., “The Effect of Impurities on Diffusion and Activation of Ion Implanted Boron in Silicon”, 2000, Mat. Res. Soc. Symp. vol. 610. |
Scholz, R et al., “Carbon-Induced Undersaturation of Silicon Self-Interstitials”, Jan. 1998, Appl. Phys. Lett. 72(2), pp. 200-202. |
Scholz, RF et al., “The Contribution of Vacancies to Carbon Out-Diffusion in Silicon”, Jan. 1999,Appl. Phys. Lett., vol. 74, No. 3, pp. 392-394. |
Stolk, PA et al., “Physical Mechanisms of Transient Enhanced Dopant Diffusion in Ion-Implanted Silicon”, May 1997, J. Appl. Phys. 81(9), pp. 6031-6050. |
Thompson, S et al., “MOS Scaling: Transistor Challenges for the 21st Century”, 1998, Intel Technology Journal Q3′ 1998, pp. 1-19. |
Wann, C. et al., “Channel Profile Optimization and Device Design for Low-Power High-Performance Dynamic-Threshold MOSFET”, 1996, IEDM 96, pp. 113-116. |
Werner, P et al., “Carbon Diffusion in Silicon”, Oct. 1998, Applied Physics Letters, vol. 73, No. 17, pp. 2465-2467. |
Yan, Ran-Hong et al., “Scaling the Si MOSFET: From Bulk to SOI to Bulk”, Jul. 1992, IEEE Transactions on Electron Devices, vol. 39, No. 7. |
Komaragiri, R. et al., “Depletion-Free Poly Gate Electrode Architecture for Sub 100 Nanometer CMOS Devices with High-K Gate Dielectrics”, IEEE IEDM Tech Dig., San Francisco CA, 833-836, Dec. 13-15, 2004. |
Samsudin, K et al., Integrating Intrinsic Parameter Fluctuation Description into BSIMSOI to Forecast sub-15 nm UTB SOI based 6T SRAM Operation, Solid-State Electronics (50), pp. 86-93. |
Wong, H et al., “Nanoscale CMOS”, Proceedings of the IEEE, Vo. 87, No. 4, pp. 537-570. |
Machine Translation of KR 10-0794094 Submitted herewith. |