Patent Grant
11205497
The present disclosure relates generally to semiconductor memory apparatuses and methods, and more particularly, to apparatuses and methods related to performing comparison operations in a memory.
Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.
Electronic systems often include a number of processing resources (e.g., one or more processors), which may retrieve and execute instructions and store the results of the executed instructions to a suitable location. A processor can comprise a number of functional units (e.g., herein referred to as functional unit circuitry (FUC)) such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and/or a combinatorial logic block, for example, which can execute instructions to perform logical operations such as AND, OR, NOT, NAND, NOR, and XOR logical operations on data (e.g., one or more operands).
A number of components in an electronic system may be involved in providing instructions to the functional unit circuitry for execution. The instructions may be generated, for instance, by a processing resource such as a controller and/or host processor. Data (e.g., the operands on which the instructions will be executed to perform the logical operations) may be stored in a memory array that is accessible by the FUC. The instructions and/or data may be retrieved from the memory array and sequenced and/or buffered before the FUC begins to execute instructions on the data. Furthermore, as different types of operations may be executed in one or multiple clock cycles through the FUC, intermediate results of the operations and/or data may also be sequenced and/or buffered.
In many instances, the processing resources (e.g., processor and/or associated FUC) may be external to the memory array, and data can be accessed (e.g., via a bus between the processing resources and the memory array) to execute instructions. Data can be moved from the memory array to registers external to the memory array via a bus.
The present disclosure includes apparatuses and methods related to performing comparison operations in a memory. As used herein, a comparison operation includes comparing vectors. A comparison operation can be performed on a first element (e.g., first vector) and a second element (e.g., second vector). An element can be stored in a group memory cells coupled to an access line. For example, a first group of memory cells coupled to a first access line can be configured to store a first element. A second group of memory cells coupled to a second access line can be configured to store a second element. The comparison operation can compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.
As used herein, a first element and a second element can be numerical values that are compared to (e.g., against) each other. That is, a first value can be compared to a second value and/or the second value can be compared to the first value. A comparison operation can be used to determine whether the first value is greater than the second value, whether the second value is greater than the first value, and/or whether the first value is equal to the second value.
In a number of examples, an element can represent an object and/or other construct, which may be represented by a bit-vector. As an example, a comparison operation can be performed to compare objects by comparing the bit-vectors that represent the respective objects.
A number of embodiments of the present disclosure can provide a reduction of the number of computations and/or time involved in performing a number of comparison operations (e.g., compare functions) relative to previous approaches. For instance, the number of computations and/or the time can be reduced due to an ability to perform various portions of the number of comparison operations in parallel in throughput (e.g., simultaneously). Performing a number of comparison operations as described herein can also reduce power consumption as compared to previous approaches. In accordance with a number of embodiments, a comparison operation can be performed on elements (e.g., data in the form of bit-vectors stored in an array) without transferring data out of the memory array and/or sensing circuitry via a bus (e.g., data bus, address bus, control bus, etc.), which can reduce the time and/or power needed to transfer data to a host in order to perform the comparison operation. Also, the result from the comparison operation can be formatted as a two bit-vectors. The two bit-vectors can incorporate greater than and less than results. The two bit-vectors can be provided to other single instruction multiple data (SIMD) operations (e.g., bit-vector division) and/or advanced pattern search applications in the form of masks. A comparison operation can involve performing a number of logical operations (e.g., AND operations, OR operations, SHIFT operations, INVERT operations, and BLOCKOR operations etc.). However, embodiments are not limited to these examples. As used herein SIMD operations is defined as performing a same operation on multiple elements in parallel (e.g., simultaneously).
In various previous approaches, elements (e.g., a first data value and a second data value) to be compared may be transferred from the array and sensing circuitry to a number of registers via a bus comprising input/output (I/O) lines. The number of registers can be used by a processing resource such as a processor, microprocessor, and/or compute engine, which may comprise ALU circuitry and/or other functional unit circuitry configured to perform the appropriate logical operations. However, often only a single comparison function can be performed by the ALU circuitry, and transferring data to/from memory from/to registers via a bus can involve significant power consumption and time requirements. Even if the processing resource is located on a same chip as the memory array, significant power can be consumed in moving data out of the array to the compute circuitry (e.g., ALU), which can involve performing a sense line address access (e.g., firing of a column decode signal) in order to transfer data from sense lines onto I/O lines, moving the data to the array periphery, and providing the data to a register in association with performing a comparison operation, for instance.
In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, the designators “F,” “M,” “N,” “P,” “R,” “S,” “U,” “V,” “X,” and “W,” particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included. As used herein, “a number of” a particular thing can refer to one or more of such things (e.g., a number of memory arrays can refer to one or more memory arrays).
The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 130 may reference element “30” in
System 100 includes a host 110 coupled to memory device 160, which includes a memory array 130. Host 110 can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, or a memory card reader, among various other types of hosts. Host 110 can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The system 100 can include separate integrated circuits or both the host 110 and the memory device 160 can be on the same integrated circuit. The system 100 can be, for instance, a server system and/or a high performance computing (HPC) system and/or a portion thereof. Although the example shown in
For clarity, the system 100 has been simplified to focus on features with particular relevance to the present disclosure. The memory array 130 can be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and/or NOR flash array, for instance. The array 130 can comprise memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digit lines or data lines). Although a single array 130 is shown in
The memory device 160 includes address circuitry 142 to latch address signals provided over an I/O bus 156 (e.g., a data bus) through I/O circuitry 144. Address signals are received and decoded by a row decoder 146 and a column decoder 152 to access the memory array 130. Data can be read from memory array 130 by sensing voltage and/or current changes on the sense lines using sensing circuitry 150. The sensing circuitry 150 can read and latch a page (e.g., row) of data from the memory array 130. The I/O circuitry 144 can be used for bi-directional data communication with host 110 over the I/O bus 156. The write circuitry 148 is used to write data to the memory array 130.
Control circuitry 140 decodes signals provided by control bus 154 from the host 110. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control operations performed on the memory array 130, including data read, data write, and data erase operations. In various embodiments, the control circuitry 140 is responsible for executing instructions from the host 110. The control circuitry 140 can be a state machine, a sequencer, or some other type of controller.
An example of the sensing circuitry 150 is described further below in association with
In various previous approaches, data associated with a comparison operation, for instance, would be read from memory via sensing circuitry and provided to an external ALU. The external ALU circuitry would perform the comparison functions using the elements (which may be referred to as operands or inputs) and the result could be transferred back to the array via the local I/O lines. In contrast, in a number of embodiments of the present disclosure, sensing circuitry (e.g., 150) is configured to perform a comparison operation on data stored in memory cells in memory array 130 and store the result back to the array 130 without enabling a local I/O line coupled to the sensing circuitry.
As such, in a number of embodiments, registers and/or an ALU external to array 130 and sensing circuitry 150 may not be needed to perform the comparison function as the sensing circuitry 150 can perform the appropriate computations involved in performing the comparison function using the address space of memory array 130. Additionally, the comparison function can be performed without the use of an external processing resource.
Memory cells can be coupled to different data lines and/or word lines. For example, a first source/drain region of a transistor 202-1 can be coupled to data line 205-1 (D), a second source/drain region of transistor 202-1 can be coupled to capacitor 203-1, and a gate of a transistor 202-1 can be coupled to word line 204-X. A first source/drain region of a transistor 202-2 can be coupled to data line 205-2 (D_), a second source/drain region of transistor 202-2 can be coupled to capacitor 203-2, and a gate of a transistor 202-2 can be coupled to word line 204-Y. The cell plate, as shown in
The memory array 230 is coupled to sensing circuitry 250 in accordance with a number of embodiments of the present disclosure. In this example, the sensing circuitry 250 comprises a sense amplifier 206 and a compute component 231 corresponding to respective columns of memory cells (e.g., coupled to respective pairs of complementary data lines). The sense amplifier 206 can comprise a cross coupled latch, which can be referred to herein as a primary latch. The sense amplifier 206 can be configured, for example, as described with respect to
In the example illustrated in
In this example, data line D 205-1 can be coupled to a first source/drain region of transistors 216-1 and 239-1, as well as to a first source/drain region of load/pass transistor 218-1. Data line D_ 205-2 can be coupled to a first source/drain region of transistors 216-2 and 239-2, as well as to a first source/drain region of load/pass transistor 218-2.
The gates of load/pass transistor 218-1 and 218-2 can be commonly coupled to a LOAD control signal, or respectively coupled to a PASSD/PASSDB control signal, as discussed further below. A second source/drain region of load/pass transistor 218-1 can be directly coupled to the gates of transistors 216-1 and 239-2. A second source/drain region of load/pass transistor 218-2 can be directly coupled to the gates of transistors 216-2 and 239-1.
A second source/drain region of transistor 216-1 can be directly coupled to a first source/drain region of pull-down transistor 214-1. A second source/drain region of transistor 239-1 can be directly coupled to a first source/drain region of pull-down transistor 207-1. A second source/drain region of transistor 216-2 can be directly coupled to a first source/drain region of pull-down transistor 214-2. A second source/drain region of transistor 239-2 can be directly coupled to a first source/drain region of pull-down transistor 207-2. A second source/drain region of each of pull-down transistors 207-1, 207-2, 214-1, and 214-2 can be commonly coupled together to a reference voltage line 291-1 (e.g., ground (GND)). A gate of pull-down transistor 207-1 can be coupled to an AND control signal line, a gate of pull-down transistor 214-1 can be coupled to an ANDinv control signal line 213-1, a gate of pull-down transistor 214-2 can be coupled to an ORinv control signal line 213-2, and a gate of pull-down transistor 207-2 can be coupled to an OR control signal line.
The gate of transistor 239-1 can be referred to as node S1, and the gate of transistor 239-2 can be referred to as node S2. The circuit shown in
The configuration of compute component 231 shown in
Inverting transistors can pull-down a respective data line in performing certain logical operations. For example, transistor 216-1 (having a gate coupled to S2 of the dynamic latch) in series with transistor 214-1 (having a gate coupled to an ANDinv control signal line 213-1) can be operated to pull-down data line 205-1 (D), and transistor 216-2 (having a gate coupled to S1 of the dynamic latch) in series with transistor 214-2 (having a gate coupled to an ANDinv control signal line 213-2) can be operated to pull-down data line 205-2 (D_).
The latch 264 can be controllably enabled by coupling to an active negative control signal line 212-1 (ACCUMB) and an active positive control signal line 212-2 (ACCUM) rather than be configured to be continuously enabled by coupling to ground and VDD. In various embodiments, load/pass transistors 208-1 and 208-2 can each having a gate coupled to one of a LOAD control signal or a PASSD/PASSDB control signal.
According to some embodiments, the gates of load/pass transistors 218-1 and 218-2 can be commonly coupled to a LOAD control signal. In the configuration where the gates of load/pass transistors 218-1 and 218-2 are commonly coupled to the LOAD control signal, transistors 218-1 and 218-2 can be load transistors. Activating the LOAD control signal causes the load transistors to conduct, and thereby load complementary data onto nodes S1 and S2. The LOAD control signal can be elevated to a voltage greater than VDD to pass a full VDD level to S1/S2. However, the LOAD control signal need not be elevated to a voltage greater than VDD is optional, and functionality of the circuit shown in
According to some embodiments, the gate of load/pass transistor 218-1 can be coupled to a PASSD control signal, and the gate of load/pass transistor 218-2 can be coupled to a PASSDb control signal. In the configuration where the gates of transistors 218-1 and 218-2 are respectively coupled to one of the PASSD and PASSDb control signals, transistors 218-1 and 218-2 can be pass transistors. Pass transistors can be operated differently (e.g., at different times and/or under different voltage/current conditions) than load transistors. As such, the configuration of pass transistors can be different than the configuration of load transistors.
Load transistors are constructed to handle loading associated with coupling data lines to the local dynamic nodes S1 and S2, for example. Pass transistors are constructed to handle heavier loading associated with coupling data lines to an adjacent accumulator (e.g., through the shift circuitry 223, as shown in
In a number of embodiments, the compute component 231, including the latch 264, can comprise a number of transistors formed on pitch with the transistors of the corresponding memory cells of an array (e.g., array 230 shown in
The voltages or currents on the respective data lines D and D_ can be provided to the respective latch inputs 217-1 and 217-2 of the cross coupled latch 264 (e.g., the input of the secondary latch). In this example, the latch input 217-1 is coupled to a first source/drain region of transistors 208-1 and 209-1 as well as to the gates of transistors 208-2 and 209-2. Similarly, the latch input 217-2 can be coupled to a first source/drain region of transistors 208-2 and 209-2 as well as to the gates of transistors 208-1 and 209-1.
In this example, a second source/drain region of transistor 209-1 and 209-2 is commonly coupled to a negative control signal line 212-1 (e.g., ground (GND) or ACCUMB control signal similar to control signal RnIF shown in
The enabled cross coupled latch 264 operates to amplify a differential voltage between latch input 217-1 (e.g., first common node) and latch input 217-2 (e.g., second common node) such that latch input 217-1 is driven to either the activated positive control signal voltage (e.g., VDD) or the activated negative control signal voltage (e.g., ground), and latch input 217-2 is driven to the other of the activated positive control signal voltage (e.g., VDD) or the activated negative control signal voltage (e.g., ground).
In a number of embodiments, a sense amplifier (e.g., 206) can comprise a number of transistors formed on pitch with the transistors of the corresponding compute component 231 and/or the memory cells of an array (e.g., 230 shown in
The voltages or currents on the respective data lines D and D_ can be provided to the respective latch inputs 233-1 and 233-2 of the cross coupled latch 215 (e.g., the input of the secondary latch). In this example, the latch input 233-1 is coupled to a first source/drain region of transistors 227-1 and 229-1 as well as to the gates of transistors 227-2 and 229-2. Similarly, the latch input 233-2 can be coupled to a first source/drain region of transistors 227-2 and 229-2 as well as to the gates of transistors 227-1 and 229-1. The compute component 233 (e.g., accumulator) can be coupled to latch inputs 233-1 and 233-2 of the cross coupled latch 215 as shown; however, embodiments are not limited to the example shown in
In this example, a second source/drain region of transistor 227-1 and 227-2 is commonly coupled to an active negative control signal 228 (RnIF). A second source/drain region of transistors 229-1 and 229-2 is commonly coupled to an active positive control signal 265 (ACT). The ACT signal 265 can be a supply voltage (e.g., VDD) and the RnIF signal can be a reference voltage (e.g., ground). Activating signals 228 and 265 enables the cross coupled latch 215.
The enabled cross coupled latch 215 operates to amplify a differential voltage between latch input 233-1 (e.g., first common node) and latch input 233-2 (e.g., second common node) such that latch input 233-1 is driven to one of the ACT signal voltage and the RnIF signal voltage (e.g., to one of VDD and ground), and latch input 233-2 is driven to the other of the ACT signal voltage and the RnIF signal voltage.
The sense amplifier 206 can also include circuitry configured to equilibrate the data lines D and D_ (e.g., in association with preparing the sense amplifier for a sensing operation). In this example, the equilibration circuitry comprises a transistor 224 having a first source/drain region coupled to a first source/drain region of transistor 225-1 and data line D 205-1. A second source/drain region of transistor 224 can be coupled to a first source/drain region of transistor 225-2 and data line D_ 205-2. A gate of transistor 224 can be coupled to gates of transistors 225-1 and 225-2.
The second source drain regions of transistors 225-1 and 225-2 are coupled to an equilibration voltage 238 (e.g., VDD/2), which can be equal to VDD/2, where VDD is a supply voltage associated with the array. The gates of transistors 224, 225-1, and 225-2 can be coupled to control signal 225 (EQ). As such, activating EQ enables the transistors 224, 225-1, and 225-2, which effectively shorts data line D to data line D_ such that the data lines D and D_ are equilibrated to equilibration voltage VDD/2. According to various embodiments of the present disclosure, a number of logical operations can be performed using the sense amplifier, and storing the result in the compute component (e.g., accumulator).
As shown in
In the example illustrated in
Although the shift circuitry 223 shown in
Embodiments of the present disclosure are not limited to the configuration of shift circuitry 223 shown in
Although not shown in
The sensing circuitry 250 can be operated in several modes to perform logical operations, including a first mode in which a result of the logical operation is initially stored in the sense amplifier 206, and a second mode in which a result of the logical operation is initially stored in the compute component 231. Operation of the sensing circuitry 250 in the first mode is described below with respect to
As described further below, the sense amplifier 206 can, in conjunction with the compute component 231, be operated to perform various logical operations using data from an array as input. In a number of embodiments, the result of a logical operation can be stored back to the array without transferring the data via a data line address access (e.g., without firing a column decode signal such that data is transferred to circuitry external from the array and sensing circuitry via local I/O lines). As such, a number of embodiments of the present disclosure can enable performing logical operations and compute functions associated therewith using less power than various previous approaches. Additionally, since a number of embodiments eliminate the need to transfer data across I/O lines in order to perform compute functions (e.g., between memory and discrete processor), a number of embodiments can enable an increased parallel processing capability as compared to previous approaches.
Each column of memory cells can be coupled to sensing circuitry (e.g., sensing circuitry 150 shown in
The sensing circuitry (e.g., compute components 331 and sense amplifiers 306) is configured to perform a comparison operation in accordance with a number of embodiments described herein. The example given in
The bit-vectors 476, 478, 480, and 482 can be stored in respective groups of memory cells coupled to particular access lines, which may be referred to as temporary storage rows 470 (e.g., rows that store data that may be updated during various phases of a comparison operation). The bit-vectors 488, 490, 492, and 494 can be referred to as vector arguments 472.
The scalar integer variables 484 (destc) and 486 (destpc) can be stored in memory (e.g., registers) associated with control circuitry 140 in
In
In the examples used herein, bit-vector values may include commas and/or spaces for ease of reference. For instance, a bit-vector represented in hexadecimal notation as [03, 09, 02, 0c] can correspond to four 8-bit wide vector elements, with the four elements separated by a respective comma and space. However, the same bit-vector can be represented as [03 09 02 0c] (e.g., without commas) and/or as [0309020c] (e.g., without commas and without spaces).
In
In the example shown in
For example, elements in a first element pair (e.g., 03 and 07 from srca 488 and srcb 490, respectively) are compared in a first comparison operation. Elements in a second element pair (e.g., 09 and 05 from srca 488 and srcb 490, respectively) are compared in a second comparison operation. Elements in a third element pair (e.g., 02 and 08 from srca 488 and srcb 490, respectively) are compared in a third comparison operation, and elements in a fourth element pair (e.g., 0c and 0c from srca 488 and srcb 490, respectively) are compared in a fourth comparison operation.
A first group of memory cells that store srca 488 can be cells coupled to a particular access line (e.g., 304-0 in
The four elements of srca 488 can be stored in the first group of memory cells. For example, a first element (e.g., 03) of srca 488 can be stored in memory cells that are coupled to access line 304-0 and sense lines 305-0 to 305-7 in
The four elements of srcb 490 can be stored in the second group of memory cells. For example, a first element (e.g., 07) of srcb 490 can be stored in memory cells that are coupled to access line 304-1 and sense lines 305-0 to 305-7, a second element (e.g., 05) can be stored in memory cells that are coupled to access line 304-1 and sense lines 305-8 to 305-15, a third element (e.g., 08) can be stored in memory cells that are coupled to access line 304-1 and sense lines 305-16 to 305-23, and a fourth element (e.g., 0c) can be stored in memory cells that are coupled to access line 304-1 and sense lines 305-34 to 305-31.
Row_Mask 476, Row_LowAct 478, Row_Retained 480, and Row_Object 482 include bit-vectors that are stored in a plurality of groups of memory cells. For instance, Row_Mask 476, Row_LowAct 478, Row_Retained 480, and Row_Object 482 can be stored in memory cells that are coupled to respective access lines 304-2 to 304-5 and to sense lines 305-0 to 305-31. Destc 484 and destpc 486 include scalar integers that are used in the comparison operation.
In this example, the first element in scra 488 has a decimal value of 3, which can be represented by bit-vector [0000 0011] with 8-bit width. The particular bits of the bit-vector can be stored in the cells coupled to access line 304-0 and to the corresponding respective sense lines 305-0 to 305-7 (e.g., the most significant bit (MSB) of the bit-vector can be stored in the ROW 0 cell coupled to sense line 305-0, the next least significant bit (LSB) can be stored in the ROW 0 cell coupled to sense line 305-1, . . . , and the LSB can be stored in the ROW 0 cell coupled to sense line 305-7) in
However, embodiments are not limited to this example. For instance, elements to be compared in accordance with embodiments described herein can be represented by bit-vectors having a width other than 8-bits. Also, a plurality of elements can be represented by a particular bit-vector. For instance, a first 64-bit wide bit-vector could represent four elements each represented by a 16-bit wide bit-vector and could be stored in cells coupled to access line 304-0 (and to sense lines 305-0 to 305-63), and a second 64-bit wide bit-vector could represent four elements each represented by a 16-bit wide bit vector and could be stored in cells coupled to access line 304-1 (and to sense lines 305-0 to 305-63). The four elements represented by the first 64-bit wide bit-vector can be compared to the respective four elements represented by the second 64-bit wide bit-vector in accordance with embodiments described herein.
In a number of embodiments, the result of a comparison operation can be stored in a third group of memory cells, which can be cells coupled to a number of particular access lines (e.g., 304-0 to 304-R in
The third group of memory cells can also comprise a first number of memory cells coupled to a particular access line and a second number of memory cells coupled to a different particular access line. The first and second numbers of memory cells can store two different bit-vectors that together indicate the results of the comparison operation (e.g., in a 2-bit horizontal vector row). For example, a first result bit-vector can be stored in the first number of memory cells and a second result bit-vector can be stored in the second number of memory cells. Particular bit patterns of the first and second result bit-vectors can indicate whether the first element in srca 488 is greater than the first element in srcb 490, whether the first element in srcb 490 is greater than the first element in srca 488, and/or whether the first element in srca 488 is equal to the first element in srcb 490.
For instance, as described further below, responsive to the first element in srca 488 being greater than the first element in srcb 490, the first result bit-vector can be a first bit pattern (e.g., [1111 1111]) and the second result bit-vector can be a second bit pattern (e.g., [0000 0000]), and responsive to the first element in srcb 490 being greater than the first element in srca 488, the first result bit-vector can be the second bit pattern (e.g., [0000 0000]) and the second result bit-vector can be the first bit pattern (e.g., [1111 1111]). Responsive to the first element in srcb 488 and the first element in srca 490 being equal, the first result bit-vector and the second result bit-vector can be the same bit pattern (e.g., [0000 0000] or [1111 1111]).
As an example, the first result bit-vector can be stored in the cells coupled to access line 304-2 and to sense lines 305-0 to 305-7 shown in
It is noted that a determination of whether a first element is greater than a second element may include a determination that the first element is not less than the second element, but may not identify whether the first element is equal to the second element. That is, if the first element is not greater than the second element, then the second element may be greater than the first element or the first element may be equal to the second element.
Accordingly, a comparison operation can also include a determination of whether the second element is greater than the first element, which may include a determination that the second element is not less than the first element. However, a determination that the second element is not less than the first element may not identify whether the second element is equal to the first element. In a number of examples, performing a comparison operation on a first element and a second element can include performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line. The number of AND operations, OR operations, INVERT operations, and SHIFT operations can be performed using sensing circuitry on pitch with memory cells corresponding to respective columns of complementary sense lines.
The below pseudocode represents instructions executable to perform a number of comparison operations in a memory in accordance with a number of embodiments of the present disclosure. The example pseudocode is referenced using reference numbers 1-8, which correspond to the respective reference numbers 1-8 shown in column 496 of the table shown in
1. Load srca, srcb.
2. Determine element count in sub array for the vector length.
3. Obtain all Temp Rows.
4. Find MSB and store in Comp_Comp, Row_Mask, Row_Retained.
5. Find MSB by shifting right with fixed vector for each length in Comp_Comp.
6. Right Shift for fixed length and store in Row_Object.
7. For each Vector element:
7.a. Create Full Row_Mask for the element with bits enabled.
7.b Right Shift Row_Retained to the fixed length of the element.
7.c. Load srca in Comp_Comp
7.d. Do Comp_Comp AND operation with srcb
7.e. Store Inverse of Comp_Comp in Row_LowAct
7.f Load Row_LowAct in Comp_Comp
7.g. Do Comp_Comp AND operation with srca
7.h. Do Comp_Comp AND operation with Row_Mask
7.i. Do Comp_Comp OR operation with dest
7.j. Store Comp_Comp in dest
7.k. Load Row_LowAct in Comp_Comp
7.l. Do Comp_Comp AND operation with srcb
7.m. Do Comp_Comp AND operation with Row_Mask
7.n. Do Comp_Comp OR operation with dest+1
7.o. Store Comp_Comp in dest+1
7.p. Load dest in Comp_Comp
7.q. Do Comp_Comp AND operation with Row_Mask
7.r. Store Comp_Comp in Row_LowAct
7.s. For Vector fixed width:
7.t. Load dest+1 in Comp_Comp
7.u. Do Comp_Comp AND operation with Row_Mask
7.v. Store Comp_Comp in Row_LowAct
7.w. For Vector fixed width:
7.x. If destc>destpc
7.y. else If destpc>destc
7.z. else
For purposes of discussion, the above pseudocode will be divided into a setup phase and a comparison phase. The pseudocode referenced by reference numbers 1-6 can correspond to the setup phase. In a number of embodiments, the setup phase can be performed simultaneously for all of the comparison operations.
The pseudocode referenced by reference number 7 (e.g., 7.a-7.z.i) can correspond to the comparison phase. The comparison phase can further be divided into a determination phase and a results phase. The determination phase can correspond to the pseudocode reference by reference numbers 7.a. to 7.w.vi. The determination phase can be executed to determine whether the first element is greater than the second element in each of the element pairs, whether the second element is greater than the first element in each of the element pairs, and/or whether the first element is equal to the second element in each of the element pairs. The values of a number of bit-vectors during execution of an example comparison phase are shown in
The pseudocode corresponding to the results phase can be executed to store the results of the comparison operation. The results phase can comprise the pseudocode referenced by reference numbers 7.x. to 7.z.i. In a number of examples, the results of the comparison operation can be stored in an array (e.g., array 330 in
The comparison phase can include performing a number of iterations of operations. For example, the pseudocode corresponding to reference number 7 (e.g., “For each Vector element:”) can represent a “For” loop associated with iterating through a number of logical operations for each vector element pair of a number of vector element pairs being compared.
A first iteration of a “For” loop corresponding to reference number 7 can be performed to compare a first element to a second element of a first element pair, while subsequent iterations of the “For” loop can be performed to compare additional element pairs. In a number of examples, each iteration of the “For” loop corresponding to reference number 7 can be performed sequentially. Performing each iteration of the “For” loop sequentially can include concluding each iteration of the “For” loop before the next iteration of the “For” loop begins.
The pseudocode corresponding to reference number 1 (e.g., “Load srca, srcb”) is associated with storing srca 488 and srcb 490 into the array 330 in
The pseudocode corresponding to reference number 2 (e.g., “Determine element count in sub array for the vector length”), is associated with determining the element count of srca 488 and srcb 490. Determining the count of elements in srca 488 and srcb 490 can include determining the number of element pairs to be compared. At reference number 2, a vector length is also determined. Although not shown in
As an example, the element count can be determined based on the width of srca 488 and srcb 490 and on the element width (e.g., the number of bits used to represent each element). Given that srca 488 and srcb 490 are each 32-bit wide bit-vectors (e.g., stored in memory cells that are coupled to 32 columns in memory) and that each element is represented by eight bits, each of srca 488 and srcb 490 comprise four elements (e.g., 32/8=4).
In a number of examples, the number of bits used to represent each element (e.g., the element width) can be a parameter provided by a host and/or user, for instance. Also, in a number of embodiments, the element count of srca 488 and/or srcb 490 and/or the vector width corresponding to srca 488 and srcb 490 can be provided by a host and/or user as a parameter. As such, in a number of examples, the element width of the bit-vectors comprising srca 488 and/or srcb 490 can be determined based on the vector width of srca 488 and srcb 490 and on the element count. For instance, given a vector width of 32 bits and an element count of 4, the element width would be 8 bits (e.g., 32/4=8).
The pseudocode referenced at reference number 3 (e.g., Obtain all Temp Rows) corresponds to initializing a number of groups of memory cells for use as temporary storage rows during a comparison operation. That is, the number of groups of memory cells can be groups of cells coupled to respective access lines (e.g., rows) and can be used to temporarily store data (e.g., as temporary storage) in association with performing the comparison operation. For example, a first group of memory cells can store a bit-vector referred to as “Row_Mask”, a second group of memory cells can store a bit-vector referred to as “Row_LowAct”, a third group of memory cells can store a bit-vector referred to as “Row_Retained”, a fourth group of memory cells can store a bit-vector referred to as “Row_Object”, a fifth group of memory cells can store a bit-vector referred to as “destc”, and a sixth group of memory cells can store a bit-vector referred to as “destpc”. Embodiments are not limited to a particular number of temporary storage rows. In a number of examples, each element pair that is being compared (e.g., a first element of srca and a first element of srcb) can be associated with a different number of bit-vectors corresponding to the rows that store Row_Mask 476, Row_LowAct 478, Row_Retained 480, Row_Object 482, destc 484, and/or destpc 486. In a number of examples, the bit-vectors corresponding to the rows that store temporary data are stored in memory cells coupled to the same sense lines as the element pairs that are being compared.
For instance, Row_Mask 476 can be used to identify and/or isolate elements that are being compared and/or bits of the bit-vectors corresponding to the elements that are being compared. Row_LowAct 478 can be used to identify the elements of srca 488 and srcb 490 that will be compared in the comparison operation. Row_Object 482 can be used to identify a least significant bit in each element. Destc 484 and destpc 486 can be used to identify the differences in srca 488 and srcb 490 (e.g., the respective bit positions having different binary values).
The groups of memory cells corresponding to temporary storage rows 470 may be oriented within memory 330 in a manner that facilitates performance of the comparison operation on the element pairs. For example, a plurality of groups of memory cells each storing the bit-vectors corresponding to respective temporary storage rows can be coupled to sense lines 305-0 to 305-31 in
Initiating Row_Mask 476, Row_LowAct 478, Row_Retained 480, and Row_Object 482 can include storing the bit-vector [00000000] in the plurality of groups of memory cells that store Row_Mask 476, Row_LowAct 478, Row_Retained 480, and Row_Object 482.
The pseudocode referenced at reference number 4 (e.g., “Find MSB and store in Comp_Comp, Row_Mask, Row_Retained”) is associated with determining the most significant bit (MSB) in srca 488 and/or srcb 490 and storing a bit-vector indicating the MSB in particular groups of memory cells. The bit pattern indicating the most significant bit can be stored (e.g., as a bit-vector) in a group of memory cells used to store Row_Mask 476 and in a group of memory cells used to store Row_Retained 480. The bit pattern indicating the most significant bit can also be stored (e.g., as a latched bit-vector) in sensing circuitry (e.g., compute components 331 and/or sense amplifiers 306 in
The pseudocode referenced at reference number 5 (e.g., Find MSB by shifting right with fixed vector for each length in Comp_Comp) is associated with determining a bit-vector that can indicate a MSB corresponding to each of a number of elements represented by srca 488 and/or srcb 490. The bit-vector used to indicate the MSBs corresponding to the number of elements can be determined by performing a number of logical operations (e.g., a number of iterations of SHIFT operations and OR operations) on the bit-vector stored in the compute components (e.g., 331-0 to 331-31 in
The pseudocode referenced at reference number 6 (e.g., Right Shift for fixed length and store in Row_Object) is associated with determining a bit-vector that can indicate a LSB corresponding to each of a number of elements represented by srca 488 and/or srcb 490. A number of SHIFT operations can be performed on Comp_Comp 431 (e.g., the result of the SHIFT and OR operations performed in reference number 5) to identify the LSB corresponding to each of the number of elements. For example, if a binary bit-vector [1000 0000, 1000 0000, 1000 0000] identifies a most significant bit for each element in srca 488 and/or srcb 490, then the bit-vector [000 0001, 0000 0001, 0000 0001] can identify the least significant bit for each bit-vector that represents an element in srca 488 and/or srcb 490. The least significant bit for each element in srca 488 bit-vector and/or srcb 490 can be identified by performing a right SHIFT operation a plurality of times equal to a vector length. The hexadecimal bit-vector [01010101] is stored in a group of memory cells that store Row_Object 482. The bit-vector [01010101] bit-vector identifies (e.g., with a “1”) the least significant bit in each of the elements.
The pseudocode referenced at reference number 7 (e.g., For each Vector element), corresponds to a “For” loop described via the pseudocode referenced at reference numbers 7.a to 7.z.i. As such, the “For” loop corresponding to reference number 7 involves performing a number of iterations of operations. Each iteration of operations of the number of iterations of operations corresponds to a particular element pair being compared. For instance, a first iteration of operations shown as pseudocode 7.a to 7.z.i is performed in association with comparing the first element pair, a second iteration of operations shown as pseudocode 7.a to 7.z.i is performed in association with comparing the second element pair, etc.
At reference number 7.a (e.g., Create Full Row_Mask for the element with bits enabled), a full row mask is created. A full row mask is defined as a mask that includes a specific bit pattern for a particular element and/or a particular plurality of elements. The specific bit pattern can include all ones (e.g, “1”) or all zeros (e.g., “0”). For example, during a first iteration (e.g., an iteration corresponding to a first element pair) of the “For” loop associated with reference number 7.a, a binary bit-vector [1111 1111, 0000 0000, 0000 0000] (e.g., a hexadecimal bit-vector [ff000000]) is created and stored in a group of memory cells that store Row_Mask 476. Row_Mask 476 can be used to isolate an element in srca 488 and/or srcb 490 during a comparison operation. The bit-vector [ff000000] can also identify that a current comparison operation compares a first element from srca 488 and a first element from srcb 490. The full row mask can be created via a plurality of SHIFT operation that are performed on Row_Mask 476 and a plurality of OR operations that are performed on Comp_Comp 431 and Row_Mask 476.
At reference number 7.b (e.g., Right Shift Row_Retained to the fixed length of the element), Row_Retained 480 is stored in a group of compute components 331 in
At reference number 7.c (e.g., Load srca in Comp_Comp), srca 488 can be stored in sensing circuitry. For example, srca 488 (e.g., a hexadecimal bit-vector [0309020c]) can be stored in the compute components 331 and/or the sense amplifiers 306 in
At reference number 7.d (e.g., Do Comp_Comp AND operation with srcb), an AND operation can be performed on Comp_Comp 431 and srcb 490 that is stored in a group of memory cells coupled to access line 304-1. The AND operation can be performed to identify common bits with a value equal to one (1) between Comp_Comp 431 (e.g., srca 488) and srcb 490. The result (e.g., a hexadecimal bit-vector [0301000c]) of the AND operation can be stored in the sensing circuitry (e.g., compute components 331 and/or sense amplifier 306).
At reference number 7.e (e.g., Store Inverse of Comp_Comp in Row_LowAct), an INVERT operation can be performed on Comp_Comp 431 (e.g., hexidecimal bit-vector [0301000c] which is the results of the previous AND operation) to identify bits that are not shared between srca 488 and srcb 490. The result (e.g., bit-vector [fcfefff3]) of the INVERT operation can be stored in the group of memory cells that store Row_LowAct 478.
At reference number 7.f (e.g., Load Row_LowAct in Comp_Comp), Row_LowAct 478 (e.g., a bit-vector [fcfefff3]) is stored in the sensing circuitry. At reference number 7.g (e.g., Do Comp_Comp AND operation with srca), an AND operation is performed on Comp_Comp 431 (e.g., Row_LowAct 478) and srca 488. The AND operation can be performed on Comp_Comp 431 (e.g., a bit-vector [fcfefff3]) and srca 488 (e.g., a bit-vector [0309020c]) to identifies indexes of bits in srca 488 that have a value of one (1) and associated bits in srcb 490 that have a value of zero (0). The result (e.g., a bit-vector [00080200]) of the AND operation is stored in the sensing circuitry. The result identifies that a bit with an index, (e.g., given that a first index identifies a least significant bit) equal to four (4) in a second element in srca 488 has a one (1) value and that a bit with an index equal to four (4) in an associated element in srcb 490 has a zero (0) value. The result also identifies that a bit with an index, (e.g., given that a first index identifies a least significant bit) equal to two (2) in a third element in srca 488 has a one (1) value and that a bit with an index equal to two (2) in an associated element in srcb 490 has a zero (0) value. The results of the AND logical operation can be stored in the sensing circuitry.
At reference number 7.h (e.g., Do Comp_Comp AND operation with Row_Mask), an AND operation is performed on Comp_Comp 431 (e.g., a hexadecimal bit-vector [00080200]) and on Row_Mask 476 (e.g., a bit-vector [ff000000]) to isolate the identified indexes that are associated with a current comparison operation. The results (e.g., a bit-vector [00000000] bit-vector) of the AND operation can be stored in the sensing circuitry.
At reference number 7.i (e.g., Do Comp_Comp OR operation with dest), an OR operation is performed on Comp_Comp 431 (e.g., a hexadecimal bit-vector [00000000]) and dest 792 (e.g., a bit-vector [00000000]). The result (e.g., a bit-vector [00000000]) of the OR operation is stored in the sensing circuitry. At reference number 7.j (e.g., Store Comp_Comp in dest), Comp_Comp 431 (e.g., a bit-vector [00000000]) is stored in a group of memory cells that store dest 492.
At reference number 7.k (e.g., Load Row_LowAct in Comp_Comp), Row_LowAct 478 (e.g., a bit-vector [fcfefff3]) is stored in the sensing circuitry. At reference number 7.l (e.g., Do Comp_Comp AND operation with srcb), an AND operation is performed on a Comp_Comp 431 (e.g., a bit-vector [fcfefff3]) and on srcb 490 (e.g., a bit-vector [0705080c]). The AND operation is performed to identify indexes of bits in srcb 490 that have a value of one (1) and associated bits in srca 488 that have a value of zero (0). The result (e.g., a bit-vector [04040800]) is stored in the sensing circuitry.
At reference number 7.m (e.g., Do Comp_Comp AND operation with Row_Mask), an AND operation is performed on Comp_Comp 431 (e.g., a bit-vector [04040800]) and on Row_Mask 476 (e.g., a bit-vector [ff000000]) to isolate the identified indexes that are associated with a current comparison operation. The result (e.g., a bit-vector [04000000]) is stored in the sensing circuitry. At reference number 7.n (e.g., Do Comp_Comp OR operation with dest+1), an OR operation is performed on Comp_Comp 431 (e.g., a bit-vector [04000000]) and dest+1 494 (e.g., a bit-vector [00000000]). At reference number 7.o (e.g., Store Comp_Comp in dest+1), the result (e.g., a bit-vector [04000000]) of the OR operation is stored in the group of memory cells that store dest+1 494.
At reference number 7.p (e.g., Load dest in Comp_Comp), dest 492 (e.g., a bit-vector [00000000]) is stored in the sensing circuitry. At reference number 7.q (e.g., Do Comp_Comp AND operation with Row_Mask), an AND operation is performed on Comp_Comp 431 (e.g., a bit-vector [00000000]) and Row_Mask 476 (e.g., a bit-vector [FF000000]) to isolate the bits in Comp_Comp 431 that are associated with the current compare operation. The result of the AND operation is stored in the sensing circuitry. At reference number 7.r (e.g., Store Comp_Comp in Row_LowAct), Comp_Comp 431 (e.g., a bit-vector [00000000]) is stored in the group of memory cells that store Row_LowAct 478.
At reference number 7.s (For Vector fixed width), a “For” loop is executed. The “For” loop iterates through the indexes associated with an element width. A number of operations are performed (e.g., operations associated with reference number 7.s.i. to 7.s.vi.) for each index. The “For” loop iterations through the indexes associated with an element width. For example, if an element is represented by a bit-vector with eight bits (e.g., element width), then the “For” loop can iterate eight times, each iteration incrementing the index by one. During a first iteration of the “For” loop an index will have a value of one (1), during a second iteration of the “For” loop an index will have a value of two (2), . . . , and during an eight iteration of the “For” loop an index will have a value of eight (8). The “For” loop will conclude (e.g., break) after the eighth iteration.
At reference number 7.s.i (e.g., Do Comp_Comp AND operation with Row_Mask), an AND operation is performed on Comp_Comp (e.g., a bit-vector [00000000]) and Row_Mask 476 (e.g., a bit-vector [ff000000]). The results (e.g., a bit-vector [00000000]) of the AND operation is stored in the sensing circuitry. At reference number 7.s.ii (e.g., Store Comp_Comp in Row_LowAct), Comp_Comp 431 (e.g., a bit-vector [00000000]) is stored in the group of memory cells that store Row_LowAct 478.
At reference number 7.s.iii. (Do Comp_Comp AND operation with Row_Object), an AND operation is performed on Comp_Comp 431 (e.g., a bit-vector [00000000]) and on Row_Object 482 (e.g., a bit-vector [01010101]). The result (e.g., a bit-vector [00000000]) of the AND operation is stored in the sensing circuitry.
At reference number 7.s.iv. (e.g., Store return value of BLOCKOR operation into scalar integer destc), a BLOCKOR operation is performed on Comp_Comp 431. The result (e.g., [00000000]) of the BLOCKOR operation is stored in memory that is associated with the control circuitry and that store destc 484. As used herein, the BLOCKOR operation can be performed to determine whether one or more bits of a bit-vector stored in the sensing circuitry are a particular value (e.g., whether any of the bits stored in the sensing circuitry are a one “1” bit). The BLOCKOR operation can be performed using an I/O line 334 and a secondary sense amplifier 312.
The BLOCKOR operation is performed to determine a most significant bit index of bits in srca 488 that have a value of one (1) and associated bits in srcb 490 that have a value of zero (0). The result of the BLOCKOR operation is stored as an scalar integer memory that is associated with control circuitry and that stores destc 484. The BLOCKOR operation is performed on the bits of Comp_Comp that are associated with a number of indexes. The number of indexes are indexes that the “For” loop in reference number 7.s iterates. For example, the BLOCKOR operation is performed during each iteration of the “For” loop referenced in reference number 7.s and is only performed on the iterated indexes of the “For” loop. For example, during a first iteration of the “For” loop referenced in reference number 7.s the BLOCKOR operation is performed on the least significant bit in Comp_Comp 431. During the second iteration of the “For” loop reference in reference number 7.s the BLOCKOR operation is performed on two least significant bits (e.g., bits with an index equal to zero (0) and one (1) in Comp_Comp 431). During an eighth iteration of the “For” loop referenced in reference number 7.s the BLOCKOR operation is performed on all the bits in Comp_Comp 431.
In a number of embodiments, a BLOCKOR operation can be performed in association with determining if the memory cells coupled to one or more (e.g., any) particular sense line store a data pattern that matches the target data pattern. For example, knowing whether one or more matches to the target data pattern are stored in an array may be useful information, even without knowing which particular sense line(s) is coupled to cells storing the matching data pattern. In such instances, the determination of whether any of the sense lines are coupled to cells storing a match of the target data pattern can include charging (e.g., precharging) a local I/O line (e.g., local I/O line 334) coupled to a secondary sense amplifier (e.g., 312) to a particular voltage. The I/O line (e.g., 334) can be precharged via control circuitry such as control circuitry 140 shown in
In performing a BLOCKOR operation (which may be referred to as an “AccumulatorBlockOr”), the column decode lines (e.g., 310-1 to 310-W) coupled to the selected sensing circuitry (e.g., sense amplifiers 306 and/or compute components 331) can be activated in parallel (e.g., such that respective transistors 308-1 to 308-V are turned on) in order to transfer the voltages of the components of the sensing circuitry (e.g., sense amplifiers 306 and/or compute components 331) to the local I/O line (e.g., 334). The secondary sense amplifier (e.g., SSA 314) can sense whether the precharged voltage of the local I/O line changes (e.g., by more than a threshold amount) responsive to activation of the column decode lines.
For instance, if the I/O line 234 is precharged to a ground voltage and one or more of the selected compute components (e.g., 331-1 to 331-X) stores a logic 1 (e.g., 0V) to represent a match, then the SSA 312 can sense a pull up (e.g., increase) of the voltage on I/O line 334 to determine whether any stored data pattern matches the target data pattern (e.g., whether at least one of the accumulators stores a “1”). Alternatively, if the I/O line 334 is precharged to Vcc and one or more of the selected sensing circuitry components (e.g., accumulators) stores a logic 0 (e.g., Vcc) to represent a match, then the SSA 312 can sense a pull down (e.g., decrease) of the voltage on I/O line 334 to determine whether any stored data pattern matches the target data pattern (e.g., whether at least one of the accumulators stores a “0”).
In a number of examples, the determination of whether the sensing circuitry coupled to selected column decode lines stores a particular data value (e.g., a match data value of “1”) is effectively performing a logic “OR” operation. In this manner, voltages corresponding to data stored in sensing circuitry can be transferred, in parallel, to the local I/O line 334 and sensed by SSA 312 as part of a BLOCKOR operation. Embodiments of the present disclosure are not limited to particular precharge voltages of local I/O line 334 and/or to particular voltage values corresponding to logic 1 or logic 0.
At reference number 7.s.v (Load Row_LowAct in Comp_Comp), Row_LowAct 478 is stored in the sensing circuitry. At reference number 7.s.vi (Shift Right), a SHIFT operation is performed on Comp_Comp 431 (e.g., a bit-vector [00000000]). The SHIFT operation can be a right SHIFT operation. The results of the SHIFT operation are stored in the sensing circuitry.
At reference number 7.t (Load dest+1 in Comp_Comp), dest+1 494 is stored in the sensing circuitry. At reference number 7.0 (e.g., Do Comp_Comp AND operation with Row_Mask), an AND operation is performed on Comp_Comp (e.g., a bit-vector [04000000]) 431 and Row_Mask 476 (e.g., a bit-vector [ff000000]). The result [04000000] is stored in the sensing circuitry. At reference number 7.v (e.g., Store Comp_Comp in Row_LowAct), Comp_Comp 431 (e.g., a bit-vector [04000000]) is stored in the group of memory cells that store Row_LowAct 478.
At reference number 7.w (e.g., For Vector fixed width), a “For” loop is performed. The “For” loop referenced in reference number 7.w is analogous to the “For” loop referenced in reference number 7.s. Reference numbers 7.w.i to 7.w.iii are also analogous to reference numbers 7.s.i to 7.s.iii.
At reference number 7.w.i (e.g., Do Comp_Comp AND operation with Row_Mask), an AND operation is performed on Comp_Comp 431 (e.g., the bit-vector [04000000]) and Row_Mask 476 (e.g., the bit-vector [ff000000]). The result (e.g., [04000000]) of the AND operation is stored in the sensing circuitry. At reference number 7.w.ii (e.g., Store Comp_Comp in Row_LowAct), the result of the AND operation is stored in the group of memory cells that store Row_LowAct 478.
At reference number 7.w.iii (e.g., Do Comp_Comp AND operation with Row_Object), an AND operation is performed on Comp_Comp 431 (e.g., a bit-vector [04000000]) and Row_Object 482 (e.g., e.g., a bit-vector [01010101]). The result (e.g., [01000000]) of the AND operation is stored in the sensing circuitry.
At reference number 7.w.iv (e.g., Store result value of BLOCKOR operation into scalar integer destpc), a BLOCKOR operation is performed on Comp_Comp 431 (e.g., a bit-vector [01000000]). The result (e.g., 3) of the BLOCKOR operation is stored in the group of memory cells that store destpc 486.
At reference number 7.w.v (e.g., Load Row_LowAct in Comp_Comp), Row_LowAct 478 is stored in the sensing circuitry. At reference number 7.w.vi (e.g., Shift Right), A SHIFT operation is performed on Comp_Comp 431 (e.g., a bit-vector [01000000]). The result (e.g., a bit-vector [00000000]) of the SHIFT operation is stored in the sensing circuitry.
At reference number 7.x (e.g., if destc>destpc), it is determined that destc 484 (e.g., a bit-vector [0]) is not greater than destpc 486 (e.g., a bit-vector [3]). If destc 484 were greater than destpc 486, then a number of operations referenced in reference numbers 7.x.i to 7.x.ii would be performed.
For example, at reference number 7.x.i (e.g., Populate dest with Row_Mask), dest 492 is stored in the sensing circuitry. An OR operation is performed on Comp_Comp 431 and Row_Mask 476. The result of the OR operation is stored in the group of memory cells that store dest 492.
At reference number 7.x.ii (e.g., Populate dest+1 with Inverse Row_Mask), an INVERT operation is performed on Row_Mask 476. The result of the INVERT operation is stored in the sensing circuitry. An AND operation is performed on Comp_Comp 431 and dest+1 494. The result of the AND operation is stored in the group of memory cells that store dest+1 494.
At reference number 7.y (e.g., else If destpc>destc), it is determined that destpc 486 (e.g., a scalar integer 3) is greater than destc 484 (e.g., a scalar integer 0). A number of operations referenced in reference numbers 7.y.i to 7.y.ii are performed based on the determination that destpc 486 is greater than destc 484.
At reference number 7.y.i (Populate dest+1 with Row_Mask), dest+1 494 is stored in the sensing circuitry. An OR operation is performed on dest+1 494 and Row_Mask 476. The result (e.g., a bit-vector [ff000000]) of the OR operation is stored in the group of memory cells that store dest+1 494 to update dest+1 494.
At reference number 7.y.ii (Populate dest with Inverse Row_Mask), an INVERToperation is performed on Row_Mask 476. An AND operation is performed on Comp_Comp 431 and dest 492. The result (e.g., a bit-vector [00000000]) of the AND operation is stored in the group of memory cells that store dest 492 to update dest 492. The bold font used in the above bit-vectors describe the portion of the bit-vector (e.g., dest 492 and/or dest+1 494) that is updated.
The bit-vector [ff000000] (e.g., dest+1 494) indicates that the first element in srcb 490 is greater than the first element in srca 488. The bits that are associated with “ff” in dest+1 494 have a number of indexes. The indexes can identify associated elements in srca 488 and srcb 490 that form an element pair. The “ff” in dest+1 494 indicates the identified element in srcb 490 is greater than the identified element in srca 488. The [00000000] dest bit-vector 492 indicates that the first element in srca 488 can be less than the first element in srcb 490 or equal to the first element in srcb 490.
At reference number 7.z (e.g., else), it is determined whether destc 484 is not equal to destpc 486 and whether destpc 486 is not equal to destc 484. That is, at reference number 7.z it is determined whether destc 484 is equal to destpc 486. If destc 484 is equal to destpc 486, then a number of operations are performed at reference number 7.z.i. The number of operations can include performing an INVERT operation on Row_Mask 476 and storing the result of the INVERT operation in the sensing circuitry. The number of operations can also include performing an AND operation on Comp_Comp 431 and dest 492. The result of the AND operation can be stored in the group of memory cells that store dest 492. The number of operations can also include performing an AND operation on Comp_Comp 431 and dest+1 494. The result of the AND operation can be stored in the group of memory cells that store dest+1 494.
At reference number 7.a, a bit-vector [00ff0000] is created. The bit-vector [00ff0000] in a group of memory cells that store Row_Mask 476. The Row_Mask 476 (e.g., the bit-vector [00ff0000]) identifies that a current comparison operation compares a second element from srca 488 and a second element from srcb 490.
At reference number 7.b, a [00008000] bit-vector is stored in the sensing circuitry and is stored in a group of memory cells that store Row_Retained 480. The bit-vector [00008000] identifies the next elements that are to be compared in a subsequent iteration of the “For” loop referenced in reference number 7.
At reference number 7.c, srca 488 is stored in the sensing circuitry. At reference number 7.d the result (e.g., [0301000c]) of an AND operation performed on srca 488 and srcb 490 is stored in the sensing circuitry.
At reference number 7.e, an INVERT operation is performed on the bit-vector [0301000c]. The result of the INVERT operation is a bit-vector [fcfefff3]. The [fcfefff3] bit-vector is stored in a group of memory cells that store Row_LowAct 478. At reference number 7.f., the bit-vector [fcfefff3] (e.g., Row_LowAct 478) is stored in the sensing circuitry. At reference number 7.g., an AND operation is performed on Comp_Comp 431 (e.g., a bit-vector [fcfefff3]) and srca 488 (e.g., a bit-vector [0309020c]). The result (e.g., a bit-vector [00080200]) of is stored in the sensing circuitry.
At reference number 7.h, an AND operation is performed on Comp_Comp (e.g., a bit-vector [00080200]) and on Row_Mask 476 (e.g., a bit-vector [00ff0000]). The result (e.g., a bit-vector [00080000]) is stored in the sensing circuitry. At reference number 7.i, an OR operation is performed on Comp_Comp 431 (e.g., a bit-vector [00080000]) and dest 492 (e.g., a bit-vector [00000000]). The result (e.g., a bit-vector [00080000]) of the OR operation is stored in the sensing circuitry.
At reference number 7.j, the result (e.g., a bit-vector [00080000]) of the OR operation is stored in the group of memory cells that store dest 492. At reference number 7.k, Row_LowAct 478 (e.g., a bit-vector [fcfefff3]) is stored in the sensing circuitry. At reference number 7.l, an AND operation is performed on Comp_Comp 431 (e.g., a bit-vector [fcfefff3]) and on srcb 490 (e.g., a bit-vector [0705080c]). The result (e.g., a bit-vector [04040800]) is stored in the sensing circuitry.
At reference number 7.m, an AND operation is performed on the bit-vector [04040800] (e.g., Comp_Comp 431) and bit-vector [00ff0000] (e.g., Row_Mask 476). The result (e.g., a bit-vector [00040000]) is stored in the sensing circuitry. At reference number 7.n, an OR operation is performed on the bit-vector [00040000] (e.g., Comp_Comp 431) and the bit-vector [ff000000] (e.g., dest+1 494). At reference number 7.o, the result (e.g., a bit-vector [ff040000]) is stored in dest+1 494.
At reference number 7.p, dest 492 (e.g., [00080000]) is stored in the sensing circuitry. At reference number 7.q, an AND operation is performed on the bit-vector [00080000] (e.g., Comp_Comp 431) and a bit-vector [00ff0000] (e.g., Row_Mask 476). At reference number 7.r, the result (e.g., a bit-vector [00080000]) of the AND operation is stored in the group of memory cells that store Row_LowAct 478.
At reference number 7.s, a “For” loop is performed. The “For” loop increments a bit index after each iteration. The index begins with a one value and is incremented until the “For” loop breaks. The “For” loop continues while the index is less or equal to the element width. Reference numbers 7.s.i to 7.s.vi show a state of a number of memory cells after the last iteration of the “For” loop.
At reference number 7.s.i., an AND operation is performed on a bit-vector [00080000] (e.g., Comp_Comp 431) and a bit-vector [000ff000] (e.g., Row_Mask 476). The result (e.g., a bit-vector [00080000]) of the AND operation is stored in the sensing circuitry. At reference number 7.s.ii., the results of the AND operation are stored in the group of memory cells that store Row_LowAct 478.
At reference number 7.s.iii, an AND operation is performed on the bit-vector [00080000] (e.g., Comp_Comp 431) and a bit-vector [01010101] (e.g., Row_Object 482). The result (e.g., a bit-vector [00000000]) is stored in the sensing circuitry. At reference number 7.s.iv, a BLOCKOR operation is performed on Comp_Comp 431. The result (e.g., 4) of the BLOCKOR operation is stored memory that is associated with control circuitry and that stores destc 484.
At reference number 7.s.v, Row_LowAct 478 is stored in sensing circuitry. At reference number 7.s.vi., a SHIFT operation is performed on the bit-vector [00080000] (e.g., Comp_Comp 431). The result of the SHIFT operation is stored in the sensing circuitry.
At reference number 7.t, a bit-vector [ff040000] (e.g., dest+1 494] is stored in the sensing circuitry. At reference number 7.u, an AND operation is performed on a bit-vector [ff040000] (e.g., Comp_Comp 431) and the bit-vector [00ff0000] (e.g., Row_Mask 476). The result (e.g., a bit-vector [00040000]) is stored in the sensing circuitry. At reference number 7.v, the result (e.g., a bit-vector [00040000]) is stored in the group of memory cells that store Row_LowAct 478.
Reference numbers 7.w.i to 7.w.vi reference a number of operations performed in a “For” loop (e.g., 7.w). At reference number 7.w.i, an AND operation is performed on the bit-vector [00040000] (e.g., Comp_Comp) and a bit-vector [00ff0000] (e.g., Row_Mask 476). The result (e.g., a bit-vector [00040000]) of the AND operation is stored in the sensing circuitry 431. At reference number 7.w.ii, the result (e.g., a bit-vector [00040000]) of the AND operation is stored in the group of memory cells that store Row_LowAct 478. At reference number 7.w.iii., an AND operation is performed on the bit-vector [00040000] (e.g., Comp_Comp) and a bit-vector [01010101] (e.g., Row_Object 482). The result (e.g., [00000000]) of the AND operation is stored in the sensing circuitry. At reference number 7.w.iv, a BLOCKOR operation is performed on a bit-vector [00000000] (e.g., Comp_Comp). The result (e.g., 3) of the BLOCKOR operation is stored in memory that is associated with control circuitry and that stores destpc 486. At reference number 7.w.v, Row_LowAct 478 is stored in the sensing circuitry. At reference number 7.w.vi, A SHIFT operation (e.g., a right SHIFT operation) is performed on the bit-vector [00000000] (e.g., Comp_Comp). The result (e.g., a bit-vector [00000000]) of the SHIFT operation is stored in the sensing circuitry.
At reference number 7.x, it is determined that destc 484 (e.g., [4]) is greater than destpc 486 (e.g., [3]). At reference number 7.x.i, a bit-vector [00080000] (e.g., dest 492) is stored in the sensing circuitry and an OR operation is performed on the bit-vector [00080000] (e.g., Comp_Comp 431) and a bit-vector [00ff0000] (e.g., Row_Mask 476). As a result (e.g., a bit-vector [00ff0000]) is stored in a group of memory cells that store dest 492. That is, dest 492 is updated (e.g., [00ff0000]). At reference number 7.x.ii, an INVERT operation is performed on the bit-vector [00ff0000]. The results (e.g., a bit-vector [ff00ffff]) is stored in the sensing circuitry. An AND operation is performed on the bit-vector [ff00ffff] (e.g., Comp_Comp 431) and a bit-vector [ff040000] (e.g., dest+1 494). The result (e.g., a bit-vector [ff000000]) is stored in the group of memory cells that store dest+1 494. That is, dest+1 494 is updated. The bit-vector [00ff0000] (e.g., dest 492) indicates that the second element in srca 488 is greater than the second element in srcb 490. The bit-vector [ff000000] dest+1 494 indicates that the second element in srcb 490 is less than or equal to the second element in srca 488.
At reference number 7.y, it is determined that destpc 486 is not greater than destc 484. At reference number 7.z, it is determined that destc 484 is not equal to destpc 486.
The final two iteration of the “For” loop referenced in reference number 7 are not shown. After a third iteration of the “For” loop, dest 492 has a value equal to a bit-vector [00ff0000] and dest+1 494 has a value equal to the bit-vector [ff00ff00]. That is, dest+1 494 indicates that the third element in srcb 490 is greater than the third element in srca 488.
After a fourth iteration of the “For” loop reference in reference number 7, dest 492 has a value equal to the bit-vector [00ff0000] and dest+1 has a value equal to the bit-vector [ff00ff00]. That is, dest 492 and dest+1 494 together indicate that the fourth element in srca 488 is equal to the fourth element in srcb 490. The “00” bits with a same index in both dest+1 494 and dest 492 indicate that the corresponding elements from srcb 490 and srca 488 are equal.
At reference number 8, the memory cells that store Row_Mask 476, Row_LowAct 478, Row_Retained 480, Row_Object 482, srca 488, and/or srcb 490 can be released. As used herein, releasing memory cells can make the memory cells available for storing data that is associated with a different instance of a comparison operation and/or logical operations not associated with a comparison operation.
Embodiments however, are not limited to the order of the sequence of instructions in the pseudocode in this example. For example, a number of operations reference in reference numbers 7.t. to 7.w.vi. can be performed before a number of operations reference in reference numbers 7.p. to 7.s.vi. are performed.
The functionality of the sensing circuitry 250 of
Initially storing the result of a particular operation in the sense amplifier 206 (e.g., without having to perform an additional operation to move the result from the compute component 231 (e.g., accumulator) to the sense amplifier 206) is advantageous because, for instance, the result can be written to a row (of the array of memory cells) or back into the accumulator without performing a precharge cycle (e.g., on the complementary data lines 205-1 (D) and/or 205-2 (D_)).
An example of pseudo code associated with loading (e.g., copying) a first data value stored in a cell coupled to row 204-X into the accumulator can be summarized as follows:
In the pseudo code above, “Deactivate EQ” indicates that an equilibration signal (EQ signal shown in
After Row X is enabled (e.g., activated), in the pseudo code above, “Fire Sense Amps” indicates that the sense amplifier 206 is enabled to set the primary latch and subsequently disabled. For example, as shown at t3 in
The four sets of possible sense amplifier and accumulator signals illustrated in
After firing the sense amps, in the pseudo code above, “Activate LOAD” indicates that the LOAD control signal goes high as shown at t4 in
After setting the secondary latch from the data values stored in the sense amplifier (and present on the data lines 205-1 (D) and 205-2 (D_), in the pseudo code above, “Deactivate LOAD” indicates that the LOAD control signal goes back low as shown at t5 in
After storing the data value on the secondary latch, the selected row (e.g., ROW X) is disabled (e.g., deselected, closed such as by deactivating a select signal for a particular row) as indicated by “Close Row X” and indicated at t6 in
A subsequent operation phase associated with performing the AND or the OR operation on the first data value (now stored in the sense amplifier 206 and the secondary latch of the compute component 231) and the second data value (stored in a memory cell 202-1 coupled to Row Y 204-Y) includes performing particular steps which depend on the whether an AND or an OR is to be performed. Examples of pseudo code associated with “ANDing” and “ORing” the data value residing in the accumulator (e.g., the first data value stored in the memory cell 202-2 coupled to Row X 204-X) and the second data value (e.g., the data value stored in the memory cell 202-1 coupled to Row Y 204-Y) are summarized below. Example pseudo code associated with “ANDing” the data values can include:
In the pseudo code above, “Deactivate EQ” indicates that an equilibration signal corresponding to the sense amplifier 206 is disabled (e.g., such that the complementary data lines 205-1 (D) and 205-2 (D_) are no longer shorted to VDD/2), which is illustrated in
After Row Y is enabled, in the pseudo code above, “Fire Sense Amps” indicates that the sense amplifier 206 is enabled to amplify the differential signal between 205-1 (D) and 205-2 (D_), resulting in a voltage (e.g., VDD) corresponding to a logic 1 or a voltage (e.g., GND) corresponding to a logic 0 being on data line 205-1 (D) (and the voltage corresponding to the other logic state being on complementary data line 205-2 (D_)). As shown at t10 in
After the second data value sensed from the memory cell 202-1 coupled to Row Y is stored in the primary latch of sense amplifier 206, in the pseudo code above, “Close Row Y” indicates that the selected row (e.g., ROW Y) can be disabled if it is not desired to store the result of the AND logical operation back in the memory cell corresponding to Row Y. However,
With the first data value (e.g., Row X) stored in the dynamic latch of the accumulator 231 and the second data value (e.g., Row Y) stored in the sense amplifier 206, if the dynamic latch of the compute component 231 contains a “0” (i.e., a voltage corresponding to a “0” on node S2 and a voltage corresponding to a “1” on node S1), the sense amplifier data is written to a “0” (regardless of the data value previously stored in the sense amp) since the voltage corresponding to a “1” on node S1 causes transistor 209-1 to conduct thereby coupling the sense amplifier 206 to ground through transistor 209-1, pass transistor 207-1 and data line 205-1 (D). When either data value of an AND operation is “0,” the result is a “0.” Here, when the second data value (in the dynamic latch) is a “0,” the result of the AND operation is a “0” regardless of the state of the first data value, and so the configuration of the sensing circuitry causes the “0” result to be written and initially stored in the sense amplifier 206. This operation leaves the data value in the accumulator unchanged (e.g., from Row X).
If the secondary latch of the accumulator contains a “1” (e.g., from Row X), then the result of the AND operation depends on the data value stored in the sense amplifier 206 (e.g., from Row Y). The result of the AND operation should be a “1” if the data value stored in the sense amplifier 206 (e.g., from Row Y) is also a “1,” but the result of the AND operation should be a “0” if the data value stored in the sense amplifier 206 (e.g., from Row Y) is also a “0.” The sensing circuitry 250 is configured such that if the dynamic latch of the accumulator contains a “1” (i.e., a voltage corresponding to a “1” on node S2 and a voltage corresponding to a “0” on node S1), transistor 209-1 does not conduct, the sense amplifier is not coupled to ground (as described above), and the data value previously stored in the sense amplifier 206 remains unchanged (e.g., Row Y data value so the AND operation result is a “1” if the Row Y data value is a “1” and the AND operation result is a “0” if the Row Y data value is a “0”). This operation leaves the data value in the accumulator unchanged (e.g., from Row X).
After the result of the AND operation is initially stored in the sense amplifier 206, “Deactivate AND” in the pseudo code above indicates that the AND control signal goes low as shown at t12 in
Although the timing diagrams illustrated in
A subsequent operation phase can alternately be associated with performing the OR operation on the first data value (now stored in the sense amplifier 206 and the secondary latch of the compute component 231) and the second data value (stored in a memory cell 202-1 coupled to Row Y 204-Y). The operations to load the Row X data into the sense amplifier and accumulator that were previously described with respect to times t1-t7 shown in
The “Deactivate EQ” (shown at t8 in
With the first data value (e.g., Row X) stored in the secondary latch of the compute component 231 and the second data value (e.g., Row Y) stored in the sense amplifier 206, if the dynamic latch of the accumulator contains a “0” (i.e., a voltage corresponding to a “0” on node S2 and a voltage corresponding to a “1” on node S1), then the result of the OR operation depends on the data value stored in the sense amplifier 206 (e.g., from Row Y). The result of the OR operation should be a “1” if the data value stored in the sense amplifier 206 (e.g., from Row Y) is a “1,” but the result of the OR operation should be a “0” if the data value stored in the sense amplifier 206 (e.g., from Row Y) is also a “0.” The sensing circuitry 250 is configured such that if the dynamic latch of the accumulator contains a “0,” with the voltage corresponding to a “0” on node S2, transistor 209-2 is off and does not conduct (and pass transistor 207-1 is also off since the AND control signal is not asserted) so the sense amplifier 206 is not coupled to ground (either side), and the data value previously stored in the sense amplifier 206 remains unchanged (e.g., Row Y data value such that the OR operation result is a “1” if the Row Y data value is a “1” and the OR operation result is a “0” if the Row Y data value is a “0”).
If the dynamic latch of the accumulator contains a “1” (i.e., a voltage corresponding to a “1” on node S2 and a voltage corresponding to a “0” on node S1), transistor 209-2 does conduct (as does pass transistor 207-2 since the OR control signal is asserted), and the sense amplifier 206 input coupled to data line 205-2 (D_) is coupled to ground since the voltage corresponding to a “1” on node S2 causes transistor 209-2 to conduct along with pass transistor 207-2 (which also conducts since the OR control signal is asserted). In this manner, a “1” is initially stored in the sense amplifier 206 as a result of the OR operation when the secondary latch of the accumulator contains a “1” regardless of the data value previously stored in the sense amp. This operation leaves the data in the accumulator unchanged.
After the result of the OR operation is initially stored in the sense amplifier 206, “Deactivate OR” in the pseudo code above indicates that the OR control signal goes low as shown at t12 in
The sensing circuitry 250 illustrated in
In a similar approach to that described above with respect to inverting the data values for the AND and OR operations described above, the sensing circuitry shown in
The “Deactivate EQ,” “Open Row X,” “Fire Sense Amps,” “Activate LOAD,” and “Deactivate LOAD” shown in the pseudo code above indicate the same functionality as the same operations in the pseudo code for the “Copy Row X into the Accumulator” initial operation phase described above prior to pseudo code for the AND operation and OR operation. However, rather than closing the Row X and Precharging after the Row X data is loaded into the sense amplifier 206 and copied into the dynamic latch, a compliment version of the data value in the dynamic latch of the accumulator can be placed on the data line and thus transferred to the sense amplifier 206 by enabling (e.g., causing transistor to conduct) and disabling the invert transistors (e.g., ANDinv and ORinv). This results in the sense amplifier 206 being flipped from the true data value that was previously stored in the sense amplifier to a compliment data value (e.g., inverted data value) stored in the sense amp. That is, a true or compliment version of the data value in the accumulator can be transferred to the sense amplifier by activating and deactivating ANDinv and ORinv. This operation leaves the data in the accumulator unchanged.
Because the sensing circuitry 250 shown in
When performing logical operations in this manner, the sense amplifier 206 can be pre-seeded with a data value from the dynamic latch of the accumulator to reduce overall current utilized because the sense amps 206 are not at full rail voltages (e.g., supply voltage or ground/reference voltage) when accumulator function is copied to the sense amplifier 206. An operation sequence with a pre-seeded sense amplifier 206 either forces one of the data lines to the reference voltage (leaving the complementary data line at VDD/2, or leaves the complementary data lines unchanged. The sense amplifier 206 pulls the respective data lines to full rails when the sense amplifier 206 fires. Using this sequence of operations will overwrite data in an enabled row.
A SHIFT operation can be accomplished by multiplexing (“muxing”) two neighboring data line complementary pairs using a traditional DRAM isolation (ISO) scheme. According to embodiments of the present disclosure, the shift circuitry 223 can be used for shifting data values stored in memory cells coupled to a particular pair of complementary data lines to the sensing circuitry 250 (e.g., sense amplifier 206) corresponding to a different pair of complementary data lines (e.g., such as a sense amplifier 206 corresponding to a left or right adjacent pair of complementary data lines. As used herein, a sense amplifier 206 corresponds to the pair of complementary data lines to which the sense amplifier is coupled when isolation transistors 221-1 and 221-2 are conducting. The SHIFT operations (right or left) do not pre-copy the Row X data value into the accumulator. Operations to shift right Row X can be summarized as follows:
In the pseudo code above, “Deactivate Norm and Activate Shift” indicates that a NORM control signal goes low causing isolation transistors 221-1 and 221-2 of the shift circuitry 223 to not conduct (e.g., isolate the sense amplifier from the corresponding pair of complementary data lines). The SHIFT control signal goes high causing isolation transistors 221-3 and 221-4 to conduct, thereby coupling the sense amplifier 206 to the left adjacent pair of complementary data lines (e.g., on the memory array side of non-conducting isolation transistors 221-1 and 221-2 for the left adjacent pair of complementary data lines).
After the shift circuitry 223 is configured, the “Deactivate EQ,” “Open Row X,” and “Fire Sense Amps” shown in the pseudo code above indicate the same functionality as the same operations in the pseudo code for the “Copy Row X into the Accumulator” initial operation phase described above prior to pseudo code for the AND operation and OR operation. After these operations, the Row X data value for the memory cell coupled to the left adjacent pair of complementary data lines is shifted right and stored in the sense amplifier 206.
In the pseudo code above, “Activate Norm and Deactivate Shift” indicates that a NORM control signal goes high causing isolation transistors 221-1 and 221-2 of the shift circuitry 223 to conduct (e.g., coupling the sense amplifier to the corresponding pair of complementary data lines), and the SHIFT control signal goes low causing isolation transistors 221-3 and 221-4 to not conduct and isolating the sense amplifier 206 from the left adjacent pair of complementary data lines (e.g., on the memory array side of non-conducting isolation transistors 221-1 and 221-2 for the left adjacent pair of complementary data lines). Since Row X is still active, the Row X data value that has been shifted right is transferred to Row X of the corresponding pair of complementary data lines through isolation transistors 221-1 and 221-2.
After the Row X data values are shifted right to the corresponding pair of complementary data lines, the selected row (e.g., ROW X) is disabled as indicated by “Close Row X” in the pseudo code above, which can be accomplished by the access transistor turning off to decouple the selected cell from the corresponding data line. Once the selected row is closed and the memory cell is isolated from the data lines, the data lines can be precharged as indicated by the “Precharge” in the pseudo code above. A precharge of the data lines can be accomplished by an equilibrate operation, as described above. Operations to shift left Row X can be summarized as follows:
In the pseudo code above, “Activate Norm and Deactivate Shift” indicates that a NORM control signal goes high causing isolation transistors 221-1 and 221-2 of the shift circuitry 223 to conduct, and the SHIFT control signal goes low causing isolation transistors 221-3 and 221-4 to not conduct. This configuration couples the sense amplifier 206 to a corresponding pair of complementary data lines and isolates the sense amplifier from the right adjacent pair of complementary data lines.
After the shift circuitry is configured, the “Deactivate EQ,” “Open Row X,” and “Fire Sense Amps” shown in the pseudo code above indicate the same functionality as the same operations in the pseudo code for the “Copy Row X into the Accumulator” initial operation phase described above prior to pseudo code for the AND operation and OR operation. After these operations, the Row X data value for the memory cell coupled to the pair of complementary data lines corresponding to the sense circuitry 250 is stored in the sense amplifier 206.
In the pseudo code above, “Deactivate Norm and Activate Shift” indicates that a NORM control signal goes low causing isolation transistors 221-1 and 221-2 of the shift circuitry 223 to not conduct (e.g., isolate the sense amplifier from the corresponding pair of complementary data lines), and the SHIFT control signal goes high causing isolation transistors 221-3 and 221-4 to conduct coupling the sense amplifier to the left adjacent pair of complementary data lines (e.g., on the memory array side of non-conducting isolation transistors 221-1 and 221-2 for the left adjacent pair of complementary data lines. Since Row X is still active, the Row X data value that has been shifted left is transferred to Row X of the left adjacent pair of complementary data lines.
After the Row X data values are shifted left to the left adjacent pair of complementary data lines, the selected row (e.g., ROW X) is disabled as indicated by “Close Row X,” which can be accomplished by the access transistor turning off to decouple the selected cell from the corresponding data line. Once the selected row is closed and the memory cell is isolated from the data lines, the data lines can be precharged as indicated by the “Precharge” in the pseudo code above. A precharge of the data lines can be accomplished by an equilibrate operation, as described above.
According to various embodiments, general computing can be enabled in a memory array core of a processor-in-memory (PIM) device such as a DRAM one transistor per memory cell (e.g., 1T1C) configuration at 6F{circumflex over ( )}2 or 4F{circumflex over ( )}2 memory cell sizes, for example. The advantage of the apparatuses and methods described herein is not realized in terms of single instruction speed, but rather the cumulative speed that can be achieved by an entire bank of data being computed in parallel without ever transferring data out of the memory array (e.g., DRAM) or firing a column decode. In other words, data transfer time can be eliminated. For example, apparatus of the present disclosure can perform ANDS or ORs simultaneously using data values in memory cells coupled to a data line (e.g., a column of 16K memory cells).
In previous approach sensing circuits where data is moved out for logical operation processing (e.g., using 32 or 64 bit registers), fewer operations can be performed in parallel compared to the apparatus of the present disclosure. In this manner, significantly higher throughput is effectively provided in contrast to conventional configurations involving a central processing unit (CPU) discrete from the memory such that data must be transferred therebetween. An apparatus and/or methods according to the present disclosure can also use less energy/area than configurations where the CPU is discrete from the memory. Furthermore, an apparatus and/or methods of the present disclosure can improve upon the smaller energy/area advantages since the in-memory-array logical operations save energy by eliminating certain data value transfers.
In the example illustrated in
The first operation phase of a logical operation described below involves loading a first operand of the logical operation into the accumulator. The time references (e.g., t1, etc.) shown in
t time t1, the equilibration signal 726 is deactivated, and then a selected row is enabled (e.g., the row corresponding to a memory cell whose data value is to be sensed and used as a first input). Signal 704-0 represents the voltage signal applied to the selected row (e.g., Row Y 204-Y shown in
At time t3, the sense amplifier (e.g., 206 shown in
According to some embodiments, the primary latch of sense amplifier 206 can be coupled to the complementary data lines D and D_ through respective pass transistors (not shown in
At time t4, the pass transistors (if present) can be enabled (e.g., via respective Passd and Passdb control signals 711 applied to control lines coupled to the respective gates of the pass transistors going high). At time t5, the accumulator positive control signal 712-1 (e.g., Accumb) and the accumulator positive control signal 712-2 (e.g., Accum) are activated via respective control lines 212-1 and 212-2 shown in
At time t6, the Passd control signal 711 (and the Passdb control signal) goes low thereby turning off the pass transistors (if present). However, since the accumulator control signals ACCUMB 712-1 and ACCUM 712-2 remain activated, an accumulated result is stored (e.g., latched) in the secondary latches (e.g., accumulator). At time t7, the row signal 704-0 is deactivated, and the array sense amps are disabled at time t8 (e.g., sense amplifier control signals 728 and 765 are deactivated).
At time t9, the data lines D and D_ are equilibrated (e.g., equilibration signal 726 is activated), as illustrated by data line voltage signals 705-1 and 705-2 moving from their respective rail values to the equilibration voltage (VDD/2). The equilibration consumes little energy due to the law of conservation of energy. As described below in association with
As shown in the timing diagrams illustrated in
At time t3, the sense amplifier (e.g., 206 shown in
As shown in timing diagrams illustrated in
Since the accumulator was previously enabled, activating only Passd (811-1 as shown in
Similarly, in an example OR/NOR operation shown in the timing diagram illustrated in
At the conclusion of an intermediate operation phase such as that shown in
For example, performing a last operation phase of an R-input can include performing the operation phase shown in
A NAND operation can be implemented, for example, by storing the result of the R-1 iterations for an AND operation in the sense amplifier, then inverting the sense amplifier before conducting the last operation phase to store the result (described below). A NOR operation can be implemented, for example, by storing the result of the R-1 iterations for an OR operation in the sense amplifier, then inverting the sense amplifier before conducting the last operation phase to store the result (described below).
The last operation phase illustrated in the timing diagram of
As shown in timing diagram illustrated in
Activating the Passd control signal 1011 (and Passdb signal) (e.g., in association with an AND or OR operation) transfers the accumulated output stored in the secondary latch of compute component 231-6 shown in
For an OR operation, if any of the memory cells sensed in the prior operation phases (e.g., the first operation phase of
The result of the R-input AND or OR logical operations can then be stored back to a memory cell of array 230 shown in
The timing diagram illustrated in
As shown in
Although the example of performing a last operation phase of an R-input was discussed above with respect to
The sensing circuitry 1150 illustrated in
Logic selection transistors 1152 and 1154 are arranged similarly to transistor 207-1 (coupled to an AND signal control line) and transistor 207-2 (coupled to an OR signal control line) respectively, as shown in
The PASS* control signal is not necessarily complementary to the PASS control signal. For instance, it is possible for the PASS and PASS* control signals to both be activated or both be deactivated at the same time. However, activation of both the PASS and PASS* control signals at the same time shorts the pair of complementary sense lines together, which may be a disruptive configuration to be avoided. Logical operations results for the sensing circuitry illustrated in
The logic table illustrated in
Via selective control of the continuity of the pass gates 1107-1 and 1107-2 and the swap transistors 1142, each of the three columns of the first set of two rows of the upper portion of the logic table of
The columns of the lower portion of the logic table illustrated in
As such, the sensing circuitry shown in
The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus might include a first group of memory cells coupled to a first access line. A first element can be stored in the first group of memory cells. An example apparatus might include a second group of memory cells coupled to a second access line. A second element can be stored in the second group of memory cells. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.
Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the one or more embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.
In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.
This application is a Continuation of U.S. application Ser. No. 15/822,748, filed Nov. 27, 2017, which issues as U.S. Pat. No. 10,593,418, on Mar. 17, 2020, which is a Continuation of U.S. application Ser. No. 14/716,079, dated May 19, 2015, which issued as U.S. Pat. No. 9,830,999 on Nov. 28, 2017, which claims the benefit of U.S. Provisional Application No. 62/008,004, filed Jun. 5, 2014, the contents of which are incorporated herein by reference.
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