Dielectric gap fill process that effectively reduces capacitance between narrow metal lines using HDP-CVD

Abstract

Substrate bombardment during HDP deposition of carbon-doped silicon oxide film results in filling the gaps between metal lines with carbon-doped low k dielectric material. This leads to the placement of low k dielectric between the narrow metal lines while the films over the metal lines have higher dielectric constant due to removal of carbon from these films during ion bombardment. Films over the metal lines have properties similar to silicon dioxide and are ready for sequential integration processes.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to fabrication of semiconductor integrated circuit device structures and, in particular, to a method of filling gaps between narrow metal lines with a carbon-doped, low k dielectric silicon oxide thin film utilizing High Density Plasma-Chemical Vapor Deposition (HDP-CVD), thereby effectively reducing the capacitance between the narrow metal lines.

2. Discussion of Related Art

In the fabrication of semiconductor integrated circuits, several levels of conductive interconnects are typically required to electrically connect the millions of active elements included in the circuit. Insulating materials, such as silicon dioxide (SiO 2 ), have been employed to isolate the interconnect wires in a given level of the IC as well as between its different levels. However, as interconnect wiring has become more dense, parasitics due to capacitive coupling negatively impact device performance, thus requiring insulators with lower dielectric constants. Pure SiO 2 thin films have a dielectric constant of around k=4. SiO 2 can be grown by oxidation of pure silicon using O 2 or H 2 O gas, or can be deposited by chemical vapor deposition (CVD) or High Density Plasma-Chemical Vapor Deposition (HDP-CVD) employing reactants such as SiH 4 /Ar/N 2 O, SiH 4 /Ar/NO, and/or SiH 4 /Ar/O 2 gas mixtures as reactants.

Current HDP-CVD SiO 2 processes use SiH 4 and O 2 for deposition along with Ar or He for sputtering. Referring to FIG. 1A , conventional CVD SiO 2 processes without a sputtering component result in the formation of voids between adjacent metal lines due to the high sticking probabilities of the precursors SiH 3 and SiH 2 in silane discharges coupled with insignificant surface diffusion. It is known that these voids can be eliminated in deposition of pure SiO 2 films by adding a sputtering component to the HDP-CVD process. Sputtering, which is controlled by applying high frequency bias power to the substrate, bombards the horizontal surfaces of the deposited SiO 2 , as shown in FIG. 1B , and pulls back the corners of the gap between structures resulting in complete filling of the gaps between narrowly-spaced metal lines, as shown in FIG. 1 C.

Work has been done wherein SiO 2 has been doped to lower the dielectric constant of the layer. For example, spin coating techniques have been employed to produce carbon-containing SiO 2 spin on glass (SOG) films with dielectric constants approaching k=3.0. While SOG films can be suitable for a great many applications, including providing interconnect dielectrics, they have a number of manufacturing disadvantages. For example, SOG processing involves the use of liquids and produces waste material that requires disposal. Also, SOG processing often produces films that have high OH − concentrations. In addition, SOG's often suffer from temperature instability, tensile stress and moisture absorption/desorption problems.

Organically-doped SiO 2 layers have also been deposited using CVD processes. One technique utilizes substitute precursors such as methylsilane (CH 3 —SiH 3 ) or phenylsilane (C 6 H 5 /SiH 3 ) as a substitute for the SiH 4 precursor. However, with respect to this technique, the methyl group is only partially dissociated and some of the methyl constituents remain bonded to the silicon atom in the oxide layer. The resulting carbon-doped oxide layer has a dielectric constant around k=3. A further technique utilizes CH 3 —SiH 3 and H 2 O 2 as the reactant species.

While attempts have been made in the past to deposit carbon-doped SiO 2 layers utilizing Plasma Enhanced CVD techniques without sputtering, it has been found that the same voids are produced in these processes as those appearing in the deposition of pure SiO 2 layers without sputtering. Past attempts to deposit carbon-doped SiO 2 layers utilizing sputtering have appeared to result in the formation of pure SiO 2 , the sputtering apparently resulting in the carbon species being driven from the SiO 2 structures. Thus, those skilled in the art have been lead away from forming carbon-doped SiO 2 layers using deposition processes enhanced by sputtering.

SUMMARY OF THE INVENTION

The use of carbon containing precursors to replace silane or added to silane and oxygen as the reactant species in an HDP-CVD reactor is desirable to produce a low dielectric constant film.

In accordance with the present invention, we have recognized that allowing substrate bombardment during HDP deposition of a carbon-doped silicon oxide film results in the filling of the intra-metal gaps with low k material having high carbon content. The process leads to the placement of a low k material exactly in the area where it can do the most good. Since the sputter process can only effectively bombard the film on the horizontal surface, the film deposited in the gaps between metal lines is least affected by the bombardment energy and, thus, maintains a carbon content conducive to low k properties. The film deposited over the metal lines has a higher dielectric constant due to the removal of carbon from these upper films during ion bombardment. Thus, the process effectively delivers material in the gap between narrow metal lines that is filled with low k SiOC dielectric which lowers the capacitance between the metal lines. The films over the metal lines have properties similar to SiO 2 and are available for sequential integration processes.

A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross-section illustrating formation of a silicon dioxide layer between narrow metal lines utilizing chemical vapor deposition without a sputtering component.

FIG. 1B is a cross-section illustrating formation of a silicon dioxide layer between narrow metal lines utilizing chemical vapor deposition with a sputtering component.

FIG. 1C is a cross-section illustrating a pure silicon dioxide layer formed between narrow metal lines using chemical vapor deposition with a sputtering component.

FIG. 2A is a cross-section illustrating formation of a carbon-doped silicon oxide film using chemical vapor deposition without a sputtering component.

FIG. 2B is a cross-section illustrating attempts to form a carbon-doped silicon oxide film using chemical vapor deposition with a sputtering component but resulting in formation of silicon dioxide.

FIG. 3 is a simple pictorial representation of a conventional High Density Plasma Chemical Vapor deposition reactor chamber.

FIG. 4A is a cross-section view illustrating a method for forming a low k dielectric material between narrow metal lines in accordance with the present invention.

FIG. 4B is a cross-section view illustrating formation of carbon-doped silicon oxide between narrow metal lines with an overlying layer of silicon oxide-like material in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3 shows a conventional High Density Plasma Chemical Vapor Deposition (HDP-CVD) reactor chamber 10 in simplified form. The chamber 10 includes a lower support member 12 which can be utilized for supporting a semiconductor wafer 14 for processing in the reactor chamber 10 . As shown in FIG. 3 , the lower support member 12 can be connected to a source 16 of high frequency bias substrate power which causes sputtering, i.e. bombardment of the horizontal wafer surfaces with ion species generated during the plasma discharge. The reactor chamber 10 also includes an upper electrode 18 to which a power supply 20 is connected for generating a plasma discharge in the conventional manner.

Thus, in accordance with the present invention, carbon containing precursors, such as methylsilane or phenylsiliane, are utilized to replace silane or added to silane in oxygen (or H 2 O 2 ) as the reactant species in the HDP-CVD reactor to produce a low dielectric constant (k) film between narrow metal lines. As shown in FIG. 4A , an HDP-CVD process in accordance with the present invention includes a simultaneous sputter etch, using, for example, Ar or He in the gas mixture, and chemical vapor deposition (CVD) which results in complete filling of the small gaps between the metal lines. The sputter etch component is controlled by high frequency bias power to the substrate in the conventional manner.

As stated above, an HDP process without bombardment effectively maintains the carbon content in the film and makes a relatively low density film to achieve the lower dielectric constant, but results in voids between the metal lines. A process in accordance with the invention provides for substrate bombardment during HDP deposition, thus filling the intra-metal gaps with low k materials having high carbon contents. This leads to the placement of a low k material in the areas between the metal films where it will do the most good. Since the sputter etch process can only effectively bombard the films on the horizonal surface, the films in the gaps between the metal lines are least affected by the bombardment energy and, thus, maintain a carbon content conducive to low k properties. Films over the metal lines have higher dielectric constant due to the removal of carbon from it during ion bombardment. Thus, the disclosed process delivers a gap effectively filled with low k (k=3.0-3.5) SiOC materials which lower the capacitance between the narrow metal lines. The films over the metal lines have similar properties as silicon dioxide (k=3.5-4.0) and are ready for sequential integration processes. A structure resulting from the above described process is shown in FIG. 4 B.

It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. It is intended that the following claims define the scope of the invention and that methods within the scope of these claims and their equivalents be covered thereby.

Claims

1. An integrated circuit structure comprising:first and second spaced-apart conductive structures formed directly upon a substantially planar upper surface region of a layer of lower dielectric material; low k dielectric material formed directly on the substantially planar upper surface region of the layer of lower dielectric material between the first and second spaced-apart conductive structures; and upper dielectric material formed over the low k dielectric material and over the first and second spaced-apart conductive structures.

2. An integrated circuit structure comprising:first and second spaced-apart conductive structures formed directly upon a substantially planar surface region of a layer of first dielectric material; carbon-containing silicon oxide having a first dielectric constant formed directly on the substantially planar upper surface region of the layer of first dielectric material between the first and second spaced-apart conductive structures; and second dielectric material having a second dielectric constant that is greater than the first dielectric constant formed over the carbon containing silicon oxide and over the first and second spaced-apart conductive structures.

3. An integrated circuit structure as in claim 2, and wherein the first and second spaced-apart conductive structures include aluminum.

4. An integrated circuit structure as in claim 2, and wherein the first and second spaced-apart conductive structures include copper.

5. An integrated circuit structure as in claim 2, and wherein the first dielectric constant is about 2.5-3.0.

6. An integrated circuit structure as in claim 5, and wherein the second dielectric constant is about 3.9-4.3.