Claims
- 1. An electrical interconnect residing over a semiconductor substrate, the interconnect comprising:
- a capturing diffusion barrier layer disposed over the substrate wherein the capturing layer has a thickness in a range of approximately 5.ANG. to 100.ANG.;
- a blocking diffusion barrier layer disposed over the capturing layer, the blocking layer has a thickness in the range of approximately 50.ANG. to 500.ANG. and is substantially unreactive with the capturing layer at approximately room temperature; and
- a conductive layer disposed over the blocking layer, the conductive layer being both thicker than the blocking layer and substantially unreactive with the blocking layer at approximately room temperature, the conductive layer further being substantially reactive with the capturing layer.
- 2. The interconnect of claim 1, wherein the conductive layer primarily comprises Cu.
- 3. The interconnect of claim 2, wherein the capturing layer is electrically conductive and comprises a material selected from the group consisting of Ti, Al, Zr, Hf, Sc, and any combination thereof.
- 4. The interconnect of claim 2, wherein the blocking layer is electrically conductive and comprises a material selected from the group consisting of Ta, TaN, TiN, HfN, V, Nb, Cr, W, Mo, and any combination thereof.
- 5. The interconnect of claim 1, wherein the blocking layer is substantially unreactive with both the capturing layer and the conductive layer up to a temperature of approximately 200.degree. C.
- 6. The interconnect of claim 1, wherein the blocking layer is substantially unreactive with both the capturing layer and the conductive layer up to a temperature of approximately 500.degree. C.
- 7. The interconnect of claim 1, wherein the conductive layer is substantially reactive with the capturing layer at a temperature of approximately 200.degree. C.
- 8. The interconnect of claim 1, wherein the conductive layer is substantially reactive with the capturing layer at approximately room temperature.
- 9. An electrical interconnect residing over a semiconductor substrate, the interconnect comprising:
- a capturing diffusion barrier layer disposed over the substrate, the capturing layer has a thickness in a range of approximately 5.ANG. to 100.ANG. and is electrically conductive;
- a blocking diffusion barrier layer disposed over the capturing layer, the blocking layer being both thicker than the capturing layer and substantially unreactive with the capturing layer at approximately room temperature, the blocking layer has a thickness in a range of approximately 50.ANG. to 500.ANG. and is electrically conductive; and
- a copper layer disposed over the blocking layer, the copper layer primarily comprising copper, the copper layer being both thicker than the blocking layer and substantially unreactive with the blocking layer up to a temperature of approximately 200.degree. C., the copper layer further being substantially reactive with the capturing layer at a temperature of approximately 200.degree. C.
- 10. The interconnect of claim 9, further comprising:
- d. a trench etched in a dielectric material formed over the substrate; and
- e. wherein the copper layer within the trench is isolated.
- 11. The interconnect of claim 9, wherein the capturing layer comprises a material selected from the group consisting of Ti, Al, Zr, Hf, Sc, and any combination thereof.
- 12. The interconnect of claim 9, wherein the blocking layer comprises a material selected from the group consisting of Ta, TaN, TiN, HfN, V, Nb, Cr, W, Mo, and any combination thereof.
- 13. The interconnect of claim 11, wherein the blocking layer comprises a material selected from the group consisting of Ta, TaN, TiN, HfN, V, Nb, Cr, W, Mo, and any combination thereof.
- 14. The interconnect of claim 9, wherein the copper layer is substantially reactive with the capturing layer at approximately room temperature.
- 15. An electrical interconnect residing over a semiconductor substrate, the interconnect comprising:
- a capturing diffusion barrier layer disposed over the substrate wherein the capturing layer has a thickness in the range of approximately 10.ANG. to 50.ANG.;
- a blocking diffusion barrier layer disposed over the capturing layer, the blocking layer being substantially unreactive with the capturing layer at approximately room temperature and the blocking layer has a thickness in the range of approximately 100.ANG. to 300.ANG.; and
- a conductive layer disposed over the blocking layer, the conductive layer being both thicker than the blocking layer and substantially unreactive with the blocking layer at approximately room temperature, the conductive layer further being substantially reactive with the capturing layer.
- 16. The interconnect of claim 15, wherein the conductive layer primarily comprises Cu.
- 17. The interconnect of claim 15, wherein the capturing layer is electrically conductive and comprises a material selected from the group consisting of Ti, Al, Zr, Hf, Sc, and any combination thereof.
- 18. The interconnect of claim 16, wherein the blocking layer is electrically conductive and comprises a material selected from the group consisting of Ta, TaN, TiN, HfN, V, Nb, Cr, W, Mo, and any combination thereof.
- 19. The interconnect of claim 15, wherein the blocking layer is substantially unreactive with both the capturing layer and the conductive layer up to a temperature of approximately 200.degree. C.
- 20. The interconnect of claim 15, wherein the blocking layer is substantially unreactive with both the capturing layer and the conductive layer up to a temperature of approximately 500.degree. C.
- 21. The interconnect of claim 15, wherein the conductive layer is substantially reactive with the capturing layer at a temperature of approximately 200.degree. C.
- 22. The interconnect of claim 15, wherein the conductive layer is substantially reactive with the capturing layer at approximately room temperature.
Parent Case Info
This is a divisional of application Ser. No. 08/555,491, filed Nov. 8, 1995, now U.S. Pat. No. 5,714,418.
US Referenced Citations (11)
Divisions (1)
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Number |
Date |
Country |
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555491 |
Nov 1995 |
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