Patent Application
20150282317
1. Field
The technology described herein relates generally to edge contacts of circuit boards, and related apparatus and methods.
2. Related Art
Many electronic systems use circuit boards to interconnect various electronic devices. A circuit board typically includes at least one substrate layer and at least one conductive layer. A substrate layer may support electronic devices disposed on the circuit board, and/or insulate conductive layers from each other. A conductive layer may include conductive traces for carrying signals on that layer of the circuit board.
Multi-layer circuit boards may include vias for carrying signals between different layers of the circuit board. A “through-hole via” typically connects the top and bottom surfaces of a circuit board, such that the via's ends are exposed at both the top and bottom surfaces of the circuit board. A “blind via” is a type of microvia which typically connects the top or bottom surface of a circuit board to an interior layer of the circuit board, such that the via's end is exposed at a top or bottom surface of the circuit board, but not both. A “buried via” is a type of microvia which typically connects interior layers of the circuit board, such that the via's ends are not exposed at the top or bottom surface of the circuit board.
A circuit board may include one or more input/output terminals. An input/output terminal may be disposed on a top or bottom surface of the circuit board, or at an edge of the circuit board. An input/output terminal disposed at an edge of a circuit board may be referred to as an “edge contact.” Conventional edge contacts are typically castellated.
Various aspects and embodiments of the disclosure are described with reference to the following figures. It should be appreciated that the figures are not necessarily drawn to scale. Items appearing in multiple figures are indicated by the same reference number in all the figures in which they appear.
In some embodiments, a circuit board is provided, comprising a plurality of layers stacked in a thickness direction, a peripheral edge having a first thickness in the thickness direction, and an edge contact disposed at the peripheral edge of the circuit board. The edge contact has a second thickness in the thickness direction. The second thickness is less than the first thickness.
In some embodiments, a method of manufacturing a circuit board is provided , comprising at least partially filling a hole with a conductive material. The hole extends through one or more layers of material. The method further comprises using the one or more layers of material to form a multilayer circuit board with at least one end of the hole covered by a layer of material, and forming an edge contact by exposing a portion of the conductive material at a peripheral edge of the multilayer circuit board.
The geometry (e.g., height, length, width, shape, etc.) of traces, vias, and/or input/output terminals may affect the quality of a circuit board's signals, such as high-frequency signals. In some applications, such as processing of sensor signals, the impact of edge contact geometry on signal quality can be significant. The inventors have recognized and appreciated that conventional techniques for forming edge contacts on circuit boards do not permit sufficient control over the geometry of the edge contact, making it difficult or impossible to maintain desired signal quality for some applications, such as sensor applications. For example, conventional edge contacts extend through the entire thickness of the circuit board, such that the thickness of the edge contact is dictated by the thickness of the circuit board, even when the thickness of the circuit board is smaller or greater than the desired thickness of the edge contact.
Thus, forming an edge contact with a thickness that is less than the thickness of the circuit board's peripheral edge may improve signal quality. The edge contact may extend to the bottom of the peripheral edge without extending to the top, or extend to the top of the peripheral edge without extending to the bottom, or extend to neither the top nor the bottom of the peripheral edge. Such an edge contact may be manufactured by forming a microvia (e.g,. buried or blind via) in a circuit board, and routing the circuit board to form the peripheral edge through the microvia.
The various aspects described above, as well as further aspects, are described in further detail below. It should be appreciated that these aspects may be used alone, all together, or in any combination of two or more, to the extent that they are not mutually exclusive.
As used herein, “circuit board” may include, but is not limited to, a printed circuit board, a printed wiring board, an etched wiring board, a printed circuit assembly, a printed circuit board assembly, circuit card, circuit card assembly, backplane, backplane assembly, or any other structure suitable for mechanically supporting and/or electrically connecting traces, pins, contacts, pads, terminals, electrical components, electronic components, optoelectronic components, electromechanical components, integrated circuits (“chips”), and/or semiconductor devices.
Edge contact 108 is disposed at a peripheral edge 120 of circuit board 100. Methods of forming edge contacts, such as edge contact 108, are described below. In some embodiments, a peripheral edge may include one or more surfaces disposed between top and bottom surfaces of a circuit board at a periphery of the circuit board. Edge contact 108 may be configured to conductively couple one or more components of circuit board 100 and an electronic component external to circuit board 100. For example, edge contact 108 may be configured to conductively couple one or more traces, vias, contacts, and/or electronic devices of circuit board 100 with an external signal carrier (e.g., conductor), a contact of another circuit board, and/or a terminal of an external electronic device. In some embodiments, edge contact 108 may be configured to communicatively couple a processing circuit disposed on circuit board 100 to a sensor signal generated external to circuit board 108. In some embodiments, edge contact 108 may be configured to communicatively couple a terminal of a sensor device disposed on circuit board 100 to a processing circuit disposed external to circuit board 100. In some embodiments, edge contact 108 may be coupled to a processing circuit configured to control a sensor circuit. In some embodiments, edge contact 108 may operate as an input terminal (e.g., a terminal that receives signals generated externally to circuit board 100 and communicates the signals to a component of circuit board 100), an output terminal (e.g., a terminal that sends a signal from circuit board 100 to a component external to circuit board 100), or as an input/output terminal (e.g., a terminal that both sends and receives signals).
As shown in
In some embodiments, an edge contact may extend between any two layers of a circuit board. In some embodiments, an edge contact may extend between any pair of layers of a circuit board other than the pair consisting of the top layer and the bottom layer of the circuit board. For example, an edge contact may extend between the top layer and any internal layer, or between the bottom layer and any internal layer, or between any two internal layers. In some embodiments, an edge contact may extend through one or more layers of a circuit board. In some embodiments, an edge contact may extend through one or more layers of a circuit board without extending through all layers of the circuit board. For example, an edge contact may be covered by a layer of the circuit board at a bottom end and exposed at a top layer of the circuit board, or be covered by a layer of the circuit board at a top end and exposed at a bottom layer of the circuit board, or be covered by a layer of the circuit board at a top end and at a bottom end.
Edge contact 108 may be manufactured, for example, by forming a buried via hole in one or more layers of a circuit board, at least partially filling the buried via hole with a conductive material, and cutting the circuit board through at least a portion of the via hole to expose the conductive material. In the embodiment of
Edge contact 208 is disposed at a peripheral edge 220 of circuit board 200. As shown in
Edge contact 208 may be manufactured, for example, by forming a blind via hole in one or more layers of a circuit board, at least partially filling the blind via hole with a conductive material, and cutting the circuit board through at least a portion of the blind via hole to expose the conductive material. In the embodiment of
Edge contact 308 may be manufactured, for example, by forming a blind via hole in one or more layers of a circuit board. In
The via hole may be plated with one or more plating materials to form plated portion 330 of edge contact 308. Plated portion 330 may include one or more conductive materials, such as copper or any suitable metallic material. In edge contact 308, plated portion 330 lines the interior of the via hole, forming a conductive plate 330b between the top and bottom of the hole. In some embodiments, conductive plate 330b may fully or partially line the interior of the via hole, forming a conductive path along the interior of the via hole.
In edge contact 308, plated portion 330 forms a border 330a at the top of edge contact 308, and a border 330c at the bottom of edge contact 308. Borders 330a and 330c may facilitate reliable electrical connections between edge contact 308 and other components of circuit board 300, such as traces. In
As shown, edge contact 308 may include a filling material 332. In some embodiments, filling material 332 may include a conductive material, such as copper, conductive epoxy, a metallic material, and/or any other suitable conductor. In some embodiments, filling material 332 may include a nonconductive material, such as nonconductive epoxy. Filling material 332 may fully or partially fill the portion of the via hole not filled by plated portion 330.
In some embodiments, plated portion 330 and/or filling material 332 may be surface plated. Surface plating may planarize the exposed surfaces of edge contact 308, increase the resistance of edge contact 308 to oxidation, and/or facilitate reliable electrical connection between edge contact 308 and other components of circuit board 300. In some embodiments, the surface plating may include electroless nickel immersion gold, solder, immersion silver, immersion tin, and/or any other material suitable for plating a via and/or an edge contact.
In
While
At step 402, a hole is formed in one or more layers of circuit board material, which may include one or more conductive layers, one or more substrate layers, and/or any other material layer(s) suitable for forming a circuit board. In the example of
At step 404, the hole is at least partially filled with one or more conductive materials. At least partially tilling the hole with one or more conductive materials may comprise plating the hole to form a plated portion (e.g., at least partially lining the hole with one or more plating materials, such as copper), and/or depositing a filling material (e.g., copper, conductive epoxy, or nonconductive epoxy) in the hole. Any suitable technique for plating the hole and/or depositing a filling material in the hole may be used, as embodiments are not limited in this regard. In some embodiments, the one or more materials at least partially filling the hole may form a via. In some embodiments, the material(s) at least partially filling the hole and one or more vias may be formed during the same circuit board fabrication step, using the same instrument(s) and/or technique(s). In the example of
At step 406, the one or more layers of material are used to form a multilayer circuit board with at least one end of the hole covered by a layer of material. In some embodiments, the one or more layers are attached to a covering layer that covers an end of the hole formed in step 402 and the via formed in step 404. In some embodiments, the one or more layers are attached to a second covering layer that covers a second end of the hole formed in step 402 and the via formed in step 404. A covering layer may include one or more substrate layers, one or more conductive layers, and/or one or more layers of any material suitable for forming a circuit board. A covering layer may be attached to the one or more layers using any suitable technique, including, but not limited to, laminating the one or more layers and the covering layer (e.g., applying pressure and heat to the one or more layers and the covering layer, such that the one or more layers and the covering layer bond to each other).
In the example of
At step 408, an edge contact is formed by exposing, at a peripheral edge of the circuit board (or at a slot or edge that will become a peripheral edge of the circuit board), a portion of the one or more conductive materials formed in the hole at step 404. In some embodiments, exposing the conductive material(s) comprises cutting the circuit board to form a slot or a peripheral edge through the hole, through the via formed in the hole, and/or through at least a portion of the conductive materials formed in the hole. A slot may include a recess or a hole in the circuit board, or a hole through the circuit board, in a direction of the thickness of the circuit board. Cutting the circuit board to form an edge or slot may be performed using any suitable instrument or technique, including, but not limited to, using a router to route the edge or slot. In the example of
At step 410, one or more exposed surfaces of the edge contact are finished (e.g., surface plated). Any suitable technique for finishing the edge contact may be used. In some embodiments, finishing the edge contact may comprise surface plating the edge contact with electroless nickel immersion gold, solder, immersion silver, immersion tin, and/or any other material suitable for plating a via. In some embodiments, finishing the one or more exposed surfaces of the edge contact and finishing a surface of a via may be performed in a same manufacturing step and/or using a same manufacturing technique.
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Some embodiments of the above-described edge contacts may provide superior signal quality, relative to conventional edge contacts. In some embodiments, the size (e.g., surface area, length, and/or width) of an edge contact may be controlled to aid in low-loss signal propagation at higher frequencies. For example, an edge contact's dimensions may be configured to reduce signal loss by reducing reflections associated with abrupt geometry changes along the signal line at interconnection sites. In some embodiments, the cross-sectional dimensions (e.g., length and/or width) of an edge contact may be configured to match the cross-sectional dimensions of one or more signal carriers (e.g., traces, vias, and/or wires) to which the edge contact is communicatively coupled. A dimension of an edge contact may “match” a corresponding dimension of a signal carrier when the difference between the edge contact's dimension and the signal carrier's corresponding dimension is less than approximately 25%, 20%, 15%, 10%, 5%, 3%, 2%, 1%, 0.1%, or 0.01%. The cross-sectional dimensions of an edge contact may “match” the corresponding cross-sectional dimensions of a signal carrier when the signal loss at the boundary between the edge contact and the signal carrier is less than approximately 3 dB, 2 dB, 1 dB, 0.5 dB, 0.1 dB, 0.05 dB, 0.01 dB, 0.005 dB, or 0.001 dB. In some embodiments, multiple edge contacts may be fabricated along an edge of a circuit board to accommodate multiple circuit interconnections including, but not limited to, differential pairs.
The above-described edge contact and manufacturing technique have been described as being suitable for sensor applications. Some embodiments are not limited in this regard. Some embodiments may, for example, additionally or alternatively be used for secure processing, data security, anti-tampering, intellectual property protection, and/or for any other suitable application.
In some embodiments, one or more edge contacts on a first circuit board may be coupled to one or more edge contacts on a second circuit board. For example, the first and second circuit boards may be disposed in a tiled configuration, with the edge contacts used for communication between the circuit boards. Any number of circuit boards may be tiled in this manner.
In some embodiments, an edge pad may be formed by routing a conductive trace to a peripheral edge of a circuit board (e.g., by cutting the circuit board to form the peripheral edge at a location which transects a conductive trace), and by forming an edge pad connected to the conductive trace. The edge pad may, for example, be formed by sputtering a conductive material (e.g., a metallic material) onto the peripheral edge at the position of the conductive trace, by pasting a conductive pad to the peripheral edge at the position of the conductive trace (e.g., with a conductive paste), or by plating a portion of the peripheral edge and etching away the plated portion to form a pad at the position of the conductive trace.
In some embodiments, a buried via hole may be filled by plating the hole and filling some or all of the remaining portion of the hole with a conductive or nonconductive material. In other embodiments, a buried via hole may be filled by filling some or all of the hole with a conductive material, without first plating the hole.
It should be understood that the various embodiments shown in the Figures are illustrative representations, and are not necessarily drawn to scale. Reference throughout the specification to “one embodiment” or “an embodiment” or “some embodiments” means that a particular feature, structure, material, or characteristic described in connection with the embodiment(s) is included in at least one embodiment, but not necessarily in all embodiments. Consequently, appearances of the phrases “in one embodiment,” “in an embodiment,” or “in some embodiments” in various places throughout the Specification are not necessarily referring to the same embodiment.
Unless the context clearly requires otherwise, throughout the disclosure, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in a sense of “including, but not limited to.” Additionally, the words “herein,” “hereunder,” “above,” “below,” and words of similar import refer to this disclosure as a whole and not to any particular portions of this disclosure. When the word “or” is used in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list; all of the items in the list; and any combination of the items in the list.
Having thus described several aspects of at least one embodiment of the technology, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the technology. Accordingly, the foregoing description and drawings provide non-limiting examples only.
