Patent Application
20230068223
The present invention relates to high power density packaging of a plurality of semiconductor power transistors in a dual side cooled package configuration with reduced thermal resistance, improved gate control signal integrity, lower material cost, and fewer required production process steps.
Semiconductor power transistors packaged in a half-bridge circuit configuration are commonly used to realize direct current (DC) to alternating current (AC) power inverter circuits, AC to DC power converter circuits, and DC to DC power converter circuits. Semiconductor power transistors used in such power conversion circuits dissipate heat. Conducting the dissipated heat out of the package in an efficient manner is important to maximize the power such semiconductor power transistors can process, while minimizing the size and cost of the semiconductor power transistor package.
Minimizing the thermal resistance between the semiconductor power transistor die and the package heat sinks can be achieved by reducing the number of material layers and material bonding layers between the semiconductor power transistor die and the package heat sinks. Reducing the number of material and material bond layers further minimizes the number of required production process steps, resulting in a lower cost package.
Improvements in semiconductor power transistor technologies have resulted in very fast transistor switching speeds on the order of tens of amperes within a few nanoseconds. Parasitic source inductances of semiconductor power transistor packages in conjunction with fast switching current transients results in transient voltage spikes opposing the controlling gate signal, which, if not mitigated, can result in significant switching performance degradation and in some cases device failures.
Solder bonds between semiconductor power transistor dies and substrates are generally limiting the package reliability when subjected to thermal cycling induced stresses. Using alternative bonding methods with improved thermal cycling durability is desirable to improve the overall package reliability.
Stray inductances within semiconductor power transistor packages and connections to external circuits can cause overvoltage transients during fast transistor switching events. Such overvoltage transients can cause the semiconductor power transistors to fail if not mitigated. While the transistor switching speed can be reduced to suppress such overvoltage transients by increasing gate resistances, such reduction of transistor switching speed increases switching losses, which is not desirable.
Paralleling multiple semiconductor power transistors can cause resonant oscillations of the gate signals to the parallel driven transistors. Such oscillations, if not mitigated, can result in large variations in dynamic current sharing and junction temperature variations between the parallel transistors leading to loss of performance and possible device failures.
An aspect of the present invention is to provide embodiments to solve one or more of the above problems. The present disclosure, which includes improvements to packaging and cooling of semiconductor power transistors, describes embodiments that allow the power semiconductor switches to operate at optimal performance, power density and cost.
In an embodiment, the present invention provides an integrated semiconductor power transistor package which includes a half-bridge electrical circuit comprising a negative voltage outer terminal of a high-side switch which is connected in series with a positive voltage outer terminal of a low-side switch, a first substrate, a second substrate, a first plurality of vertical spacers, a second plurality of vertical spacers, and an encapsulant. Each of the high side switch and the low-side switch comprises a plurality semiconductor power transistor dies which are connected electrically parallel. The first substrate comprises a cladding layer which is sinter bonded to at least a first one of the plurality of semiconductor power transistor dies so as to define the low-side power switch. The second substrate is arranged parallel to the first substrate. The second substrate comprises a first cladding layer which is sinter bonded to at least a second one of the plurality of semiconductor power transistor dies so as to define the high-side power switch, and a second cladding layer. The first plurality of vertical spacers sinter bonds the at least the first one of the plurality of semiconductor power transistor dies which defines the low-side power switch on the first substrate to the second cladding layer of the second substrate. The second plurality of vertical spacers sinter bonds the at least the second one of the plurality of semiconductor power transistor dies which defines the high-side power switch on the second substrate to the cladding layer of the first substrate. The encapsulant encapsulates at least a cavity between the first substrate and the second substrate.
The present invention is described in greater detail below on the basis of embodiments and of the drawings in which:
Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows. It should thereby be appreciated that in the drawings like reference numerals are used to identify like elements, wherein showings therein are only for purposes of illustrating embodiments of the present invention and not for purposes of limiting the scope of protection of the present invention.
The present invention relates to packaging of semiconductor power transistors and apparatus and methods used to maximize power density while minimizing the thermal resistance between the packaged transistors and external heat sinks.
The present invention, which describes improvements to packaging and cooling structures, describe embodiments that allow the packaged semiconductor power transistors to be more efficient, to be more reliable, to have a higher power density, and to be more cost effective.
In certain embodiments, the package may include diode structures 110a and 130a comprising a plurality of semiconductor diode dies which are connected in parallel with the high-side power switch 110 and low-side power switch 130, respectively.
In certain embodiments, the MOSFET or IGBT transistor structure may be formed from silicon, silicon carbide, gallium nitride, another III-V semiconductor, or other semiconductor materials.
Certain embodiments of the present inventions can be used to realize direct current (DC) to alternating current (AC) power inverter circuits, AC to DC power converter circuits, and DC to DC power converter circuits. Such power conversion circuits generate heat as a byproduct. Most of this heat is generated by the semiconductor power transistors within the package. Certain embodiments of the present invention provide more efficient and more uniform ways to dissipate heat through both the top and bottom side of the package.
Vgn=Vdd-Vind=Vdd-Lp×dtdi
To mitigate the influence of parasitic inductance Lp 330 on the gate control voltage Vgn 310d, an alternate circuit 300b having a Kelvin gate return signal 350 is directly connected to the negative power terminal of the power semiconductor power transistor. Certain exemplary embodiments of the present invention include package interconnect structures that electrically implement Kelvin gate return signals 350. An exemplary embodiment 300c of the present invention implements structures to realize a common gate control signal 320c for a plurality of parallel connected semiconductor power transistor dies 200. Circuit 300c schematically exemplarily illustrates three parallel connected semiconductor power transistor dies 200. Another exemplary embodiment 300d of the present invention includes package interconnect structures and resistive elements 310e electrically connected in series with each of the plurality of parallel connected semiconductor power transistor dies. An advantage of the present invention is that resistive elements 310e in series with each individual semiconductor power transistor die 200 dampen voltage ripple on the gate control signal 320c caused by resonant oscillations between gate control signal terminations for such parallel connected semiconductor power transistor dies 200.
The positive power terminal pad 210 of the second instance low-side power transistor die 400b is directly bonded electrically and thermally through bonding layer 450b to the cladding layer 415c of the first substrate 41, where such cladding layer 415c forms a mid-point terminal electrical connection 160. The negative power terminal pad 220 of the low-side power transistor die 400b is bonded electrically and thermally through a vertical spacer 425b and bonding layers 430b, 420b to the cladding layer 445c, where the cladding layer 445c forms a negative voltage outer terminal electrical connection 170.
The positive power terminal pad 210 of the high-side power transistor die 400a is directly bonded electrically and thermally through a bonding layer 450a to a cladding layer 445d of the second substrate, wherein the cladding layer 445d forms a positive voltage outer terminal electrical connection 150. The negative power terminal pad 220 of the high-side power transistor die 400a is bonded electrically and thermally through a vertical spacer 425a and the bonding layers 430a, 420a to a cladding layer 415c, where the cladding layer 415c forms a mid-point terminal electrical connection 160.
In certain exemplary embodiments, the bonding layers 420a, 430a, 450a, 420b, 430b, and 450b are realized by means of sintering bonds. Sintering bonds may be formed using paste or film comprising silver, copper, platinum, palladium, gold particles, microparticles, or nanoparticles. Advantages of sintering bonds of the present disclosure compared with soldering bonds are substantial reduction in thermal cycling fatigue resulting in improved durability of bonding layers and reduction of thermal resistance resulting in improved cooling performance.
In certain embodiments the spacers 425a, 425b may be made from electrically and thermally conducting metal alloys, including copper alloys, Si filled AlMg alloys, or other alloys having requisite thermal and electrical conductivities.
In certain exemplary embodiments, wire bonding structures define electrical connections between the transistor gate terminal pad 230 of the transistor die 400b and the cladding layer 415e defining a gate control signal 320b interconnect structure and between the negative power terminal pad 220 of the transistor die 400b and the copper cladding layer 415d together defining a Kelvin gate return signal interconnect structure. Exemplary wire bonding structures correspondingly make electrical connections between the transistor gate terminal pad 230 and the negative power terminal pad 220 of the transistor 400a to the respective copper clad layers 445f and 445e on the second substrate forming gate control 320b and Kelvin return signal interconnect structures. In other embodiments, gate and power terminal pads 220, 230 of transistors 400a, 400b may be wire bonded to a lead frame pin or a lead frame pin may be directly bonded to the transistor gate terminal pad 230 and to the power terminal pad 220 without bond wires.
Heat generated by transistor 400a is partially spread and transferred through the bonding layers 450a, the inner copper clad layer 445e, the substrate core 445b, the external copper clad layer 445a, the heatsink bonding layer 410b, and is dissipated through an exemplary external heat sink 405b. Heat generated by transistor 400a is further partially spread and transferred through the bonding layer 430a, the spacer 425a, the bonding layer 420a, the inner copper clad layer 415c, the substrate core material 415b, the external copper clad layer 415a, the heatsink bonding layer 410a, and is dissipated through an exemplary external heat sink 405a. The thermal resistance from the transistor die 400a to the heatsink 405b is proportionally lower than the thermal resistance from the die 400a to the heatsink 405a. The proportionally higher thermal resistance from the die 400a to the heatsink 405a is caused by additional thermal resistances introduced by the spacer 425a and the bonding layer 420a as well as the cross-section area of the spacer 425a being smaller than the total area of die 400a. As a result of the inverted, complementary structure of the present invention, the die 400b has a proportionally lower thermal resistance to heatsink 405a than thermal resistance from the die 400b to the heatsink 405b. This complementary thermal resistance relationship results in lower concentration of heat flux and more uniform cooling performance on both heatsinks, allowing closer horizontal spacing of the dies 400a and 400b, enabling a reduced size and cost dual side cooled package for the same thermal performance. An advantage of the present invention is the reduced number of material layers and material bonding layers between the transistors 400a, 400b to the external heat sinks 405a, 405b.
In certain exemplary embodiments, the heatsinks 405a, 405b may be air cooled. In other exemplary embodiments, the heatsinks 405a, 405b may be liquid cooled. In some exemplary embodiments, the heatsinks 405a, 405b may be flat plates, finned plates, plates with microchannels, or having other microstructures. In some embodiments, the heatsinks 405a, 405b may be constructed from copper alloys, aluminum alloys, or other metallic alloys.
The heatsink bonding layers 410a, 410b may in some exemplary embodiments be formed by soldering. In certain embodiments, the bonding layers 410a, 410b may be sinter formed using paste or film comprising silver, copper, platinum, palladium, or gold particles, microparticles, or nanoparticles. In other embodiments, the bonding layers 410a, 410b may be formed by thermally conductive adhesives. In other embodiments, the bonding layers 410a, 410b may be formed by thermal interface materials including thermal pastes and thermal pads.
The encapsulant 460 encases at least the cavity formed between the first and second substrates. An advantage of the present invention is that the encapsulant 460 provides mechanical structural support, protection against moisture and pollutant ingress, and electrical isolation of the power semiconductor transistors and package internal interconnect structures. In some exemplary embodiments, the encapsulant 460 may comprise a polymer such as an epoxy resin, polyester, polyurethane, or other plastics.
An exemplary gate control signal 320c interconnect structure comprises a copper lead frame pin 505a bonded to a copper cladding layer shape 520, which is further separately bonded by a wire 560b, 570b, 580b, 590b to gate terminal pads 230 for each individual semiconductor power transistor die 200.
An exemplary Kelvin gate interconnect structure for a Kelvin gate return signal 360 comprises a copper lead frame pin 505b bonded to a copper cladding layer shape 510, which is further separately bonded by a wire 560a, 570a, 580a, 590a to the negative power terminal pads 220 for each individual semiconductor power transistor die instance.
The semiconductor power transistor die negative power terminals 220 are schematically illustrated as 560c, 570c, 580c, and 590c.
The top surface of the spacer 425b bonded to the negative power terminal pad of each semiconductor power transistor die instance are illustrated by reference numerals 560d, 570d, 580d, and 590d.
An exemplary interconnect structure of a mid-point terminal 160 comprises a power lead frame pin 505d bonded to a copper cladding layer shape 530, which is further bonded to the positive power terminal pad of each semiconductor power transistor die instance. An advantage of the present invention is large contiguous surface area of copper cladding layer 530, which minimizes impedance resulting in lower thermal conduction losses, minimizes stray inductance between transistor die in the high-side power switch 110 and the low-side power switch 130 improving the switching performance, and further improves the structural rigidity of the package.
In another exemplary embodiment of the present invention, copper lead frame pin 505c bonded to copper cladding layer 530 provide an external electrical sensing connection to the mid-point terminal 160 for implementation of external overcurrent detection circuits.
An exemplary interconnect structure of a gate control signal 320c comprises a copper lead frame pin 605a bonded to a copper cladding layer shape 620, which is further separately bonded by a wire 660b, 670b, 680b, and 690b to the transistor gate terminal pads 230 for each individual semiconductor power transistor die 200.
An exemplary interconnect structure of a Kelvin gate return signal 360 comprises a copper lead frame pin 605b bonded to copper cladding layer shape 610, which is further separately bonded by a wire 660a, 670a, 680a, and 690a to negative power terminal pads 220 for each individual semiconductor power transistor die instance.
The semiconductor power transistor negative power terminals are schematically illustrated as 660c, 670c, 680c, and 690c.
The top surface of spacer 425a bonded to the negative power terminal pad of each semiconductor power transistor die instance are illustrated by 660d, 670d, 680d, and 690d.
An exemplary interconnect structure of a positive voltage outer terminal 150 comprises a power lead frame pin 605d bonded to a copper cladding layer shape 630. An exemplary negative voltage outer terminal 170 interconnect structure comprises a power lead frame pin 605e bonded to a copper cladding layer shape 640, which is further bonded to the positive power terminal pad of each individual semiconductor power transistor die instance. An advantage of the structure of the present invention is the close parallel proximity of the copper cladding layers 630 and 640 corresponding to the positive voltage outer terminal 150 and the negative voltage outer terminal 170 of the half-bridge electrical circuit configuration 100. This parallel proximity suppresses parasitic loop inductance across positive voltage outer terminal 150 and the negative voltage outer terminal 170, which reduces switching transient voltage overshoot amplitudes.
Exemplary embodiment copper lead frame pin 605c bonded to copper cladding layer shape 630 provides an external electrical sensing connection to the positive voltage outer terminal for implementation of external overcurrent detection circuits.
An advantage of the present invention is realized by having one of the power lead frame pins 505d bonded to the first substrate and the other two power lead frame pins 605d and 605e bonded to the second substrate. The width of power lead frame pins and number of power lead frame pins in the same plane drive the overall width of the package. The overall width of the package can be reduced by separating the three power lead frames in two parallel planes, one plane per substrate. The cost of two lead frames doubles the copper lead frame material cost. In comparison, the material cost of each substrate is more than 30 times higher per unit area than the material cost of each copper lead frame. A reduction of package width allowed by the present invention improves overall power density and reduces overall material cost.
The plane of cross section cuts through the semiconductor power transistor die 200 comprising the high-side power switch 110. The plane of cross section cuts through the semiconductor power transistor dies 200 comprising the low-side power switch 130.
Exemplary power lead frame pin 505d is bonded with a bonding layer 712 to a copper cladding layer shape 630 on the first substrate. Exemplary power lead frame pins 605d and 605e are bonded with bonding layers 714 and 724, respectively, to copper cladding layer shapes 630, 640 of the second substrate. Exemplary copper lead frame pin 505c is bonded through a bonding layer 715 to a copper cladding layer shape 530 on the second substrate. A copper lead frame pin 605c is bonded through a bonding layer 725 to the copper cladding layer shape 630 on the second substrate. In certain exemplary embodiments of the present invention, lead frame pin bonding layers 712, 714, 715, 724, and 725 may be formed by soldering, ultrasonic welding, or in certain embodiments, sintering bonds may be formed using paste or film comprising silver, copper, platinum, palladium, or gold particles, microparticles, or nanoparticles.
In one exemplary embodiment of the present invention, the package and lead frame pins are encapsulated by encapsulant 460 except for: the lead frame pins 505c, 605c extruding beyond the encapsulant, the exposed power lead frame pin surfaces 711, 713, 723, and the external copper clad layers 415a, 445a. An advantage of the exposed large surface area power lead frame pin surfaces 711, 713, 723 is allowing for the formation of a low-impedance connection to external busbars. One exemplary embodiment of a low-impedance bonding of busbars to power lead frame pin surfaces 711, 713, 723 includes a welding bond. In some exemplary embodiments of the present invention, such welding bonds may be formed using ultrasonic welding, laser welding, or electron-beam welding.
The height of spacers 425a and 425b is determined by the required minimum electrical clearances between i) inner copper clad layer shapes (415c, 415d, 415e) of the first substrate 41 and inner copper clad layer shapes (445c, 445d, 445e, 4451) of the second substrate 42, and ii) the power lead frame pin 505d on the first substrate and the power lead frame pins 605d and 605e on the second substrate. The minimum electrical clearance depends on the maximum operating voltage for the specific application and the voltage withstand properties of the encapsulant 460 material. In one exemplary embodiment, spacers 425a and 524b have a height of 2.4 mm. The height of the spaces 425a, 425b will generally be between 1.5 mm and 5.0 mm.
Another exemplary embodiment of the present invention includes a temperature sensing device 850 having a first terminal bonded to copper cladding layer shape 840a being further bonded to a lead frame pin 830a and having a second terminal bonded to a copper cladding layer shape 840b being further bonded to a lead frame pin 830b. In other exemplary embodiments, the first terminal may be sinter bonder to copper cladding layer shape 840a and the second terminal may be wire bonded to copper cladding layer shape 840b. In certain exemplary embodiments, such temperature sensing device 850 may be a thermistor, thermocouple, or resistance-temperature-detector (RTD). Such temperature sensing device 850 can be used by external circuitry to monitor the package internal temperature for diagnostics, thermal power curtailing control, or thermal shutdown control.
Certain exemplary embodiments of the present invention may further comprise exemplary energy absorbing snubber devices 800 used to suppress transient voltage oscillations induced by switching of the semiconductor power transistor dies 200. Energy absorbing snubber devices are electrically connected between the positive voltage outer terminal 150 and the negative voltage outer terminal 170. An exemplary embodiment of a snubber device may be a resistive-capacitive (RC) snubber device 800 comprising a capacitor 800a and resistor 800c connected in series implemented as a semiconductor die having its bottom surface corresponding to its outer capacitor terminal 800b and its top surface corresponding to its outer resistor terminal 800d. In certain exemplary embodiments of the present invention, a plurality of such snubber dies 820a and 820b is provided, each die having its respective terminal 800b solder or sinter bonded to a copper clad layer shape 630, and terminal 800d bonded to a copper cladding layer shape 640 using a plurality of bond wires 825. Advantages of the energy absorbing snubber device 800 in the present invention include reduced voltage stresses on the semiconductor power transistors and reduced high frequency voltage oscillations.
In the foregoing specifications, the disclosure has been described with reference to specific embodiments. However, as one skilled in the art will appreciate, various embodiments disclosed herein can be modified or otherwise implemented in various other ways without departing from the spirit and scope of the disclosure. This description is accordingly to be considered as illustrative and is for the purpose of teaching those skilled in the art the manner making and using various embodiments of the disclosed invention. It is to be understood that the forms of disclosure herein shown and described are to be takes as representative embodiments. Equivalent elements, materials, processes or steps may be substituted for those representatively illustrated and described herein. Certain features of the disclosure may moreover be utilized independently of the use of other features, all as would be apparent to one skilled in the art after having the benefit of this description of the disclosure.
As used herein, the terms “comprises”, “comprising”, “includes”, “including”, “has”, “having” or any contextual variants thereof, are intended to cover a non-exclusive inclusion. For example, a process, product, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such process, product, article, or apparatus. Further, unless expressly stated to the contrary, “or” refers to an inclusive or and not to an exclusive or. For example, a condition “A or B” is satisfied by any of the following: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B is true (or present).
It will also be appreciated that one or more of the elements depicted in the drawings/figures can also be implemented in a more separated or integrated manner, or even removed or rendered as inoperable in certain cases, as is useful in accordance with a particular application. Reference should also be had to the appended claims.
This application is a U.S. National Phase application under 35 U.S.C. § 371 of International Application No. PCT/US2020/018713, filed on Feb. 19, 2020. The International Application was published in English on Aug. 26, 2021 as WO 2021/167596 A1 under PCT Article 21(2).
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US20/18713 | 2/19/2020 | WO |
