Patent Application
20070210297
1. Field of the Invention
Embodiments of the present invention refer to an electrical structure, a memory with a memory cell comprising a programmable structure, a method of fabricating an electrical structure on a substrate, and a method for fabricating memory on a substrate.
2. Description of the Related Art
Memory cells comprising a solid electrolyte material are well known as programmable metallization memory cells (PMC memory cells). Memory devices including such PMC memory cells are known as conductive bridging random access memory devices (CBRAM). Storing of different states in a PMC memory cell is based on the development or diminishing of a conductive path in the electrolyte material between electrodes based on an applied electric field. Although the electrolyte material may typically have a high resistance, the conductive path between electrodes may be adjusted to lower resistance. Thus, the PMC memory cell may be set to different states corresponding to the resistance of the PMC memory cell. Typically, both states of the PMC memory cell are sufficiently time-stable in such a way that data may permanently be stored.
A PMC memory cell is operated by applying a positive or a negative voltage to the solid electrolyte of the PMC memory element. In order to store data within the PMC memory cell, the PMC memory cell is brought to a programmed state by applying a suitable programming voltage to the PMC memory cell which results in the development of the conductive path in the electrolyte material and therefore setting the PMC memory cell to a first state with low resistance. In order to store a second state, a PMC memory cell with high resistance, an erase voltage has to be supplied in such a manner that the resistance of the PMC memory cell changes back to a high resistance which refers to an erased state. To read from a PMC memory cell, a read voltage is applied that is lower than the programming voltage. With the read voltage, a current through the resistance of the PMC memory element is detected and associated with the lower or higher resistance state of the PMC memory cell.
Embodiments of the present invention provide an improved electrical structure, an improved programmable structure, an improved memory, an improved method of fabricating an electrical structure on a substrate and an improved method of fabricating a memory on a substrate.
More particularly, embodiments of the invention provide an electrical structure with a solid state electrolyte layer and an electrode layer, whereby at an interface of the solid state electrolyte layer and the electrode layer a layer region is disposed with a higher concentration of oxygen than in the electrical layer and the solid state electrolyte layer.
A further aspect of the present invention refers to a programmable structure with an electrical structure, the electrical structure comprising a solid state electrolyte layer and an electrode layer disposed on the solid state electrolyte layer. At an interface of the solid state electrolyte layer and the electrode layer a layer region with an increased oxygen concentration is disposed.
A further aspect of the present invention refers to a memory with a memory cell comprising a programmable structure with an electrical structure comprising a substrate with a solid state electrolyte layer, an electrode layer on the solid state electrolyte layer and at an interface between the solid state electrolyte layer and the electrode layer a layer region with an increased concentration of oxygen is disposed.
The invention refers to a method of fabricating an electrical structure on a substrate, whereby between a first layer made of solid state electrolyte material and a second layer made of an electrode material, at an interface a layer region is generated by depositing oxygen. In the layer region an increased oxygen concentration is formed.
A further aspect of the present invention refers to a method of fabricating a memory on a substrate with the steps of processing front end of line processes, fabricating a memory cell with a solid state electrolyte layer, an electrode layer and a layer region with an increased oxygen concentration at an interface of the solid electrolyte layer and the electrode layer. Then the memory is processed with front end of line processes.
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
Embodiments of the present invention provide an electrical structure, a programmable electrical structure, a memory with a memory cell comprising a programmable structure, a method of fabricating an electrical structure on a substrate and a method of fabricating a memory with a memory cell.
The present invention may be described in terms of various functional components. It should be appreciated that such functional components may be realized by any number of hardware or structural components configured to conform the specified functions. For example, the present invention may employ various integrated components comprised of various electrical devices, in example resistors, transistors, capacitors, diodes and such like, the values of which may be suitably configured for various intended purposes. In addition, the present invention may be practiced in any integrated circuit application where an improved electrical structure is desired. Such general applications which may be appreciated by those skilled in the art in light of the present disclosure are not described in detail. Further, it should be noted that while various components may be suitably coupled or connected to other components within exemplary circuits, such connections and couplings can be realized by varied connections between components and by connections through other components and devices located in between.
The present invention generally relates to an electrical structure with a substrate, a solid state electrolyte layer, an electrode layer comprising metal, the electrode layer being disposed on the solid state electrolyte layer, whereby at an interface region of the two layers, a layer region is disposed comprising a higher oxygen concentration than in the two layers.
In a schematic view,
The electrical structure 1 shown in
The solid state electrolyte layer 3 is formed by a material that conducts ions upon application of a sufficient voltage. Suitable materials for ion conductors include polymers, glasses and semiconductor materials. In one exemplary embodiment of the invention, the solid state electrolyte layer 3 is formed by a chalcogenide material. A chalcogenide material may include compounds of sulfur, selenium and tellurium such as GeSe, AsS, GeAsTe, AlGeAsTe, GeTeSb among others in various compositions. The solid state electrolyte layer 3 may also suitably include dissolved and/or dispersed conductive material. For example, the solid state electrolyte layer 3 may comprise a solid solution that includes dissolved metals and/or metal ions. The chalcogenide materials including silver, copper, combinations of these materials, or similar materials could be used for the solid state electrolyte layer 3.
The electrode layer 2 and the second electrode layer 4 may be formed by any suitable conductive material. For example, the electrode layer 2 and the second electrode layer 4 may be formed by doped polysilicon material or metal. In accordance with one exemplary embodiment of the present invention, one of the electrode layers, particular in this example the electrode layer 2 is formed by a material including a metal that dissolves in ion conductors when sufficient bias is applied across the electrode 2 and the second electrode layer 4. In this example the second electrode 4 is made of material that is relatively inert and does not dissolve by applying a bias voltage on the electrical structure 1. The electrode layer 2 may function as an anode during a write operation and be comprised of a material including silver that dissolves in the electrolyte layer. Depending on the embodiment, the electrode layer 2 may comprise copper. The second electrode 4 may be a cathode during the write operation and be comprised of an inert material such as tungsten, nickel, molybdenum, platinum, metal silicides, or similar materials.
Depending on the embodiment of the electrical structure, the solid state electrolyte layer 3 may at least comprise a chalcogenide material. For example, the electrolyte layer may comprise selenium and germanium. In a further embodiment, the electrolyte layer may comprise sulfur and germanium.
In one embodiment an interface region, layer region 7, may exist. The layer region 7 may contain a higher oxygen concentration compared to the solid state electrolyte layer 3 and the electrode layer 2.
The layer region 7 may reside within the solid state electrolyte layer 3 or in the electrode layer 2. In a further embodiment, the layer region 7 may be reside within both the solid state electrolyte layer 3 and the electrode layer 2. The layer region 7 is at least adjacent to the interface of the solid state electrolyte layer and the electrode layer. The layer region 7 comprises an oxygen concentration that is at least 10% higher than in the solid state electrolyte layer 3 outside of the layer region 7 and in the electrode layer 2 outside the layer region.
In a further embodiment, the oxygen concentration in the layer region 7 is 5% higher than outside the layer region 7 in the solid state electrolyte layer 3 and outside the layer region 7 in the electrode layer 2.
The higher oxygen concentration of layer region 7 improves the thermal stability of the interface between the solid state electrolyte layer 3 and the electrode layer 2. The layer region 7 with the higher oxygen concentration reduces the diffusion of metal ions from the electrode layer 2 into the solid state electrolyte layer 3. Therefore, the possibility of generating a short circuit in the solid state electrolyte layer 3 is decreased. Additionally, the possibility of degrading the structure in example the lattice of the electrode layer 2 is reduced. Therefore, recrystallization may be embedded.
In the electrical structure 1 a conductive path 5 is generated when a bias larger than a threshold voltage is applied across the solid state electrolyte layer 3. The electrical properties of the electrical structure 1 are changed to a durable conductive path. If a voltage larger than the threshold voltage is applied to the electrical structure 1, conductive ions within the solid state electrolyte layer 3 start to migrate and form a region having an increased conductivity compared to the conductor at or near the more negative of either the electrode layer 2 or the second electrode layer 4. As the conductive region forms the conductive path 5, the resistance between the electrode layer 2 and the second electrode layer 4 decreases and other electrical properties may also change. If the same voltage is applied in reverse, the conductive path 5 will dissolve back into the solid state electrolyte layer 3 and the electrical structure 1 will return to a high resistance (e.g., an erased state).
The basic reaction is if a higher voltage is applied to the solid state electrolyte layer 3, a redox reaction at the second electrode layer 4 drives metal ions from the reactive electrode layer 2 into the solid state electrolyte layer 3. Therefore, within the electrolyte layer 3, metal-rich clusters are formed. The result is a conductive path 5 that occurs between the electrode layer 2 and the second electrode layer 4. If a reverse voltage is applied to the electrical structure 1, the metal-rich clusters are dissolved and the conductive path 5 is degraded.
If the programmed state of the electrical structure 1 is to be sensed or read, a sensing voltage VS, that is lower than the threshold voltage VT, is applied to the electrical structure 1. For example, the sensing voltage VS may be about 0.1 V. Due to the sensing voltage VS, a working current Iw flows through the electrical structure 1. Without the previous programming operation, no current would flow through the electrical structure 1 when a sensing voltage VS is applied. To erase the program state, a lower voltage, for example a negative voltage, is applied to the electrode layer 2. This voltage may start at 0 V, and proceed to an erase voltage VE, for example a negative voltage of about −0.1 V. In response to the negative voltage a negative current flows through the electrical structure 1. When the negative voltage drops below the erase voltage VI, for example below −0.1 V, the current recedes to 0 A. The electrical structure 1 again has a high resistance, as it did prior to the programming operation.
The sensed program state of the memory cell 8 refers to a program data and the data is output by output units of the memory 12. Additionally, data may be stored in the memory 12 by input units that are connected with the bit lines 14.
FIGS. 4 to 7 depict a first method for producing an electrical structure 1.
The electrical structure 1 may be a particular type of memory, i.e. a DRAM, a SRAM, a PROM, an EEPROM or a flash memory.
A memory 12 is fabricated using a substrate 6 and processing controlling units, decoder units, sensing units during a front end of line process. During the front end of line process high temperatures are generated, whereby active semiconductor elements such as transistors are formed in the substrate using layer depositing processes, ion implantations, diffusion processes and annealing processes. The substrate may be a wafer, in particular a semiconductor wafer.
Next, as shown in
Next, an upper layer of the solid state electrolyte layer 3 is sputtered back in an oxygen atmosphere, whereby a layer region 7 is formed with an oxygen concentration 18 in an upper portion of the solid state electrolyte layer 3 as shown in
Additionally, as seen in
The electrical structure 1 may be processed to a memory cell and a memory, i.e. a DRAM may be produced using back end of line processes.
Depending on the embodiment, the electrical structure 1 may also be processed producing other devices, i.e. an electrical circuit.
In
A back end of line processes may be used with the electrical structure 1 of
Next, as shown in
In a further process step, the electrical structure 1 of
In a further thermal heating process, the electrical structure 1 is heated up and the oxygen generates a layer region 7 at the interface of the electrode layer 2 and the solid state electrolyte layer 3 as shown in
The thickness of the layer region 7 may be enlarged by raising the partial pressure of the oxygen ambient during the bias sputtering or increasing the process time for the bias sputtering. Additionally, using the reactive sputter process for depositing the oxygen, the thickness of the region layer 7 may be enlarged by increasing the partial pressure of the oxygen during the reactive sputter process.
In a further embodiment, the memory may be produced as a conductive bridging random access memory (CBRAM) including a programmable metallization cell with the electrical structure 1. The layer region 7 may reduce the negative impact of thermal processes in particular when using a back end of line process that may use temperatures up to 400 and 450° C.
In a further embodiment, the electrode layer 2 may include copper or be made of copper.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
