Patent Application
20250054837
This disclosure relates to electronic device cooling structures. Some embodiments relate to directly bonded structures.
Cooling structures may be disposed over and bonded to semiconductor elements (such as integrated device dies) and utilize a liquid or coolant to be flowed through cavities or channels within the cooling structures. The cooling structures can be bonded to the semiconductor elements or integrated device dies to be cooled. Pumps can be used to help facilitate the flow of liquid through the cooling structure.
These and other features, aspects, and advantages of the disclosure are described with reference to drawings of certain embodiments, which are intended to illustrate, but not to limit, the present disclosure. It is to be understood that the accompanying drawings, which are incorporated in and constitute a part of this specification, are for the purpose of illustrating concepts disclosed herein and may not be to scale.
Like reference numbers are used to refer to like features throughout the description and drawings.
Although several embodiments, examples, and illustrations are disclosed below, it will be understood by those of ordinary skill in the art that the inventions described herein extend beyond the specifically disclosed embodiments, examples, and illustrations and include other uses of the inventions and obvious modifications and equivalents thereof. Embodiments of the inventions are described with reference to the accompanying figures, wherein like numerals refer to like elements throughout. The terminology used in the description presented herein is not intended to be interpreted in any limited or restrictive manner simply because it is being used in conjunction with a detailed description of some specific embodiments of the inventions. In addition, embodiments of the inventions can comprise several novel features and no single feature is solely responsible for its desirable attributes or is essential to practicing the inventions herein described.
As feature sizes shrink, density increases, and more functionality is brought onto single semiconductor chips, there is an increasing need for efficient heat extraction. Liquid cooling has long been one option for cooling semiconductor chips. However, there are serious limitations to current technologies. For example, often, liquid cooling solutions are deployed relatively far from the chip itself. For example, a liquid cooling solution can be provided on top of a heat sink or heat spreader. It is possible to bring liquid cooling closer to the semiconductor chip itself, but there are significant complications.
Inadequate cooling of semiconductor devices can lead to decreased performance, increased errors, decreased lifespan, and so forth. Providing adequate cooling can be especially challenging for semiconductor devices made using advanced processing nodes, where features can be densely packed together, resulting in large heat production in a relatively small area. Accordingly, there is a need for improved cooling solutions.
According to some embodiments herein, heat transport away from a semiconductor chip can be improved via spraying liquid onto the backside of the chip. According to some embodiments, liquid flow can be facilitated using multiple spray nozzles (also referred to herein as spray jets), multiple channels, or both. In some embodiments, a plurality of spray jets can be provided. In some embodiments, the spray jets can be arranged in a regular pattern. In some embodiments, the spray jets may be unevenly distributed. For example, there can be an increased density of spray jets over areas of the semiconductor chip that are likely to produce the most heat.
In some embodiments, a cooling structure can comprise one or more layers. In some embodiments, each layer can be formed on a different substrate. In some embodiments, the substrates can be directly bonded to one another. In some embodiments, the channel structure can be directly bonded to a semiconductor chip. In some embodiments, wafer to wafer bonding can be used. In some embodiments, die to wafer bonding can be used. In some embodiments, die to die bonding can be used. In some embodiments, a combination of wafer to wafer, die to wafer, and/or die to die bonding can be used.
A channel structure can offer many advantages. If large, open chambers are used, structural integrity can be compromised. For example, if subjected to high pressures, cracking or breaking can occur, which can result in less efficient cooling or, in some cases, render a device inoperable. This issue can be mitigated to some extent by maintaining relatively low flow rates and pressures, but cooling ability can be limited as a result of the relatively slow flow and long time that liquid is contact with semiconductor chip. Channels can offer structural reinforcement, enabling higher pressure. In some embodiments, the layers defining the channels can be directly bonded to the semiconductor die without an adhesive. In addition to providing structural support, the channels can provide a degree of thermal isolation, which can reduce the transport of heat from one area of the semiconductor chip to another via the cooling liquid.
In some embodiments, a pump can be used to flow liquid into a cooling structure. In some embodiments, a pump can be used to remove liquid from the cooling structure. As shown in
Various embodiments disclosed herein relate to directly bonded structures in which two or more elements can be directly bonded to one another without an intervening adhesive. Such processes and structures are referred to herein as “direct bonding” processes or “directly bonded” structures. Direct bonding can involve bonding of one material on one element and one material on the other element (also referred to as “uniform” direct bond herein), where the materials on the different elements need not be the same, without traditional adhesive materials. Direct bonding can also involve bonding of multiple materials on one element to multiple materials on the other element (e.g., hybrid bonding).
In some implementations (not illustrated), each bonding layer has one material. In these uniform direct bonding processes, only one material on each element is directly bonded. Example uniform direct bonding processes include the ZIBOND® techniques commercially available from Adeia of San Jose, CA. The materials of opposing bonding layers on the different elements can be the same or different, and may comprise elemental or compound materials. For example, in some embodiments, nonconductive bonding layers can be blanket deposited over the base substrate portions without being patterned with conductive features (e.g., without pads). In other embodiments, the bonding layers can be patterned on one or both elements, and can be the same or different from one another, but one material from each element is directly bonded without adhesive across surfaces of the elements (or across the surface of the smaller element if the elements are differently-sized). In another implementation of uniform direct bonding, one or both of the nonconductive bonding layers may include one or more conductive features, but the conductive features are not involved in the bonding. For example, in some implementations, opposing nonconductive bonding layers can be uniformly directly bonded to one another, and through substrate vias (TSVs) can be subsequently formed through one element after bonding to provide electrical communication to the other element.
In various embodiments, the bonding layers 108a and/or 108b can comprise a non-conductive material such as a dielectric material or an undoped semiconductor material, such as undoped silicon, which may include native oxide. Suitable dielectric bonding surface or materials for direct bonding include but are not limited to inorganic dielectrics, such as silicon oxide, silicon nitride, or silicon oxynitride, or can include carbon, such as silicon carbide, silicon oxycarbonitride, low K dielectric materials, SiCOH dielectrics, silicon carbonitride or diamond-like carbon or a material comprising a diamond surface. Such carbon-containing ceramic materials can be considered inorganic, despite the inclusion of carbon. In some embodiments, the dielectric materials at the bonding surface do not comprise polymer materials, such as epoxy (e.g., epoxy adhesives, cured epoxies, or epoxy composites such as FR-4 materials), resin or molding materials.
In other embodiments, the bonding layers can comprise an electrically conductive material, such as a deposited conductive oxide material, e.g., indium tin oxide (ITO), as disclosed in U.S. Provisional Patent Application No. 63/524,564, filed Jun. 30, 2023, the entire contents of which is incorporated by reference herein in its entirety for providing examples of conductive bonding layers without shorting contacts through the interface.
In direct bonding, first and second elements can be directly bonded to one another without an adhesive, which is different from a deposition process and results in a structurally different interface compared to that produced by deposition. In one application, a width of the first element in the bonded structure is similar to a width of the second element. In some other embodiments, a width of the first element in the bonded structure is different from a width of the second element. The width or area of the larger element in the bonded structure may be at least 10% larger than the width or area of the smaller element. Further, the interface between directly bonded structures, unlike the interface beneath deposited layers, can include a defect region in which nanometer-scale voids (nanovoids) are present. The nanovoids may be formed due to activation of one or both of the bonding surfaces (e.g., exposure to a plasma, explained below).
The bond interface between non-conductive bonding surfaces can include a higher concentration of materials from the activation and/or last chemical treatment processes compared to the bulk of the bonding layers. For example, in embodiments that utilize a nitrogen plasma for activation, a nitrogen concentration peak can be formed at the bond interface. In some embodiments, the nitrogen concentration peak may be detectable using secondary ion mass spectroscopy (SIMS) techniques. In various embodiments, for example, a nitrogen termination treatment (e.g., exposing the bonding surface to a nitrogen-containing plasma) can replace OH groups of a hydrolyzed (OH-terminated) surface with NH2 molecules, yielding a nitrogen-terminated surface. In embodiments that utilize an oxygen plasma for activation, an oxygen concentration peak can be formed at the bond interface between non-conductive bonding surfaces. In some embodiments, the bond interface can comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. The direct bond can comprise a covalent bond, which is stronger than van Der Waals bonds. The bonding layers can also comprise polished surfaces that are planarized to a high degree of smoothness.
In direct bonding processes, such as uniform direct bonding and hybrid bonding, two elements are bonded together without an intervening adhesive. In non-direct bonding processes that utilize an adhesive, an intervening material is typically applied to one or both elements to effectuate a physical connection between the elements. For example, in some adhesive-based processes, a flowable adhesive (e.g., an organic adhesive, such as an epoxy), which can include conductive filler materials, can be applied to one or both elements and cured to form the physical (rather than chemical or covalent) connection between elements. Typical organic adhesives lack strong chemical or covalent bonds with either element. In such processes, the connections between the elements are weak and/or readily reversed, such as by reheating or defluxing.
By contrast, direct bonding processes join two elements by forming strong chemical bonds (e.g., covalent bonds) between opposing nonconductive materials. For example, in direct bonding processes between nonconductive materials, one or both nonconductive surfaces of the two elements are planarized and chemically prepared (e.g., activated and/or terminated) such that when the elements are brought into contact, strong chemical bonds (e.g., covalent bonds) are formed, which are stronger than Van der Waals or hydrogen bonds. In some implementations (e.g., between opposing dielectric surfaces, such as opposing silicon oxide surfaces), the chemical bonds can occur spontaneously at room temperature upon being brought into contact. In some implementations, the chemical bonds between opposing non-conductive materials can be strengthened after annealing the elements.
As noted above, hybrid bonding is a species of direct bonding in which both non-conductive features directly bond to non-conductive features, and conductive features directly bond to conductive features of the elements being bonded. The non-conductive bonding materials and interface can be as described above, while the conductive bond can be formed, for example, as a direct metal-to-metal connection. In conventional metal bonding processes, a fusible metal alloy (e.g., solder) can be provided between the conductors of two elements, heated to melt the alloy, and cooled to form the connection between the two elements. The resulting bond often evinces sharp interfaces with conductors from both elements, and is subject to reversal by reheating. By way of contrast, direct metal bonding as employed in hybrid bonding does not require melting or an intermediate fusible metal alloy, and can result in strong mechanical and electrical connections, often demonstrating interdiffusion of the bonded conductive features with grain growth across the bonding interface between the elements, even without the much higher temperatures and pressures of thermocompression bonding.
The conductive features 106a and 106b of the illustrated embodiment are embedded in, and can be considered part of, a first bonding layer 108a of the first element 102 and a second bonding layer 108b of the second element 104, respectively. Field regions of the bonding layers 108a, 108b extend between and partially or fully surround the conductive features 106a, 106b. The bonding layers 108a, 108b can comprise layers of non-conductive materials suitable for direct bonding, as described above, and the field regions are directly bonded to one another without an adhesive. The non-conductive bonding layers 108a, 108b can be disposed on respective front sides 114a, 114b of base substrate portions 110a, 110b.
The first and second elements 102, 104 can comprise microelectronic elements, such as semiconductor elements, including, for example, integrated device dies, wafers, passive devices, discrete active devices such as power switches, MEMS, etc. In some embodiments, the base substrate portion can comprise a device portion, such as a bulk semiconductor (e.g., silicon) portion of the elements 102, 104, and back-end-of-line (BEOL) interconnect layers over such semiconductor portions. The bonding layers 108a, 108b can be provided as part of such BEOL layers during device fabrication, as part of redistribution layers (RDL), or as specific bonding layers added to existing devices, with bond pads extending from underlying contacts. Active devices and/or circuitry can be patterned and/or otherwise disposed in or on the base substrate portions 110a, 110b, and can electrically communicate with at least some of the conductive features 106a, 106b. Active devices and/or circuitry can be disposed at or near the front sides 114a, 114b of the base substrate portions 110a, 110b, and/or at or near opposite backsides 116a, 116b of the base substrate portions 110a, 110b. In other embodiments, the base substrate portions 110a, 110b may not include active circuitry, but may instead comprise dummy substrates, passive interposers, passive optical elements (e.g., glass substrates, gratings, lenses), etc. The bonding layers 108a, 108b are shown as being provided on the front sides of the elements, but similar bonding layers can be additionally or alternatively provided on the back sides of the elements.
In some embodiments, the base substrate portions 110a, 110b can have significantly different coefficients of thermal expansion (CTEs), and bonding elements that include such different based substrate portions can form a heterogenous bonded structure. The CTE difference between the base substrate portions 110a and 110b, and particularly between bulk semiconductor (typically single crystal) portions of the base substrate portions 110a, 110b, can be greater than 5 ppm/° C. or greater than 10 ppm/° C. For example, the CTE difference between the base substrate portions 110a and 110b can be in a range of 5 ppm/° C. to 100 ppm/° C., 5 ppm/° C. to 40 ppm/° C., 10 ppm/° C. to 100 ppm/° C., or 10 ppm/° C. to 40 ppm/° C.
In some embodiments, one of the base substrate portions 110a, 110b can comprise optoelectronic single crystal materials, including perovskite materials, that are useful for optical piezoelectric or pyroelectric applications, and the other of the base substrate portions 110a, 110b comprises a more conventional substrate material. For example, one of the base substrate portions 110a, 110b comprises lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), and the other one of the base substrate portions 110a, 110b comprises silicon (Si), quartz, fused silica glass, sapphire, or a glass. In other embodiments, one of the base substrate portions 110a, 110b comprises a III-V single semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other one of the base substrate portions 110a, 110b can comprise a non-III-V semiconductor material, such as silicon (Si), or can comprise other materials with similar CTE, such as quartz, fused silica glass, sapphire, or a glass. In still other embodiments, one of the base substrate portions 110a, 110b comprises a semiconductor material and the other of the base substrate portions 110a, 110b comprises a packaging material, such as a glass, organic or ceramic substrate.
In some arrangements, the first element 102 can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the first element 102 can comprise a carrier or substrate (e.g., a semiconductor wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, forms a plurality of integrated device dies, though in other embodiments such a carrier can be a package substrate or a passive or active interposer. Similarly, the second element 104 can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the second element 104 can comprise a carrier or substrate (e.g., a semiconductor wafer). The embodiments disclosed herein can accordingly apply to wafer-to-wafer (W2 W), die-to-die (D2D), or die-to-wafer (D2 W) bonding processes. In W2 W processes, two or more wafers can be directly bonded to one another (e.g., direct hybrid bonded) and singulated using a suitable singulation process. After singulation, side edges of the singulated structure (e.g., the side edges of the two bonded elements) can be substantially flush (substantially aligned x-y dimensions) and/or the edges of the bonding interfaces for both bonded and singulated elements can be coextensive, and may include markings indicative of the common singulation process for the bonded structure (e.g., saw markings if a saw singulation process is used).
While only two elements 102, 104 are shown, any suitable number of elements can be stacked in the bonded structure 100. For example, a third element (not shown) can be stacked on the second element 104, a fourth element (not shown) can be stacked on the third element, and so forth. In such implementations, through substrate vias (TSVs) can be formed to provide vertical electrical communication between and/or among the vertically-stacked elements. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent one another along the first element 102. In some embodiments, a laterally stacked additional element may be smaller than the second element. In some embodiments, the bonded structure can be encapsulated with an insulating material, such as an inorganic dielectric (e.g., silicon oxide, silicon nitride, silicon oxycarbonitride, etc.). One or more insulating layers can be provided over the bonded structure. For example, in some implementations, a first insulating layer can be conformally deposited over the bonded structure, and a second insulating layer (which may include be the same material as the first insulating layer, or a different material) can be provided over the first insulating layer.
To effectuate direct bonding between the bonding layers 108a, 108b, the bonding layers 108a, 108b can be prepared for direct bonding. Non-conductive bonding surfaces 112a, 112b at the upper or exterior surfaces of the bonding layers 108a, 108b can be prepared for direct bonding by polishing, for example, by chemical mechanical polishing (CMP). The roughness of the polished bonding surfaces 112a, 112b can be less than 30 Å rms. For example, the roughness of the bonding surfaces 112a and 112b can be in a range of about 0.1 Å rms to 15 Å rms, 0.5 Å rms to 10 Å rms, or 1 Å rms to 5 Å rms. Polishing can also be tuned to leave the conductive features 106a, 106b recessed relative to the field regions of the bonding layers 108a, 108b.
Preparation for direct bonding can also include cleaning and exposing one or both of the bonding surfaces 112a, 112b to a plasma and/or etchants to activate at least one of the surfaces 112a, 112b. In some embodiments, one or both of the surfaces 112a, 112b can be terminated with a species after activation or during activation (e.g., during the plasma and/or etch processes). Without being limited by theory, in some embodiments, the activation process can be performed to break chemical bonds at the bonding surface(s) 112a, 112b, and the termination process can provide additional chemical species at the bonding surface(s) 112a, 112b that alters the chemical bond and/or improves the bonding energy during direct bonding. In some embodiments, the activation and termination are provided in the same step, e.g., a plasma to activate and terminate the surface(s) 112a, 112b. In other embodiments, one or both of the bonding surfaces 112a, 112b can be terminated in a separate treatment to provide the additional species for direct bonding. In various embodiments, the terminating species can comprise nitrogen. For example, in some embodiments, the bonding surface(s) 112a, 112b can be exposed to a nitrogen-containing plasma. Other terminating species can be suitable for improving bonding energy, depending upon the materials of the bonding surfaces 112a, 112b. Further, in some embodiments, the bonding surface(s) 112a, 112b can be exposed to fluorine. For example, there may be one or multiple fluorine concentration peaks at or near a bond interface 118 between the first and second elements 102, 104. Typically, fluorine concentration peaks occur at interfaces between material layers. Additional examples of activation and/or termination treatments may be found in U.S. Pat. No. 9,391,143 at Col. 5, line 55 to Col. 7, line 3; Col. 8, line 52 to Col. 9, line 45; Col. 10, lines 24-36; Col. 11, lines 24-32, 42-47, 52-55, and 60-64; Col. 12, lines 3-14, 31-33, and 55-67; Col. 14, lines 38-40 and 44-50; and 10,434,749 at Col. 4, lines 41-50; Col. 5, lines 7-22, 39, 55-61; Col. 8, lines 25-31, 35-40, and 49-56; and Col. 12, lines 46-61, the activation and termination teachings of which are incorporated by reference herein.
Thus, in the directly bonded structure 100, the bond interface 118 between two non-conductive materials (e.g., the bonding layers 108a, 108b) can comprise a very smooth interface with higher nitrogen (or other terminating species) content and/or fluorine concentration peaks at the bond interface 118. In some embodiments, the nitrogen and/or fluorine concentration peaks may be detected using various types of inspection techniques, such as SIMS techniques. The polished bonding surfaces 112a and 112b can be slightly rougher (e.g., about 1 Å rms to 30 Å rms, 3 Å rms to 20 Å rms, or possibly rougher) after an activation process. In some embodiments, activation and/or termination can result in slightly smoother surfaces prior to bonding, such as where a plasma treatment preferentially crodes high points on the bonding surface.
The non-conductive bonding layers 108a and 108b can be directly bonded to one another without an adhesive. In some embodiments, the elements 102, 104 are brought together at room temperature, without the need for application of a voltage, and without the need for application of external pressure or force beyond that used to initiate contact between the two elements 102, 104. Contact alone can cause direct bonding between the non-conductive surfaces of the bonding layers 108a, 108b (e.g., covalent dielectric bonding). Subsequent annealing of the bonded structure 100 can cause the conductive features 106a, 106b to directly bond.
In some embodiments, prior to direct bonding, the conductive features 106a, 106b are recessed relative to the surrounding field regions, such that a total gap between opposing contacts after dielectric bonding and prior to anneal is less than 15 nm, or less than 10 nm. Because the recess depths for the conductive features 106a and 106b can vary across each element, due to process variation, the noted gap can represent a maximum or an average gap between corresponding conductive features 106a, 106b of two joined elements (prior to anneal). Upon annealing, the conductive features 106a and 106b can expand and contact one another to form a metal-to-metal direct bond.
During annealing, the conductive features 106a, 106b (e.g., metallic material) can expand while the direct bonds between surrounding non-conductive materials of the bonding layers 108a, 108b resist separation of the elements, such that the thermal expansion increases the internal contact pressure between the opposing conductive features. Annealing can also cause metallic grain growth across the bonding interface, such that grains from one element migrate across the bonding interface at least partially into the other element, and vice versa. Thus, in some hybrid bonding embodiments, opposing conductive materials are joined without heating above the conductive materials' melting temperature, such that bonds can form with lower anneal temperatures compared to soldering or thermocompression bonding.
In various embodiments, the conductive features 106a, 106b can comprise discrete pads, contacts, electrodes, or traces at least partially embedded in the non-conductive field regions of the bonding layers 108a, 108b. In some embodiments, the conductive features 106a, 106b can comprise exposed contact surfaces of TSVs (e.g., through silicon vias).
As noted above, in some embodiments, in the elements 102, 104 of
Beneficially, the use of hybrid bonding techniques (such as Direct Bond Interconnect, or DBI®, techniques commercially available from Adeia of San Jose, CA) can enable high density of connections between conductive features 106a, 106b across the direct bond interface 118 (e.g., small or fine pitches for regular arrays).
In some embodiments, a pitch p of the conductive features 106a, 106b, such as conductive traces embedded in the bonding surface of one of the bonded elements, may be less than 40 μm, less than 20 μm, less than 10 μm, less than 5 μm, less than 2 μm, or even less than 1 μm. For some applications, the ratio of the pitch of the conductive features 106a and 106b to one of the lateral dimensions (e.g., a diameter) of the bonding pad is less than 20, or less than 10, or less than 5, or less than 3 and sometimes desirably less than 2. In various embodiments, the conductive features 106a and 106b and/or traces can comprise copper or copper alloys, although other metals may be suitable, such as nickel, aluminum, or alloys thereof. The conductive features disclosed herein, such as the conductive features 106a and 106b, can comprise fine-grain metal (e.g., a fine-grain copper). Further, a major lateral dimension (e.g., a pad diameter) can be small as well, e.g., in a range of about 0.25 μm to 30 μm, in a range of about 0.25 μm to 5 μm, or in a range of about 0.5 μm to 5 μm.
For hybrid bonded elements 102, 104, as shown, the orientations of one or more conductive features 106a, 106b from opposite elements can be opposite to one another. As is known in the art, conductive features in general can be formed with close to vertical sidewalls, particularly where directional reactive ion etching (RIE) defines the conductor sidewalls either directly though etching the conductive material or indirectly through etching surrounding insulators in damascene processes. However, some slight taper to the conductor sidewalls can be present, wherein the conductor becomes narrower farther away from the surface initially exposed to the etch. The taper can be even more pronounced when the conductive sidewall is defined directly or indirectly with isotropic wet or dry etching. In the illustrated embodiment, at least one conductive feature 106b in the bonding layer 108b (and/or at least one internal conductive feature, such as a BEOL feature) of the upper element 104 may be tapered or narrowed upwardly, away from the bonding surface 112b. By way of contrast, at least one conductive feature 106a in the bonding layer 108a (and/or at least one internal conductive feature, such as a BEOL feature) of the lower element 102 may be tapered or narrowed downwardly, away from the bonding surface 112a. Similarly, any bonding layers (not shown) on the backsides 116a, 116b of the elements 102, 104 may taper or narrow away from the backsides, with an opposite taper orientation relative to front side conductive features 106a, 106b of the same element.
As described above, in an anneal phase of hybrid bonding, the conductive features 106a, 106b can expand and contact one another to form a metal-to-metal direct bond. In some embodiments, the materials of the conductive features 106a, 106b of opposite elements 102, 104 can interdiffuse during the annealing process. In some embodiments, metal grains grow into each other across the bond interface 118. In some embodiments, the metal is or includes copper, which can have grains oriented along the 111 crystal plane for improved copper diffusion across the bond interface 118. In some embodiments, the conductive features 106a and 106b may include nanotwinned copper grain structure, which can aid in merging the conductive features during anneal. There is substantially no gap between the non-conductive bonding layers 108a and 108b at or near the bonded conductive features 106a and 106b. In some embodiments, a barrier layer may be provided under and/or laterally surrounding the conductive features 106a and 106b (e.g., which may include copper). In other embodiments, however, there may be no barrier layer under the conductive features 106a and 106b.
In some embodiments, the cooling structure 230 is directly bonded to a back side 224 of the integrated device die 218 without an intervening adhesive. In other embodiments, the cooling structure 230 can be bonded to the front side 250 of the integrated device die 218. Direct bonding the cooling structure 230 to the back side 224 of the integrated device die 218 helps achieve a fluid-tight seal, while also ensuring excellent thermal contact in comparison with intervening adhesive layers. The cooling structure 230 comprises a first element 210 disposed over and bonded to a second element 216. In some embodiments, a second side 226 of the first element 210 (bottom side in the drawings) is directly bonded to a first side 228 (upper side in the drawings) of the second element 216 without an intervening adhesive. Directly bonding the first element 210 to the second element 216 comprises creating a fluid-tight seal between the two elements 210, 216 that make up the cooling structure 230, and also ensures excellent thermal contact. In some embodiments, the first element 210 has a CTE that matches the CTE of the second element 216 of the cooling structure 230.
Although not illustrated, the skilled artisan will appreciate that directly bonded interfaces, such as the bonding interface 222 between the second side 242 of the cooling structure 230 and the back surface 224 of the integrated device dic 218, and the bonding interface 222 between second side 226 of the first element 210 and the first side 228 of the second element 216, can be provided with bonding layers as described above. The direct bonding can be uniform direct bonding or can be hybrid bonding if metallic connections (not shown) are also desired for electrical or thermal reasons. The bonding layers can form part of the pre-bonding elements and provide the surfaces to be directly bonded, and each bonding layer can comprise an inorganic dielectric as described above. At least one of the bonding surfaces for each bonding interface can be prepared for direct bonding as described above.
Although one inlet 202 and one outlet 204 are shown, the cooling structure 230 can comprise multiple inlets and/or outlets.
In
As shown in
The first channels 212 are oriented parallel to the second channels 214 in the embodiment of
As noted, the nozzles 208 represent restrictions in the flow path and can represent greater than a 20% reduction in the flow path from first channels 212 to the nozzles 208, which increase flow rate through the nozzles, and enhances the cooling effect. In other words, a ratio of the flow path surface area in the first channels 212 to the flow path surface area in the nozzles 208 can be greater than 1.2:1, such as between 2:1 and 50:1.
In some embodiments, the nozzles 208 can have straight sidewalls. In the illustrated embodiment the orifices 234 on the first sides 236 of nozzles 208 are greater in size than the orifices 234 on the second sides 238 of nozzles 208. The orifices 234 on the second sides 238 of nozzles 208 comprise a narrow opening. In some embodiments, the orifices 234 can be rectangular or circular in shape from a top-down view. In some embodiments the orifices 234 can have dimensions of a width or a diameter between about 25 μm and about 50 μm. In some embodiments, the nozzles 208 can be formed comprising sides including an angle α, where α can be an angle at or between values of about 55° and about 90°. In some embodiments where the nozzles 208 are formed with sloped sides, the height of the nozzles 208 may be in a range between approximately 3 and 8 times the size of the diameter of the orifices 234 on the second sides 238 of the nozzles 208. For example, if the diameter of the orifices 234 on the second sides 238 of the nozzles 208 is 25 μm, then the height of the nozzles 208 may be in a range between about 75 μm and 200 μm. In some embodiments, there can be 10-98% reduction in the surface area of the orifices 234 from the first sides 236 of nozzles 208 to the second sides 238 of nozzles 208.
This narrow opening can create a high pressure, enhancing the cooling effect on the integrated device die 218. After exiting the nozzles 208, the liquid flows into the second channels 214 in the second element 216 of the cooling structure 230. The second channels 214 provide defined flow paths that can reduce or mitigate thermal crosstalk by providing a degree of thermal insulation, which reduces the transport of heat from one area of the die 218 to another via the cooling liquid and reduces risk of dead zones in the flow of coolant. As shown in
A protective layer 404 can be formed or deposited on the first side 406 of the second substrate 426 and as shown in
In
The first cavity 246, which can include the first channels 212 as described with respect to
Although the cooling structure 400 has been described to be formed through a method utilizing two substrates 402, 426, in some embodiments, three substrates could be used. For example, the method of forming the cooling structure could comprise three layers such that a first plurality of channels is formed in a first substrate (first layer), a plurality of nozzles is formed in a second substrate (second layer), and a second plurality of channels is formed in a third substrate (third layer). The first layer can be direct bonded to the second layer, and the second layer can be direct bonded to the third layer. In this latter method of formation, the concern of etching an unintended side is removed or mitigated by further separating the layers into which the channels and nozzles are etched into, but an additional substrate, additional alignment process and additional bonding process are entailed.
The fabrication process for forming a cooling structure 400 can further comprise the steps of bonding the cooling structure 400 to the integrated device die 218, either at the wafer or die stage. For example, the second side 408 of the second substrate 426 of the cooling structure 400 can be bonded to a semiconductor element that is or includes the integrated device die 218. The second channels 214 of the second substrate 426 are exposed to the semiconductor element 218. In some embodiments, bonding the cooling structure 400 to the integrated device die 218 can comprise directly bonding the second side 408 of the second substrate 426 to the integrated device die 218 or the wafer from which it will be singulated. In some embodiments, the second substrate 426 and the first substrate 402 can have a coefficient of thermal expansion that is matched to a coefficient of thermal expansion of the integrated device die 218.
Producing an air gap 606 can increase the efficiency of the spray jet and improve thermal removal. In the embodiment of
The second portion 704 can have a second cross-sectional area at the second orifice 818 and a second height (e.g., a cone length or a second length L2). The second cross-sectional area can be circular (for a conical second portion 704), or polygonal (e.g., triangular or rectangular, for a pyramidical second portion 702) from a top-down view, and it can have a second width or a diameter D2. In some embodiments, the second portion 704 can be formed to have sides or sidewalls at a cone angle α, where α can be an angle at or between values of about 45° and about 80°. For example, the second sidewalls 708 can be oblique relative to a second orifice 818 (see
The resulting shape of the nozzle 700 is funnel-like, which can help with increasing the velocity of a fluid 710 exiting the first portion 702 of the nozzle 700 by narrowing the nozzle 700 in the manner described. The funnel-like shape of the nozzle 700 allows the fluid 710 to undergo an increase in pressure as it flows from the larger input width or diameter D2 of the upstream end of the second portion 704 to the smaller output width or diameter D1 of the first portion 702. The first portion 702 allows for the fluid 710 to accelerate and exit the nozzle 700 at a high speed. In some cases, the straight throat length L1 may be relatively small in value (e.g., approximately in a range of 50 μm and 125 μm). If the straight throat length L1 is too large, then this may result in too high of a back pressure, which can risk structural damage to the nozzle 700 and thus the cooling structure 230.
In some embodiments, and as shown in
In some embodiments, the first length L1 may be greater than the diameter D1. For example, L1 can be at least 2 times the value of D1 or at least 5 times the value of D1. In some cases, L1 can have a value in a range of approximately 2 and 5 times the value of D1. In one example, the nozzle 700 can be fabricated to have a cone angle α approximately equal to 55°, which can be readily provided, for example, by wet etching silicon along a (111) plane. In one example, the diameter D2 (e.g., input diameter of the nozzle 700) can be about 155-175 μm, the cone length L2 can be about 90-110 μm, and the diameter D1 (e.g., output diameter of the nozzle 700) can be about 20-30 μm. With these values, the straight throat length L1 can be in a range of approximately between 50 and 125 μm. The configuration where L1 is greater than D1 by at least a factor of 2 can minimize the jet angle B of the fluid 710, which can allow for the fluid 710 exiting the first portion 702 to have an increased fluid velocity as it contacts a chip to be cooled. Beneficially, the relationship between L1 and D1 can facilitate a suitable collimated (e.g., β value between approximately 0° and 20°, such as approximately 0° and 10°, or approximately 0° and) 5° exit flow of the fluid 710 with minimal losses due to friction.
A second substrate 802 is shown in
A protective layer 404 can be formed or deposited on the first side 804 of the second substrate 802 and as shown in
In
The first cavity 246, which can include the first channels 212 as described with respect to
As the dimensions of the first portion 702 of the nozzle 700 become smaller, the hydrophilic properties of the nozzle 700 become increasingly important to reduce the turbulence within the nozzle 700. Otherwise, as the turbulence within the nozzle 700 increases, the flow of the fluid 710 through the nozzle 700 can become obstructed because of the turbulence, and thus substantially reduce the fluid velocity as it exits the nozzle 700.
In fabricating a nozzle 700 to have a tapered or funnel portion and a relatively straighter throat/edge portion with the varying relative dimensions described herein, the fluid exit velocity can be maximized as it exits the nozzle 700. Maximizing the fluid exit velocity as it contacts the chip to be cooled can increase the turbulence of the fluid in the second cavity 248 (e.g., second channels 414) after exiting the nozzle 700. This in turn can enable better penetration of any stagnant fluid at a chip's surface and increase the heat transfer efficiency, thereby leading to more effective heat removal.
In some aspects, the techniques described herein relate to a method of forming a cooling structure, the method including forming an inlet and a first cavity in a first substrate, forming a second cavity in a second substrate, forming a plurality of nozzles in at least one of the first and second substrates, forming an outlet extending from the second cavity, and bonding the first substrate to the second substrate such that the nozzles fluidly connect the first cavity to the second cavity.
In some embodiments, the nozzles are formed in the second substrate.
In some embodiments, the outlet extends through a thickness of the first substrate, and the inlet extends through the first substrate to a depth less than the thickness of the first substrate.
In some embodiments, the second cavity of the second substrate is directly connected to the outlet.
In some embodiments, the method further includes forming an inorganic dielectric bonding layer on a side of the second substrate opposite the first substrate.
In some embodiments, bonding the first substrate to the second substrate includes forming a direct bond between the first substrate and the second substrate without an intervening adhesive. In some embodiments, forming the direct bond includes forming an oxide bonding layer on the first substrate or on the second substrate.
In some embodiments, the techniques described herein relate to a method of forming a liquid-cooled package. The method of forming the liquid-cooled package can include the method of forming the cooling structure and bonding the second substrate to a semiconductor element. In some embodiments, the second cavity of the second substrate is exposed to the semiconductor element. In some embodiments, bonding the second substrate to the semiconductor element includes forming a direct bond between the second substrate and the semiconductor element without an intervening adhesive. In some embodiments, the semiconductor element includes one of a wafer or a semiconductor die. In some embodiments, the first substrate and the second substrate have coefficients of thermal expansion that match a coefficient of thermal expansion of the semiconductor element.
In some embodiments, forming the plurality of nozzles includes forming tapered openings. In some embodiments, forming tapered openings can include wet etching a single crystal material of the second substrate. In some embodiments, the tapered openings are rectangular in shape.
In some embodiments, a nozzle of the plurality of nozzles is formed in the second substrate, the nozzle including a first portion having first sidewalls and a first orifice adjacent to the first substrate, and a second portion having second sidewalls and a second orifice opening from the nozzle to the second cavity. A first angle between the first sidewalls and the first orifice can be between approximately 85° and 95°, and a second angle between the second sidewalls and the second orifice can be between approximately 45° and 80°. In some embodiments, the method further includes forming the first portion with a dry etch process and forming the second portion with a wet etch process.
In some embodiments, the method further includes forming a hydrophilic layer to line the nozzles.
In some embodiments, the first cavity includes a plurality of first channels, and the second cavity includes a plurality of second channels.
In some aspects, the techniques described herein relate to a bonded structure including a cooling structure including a bonding surface, a plurality of channels extending into the cooling structure from the bonding surface, a plurality of nozzles, and an integrated device die bonded to the cooling structure through the bonding surface of the cooling structure. Each nozzle of the plurality of nozzles can be disposed over and in fluid communication with a channel of the plurality of channels.
In some embodiments, each nozzle of the plurality of nozzles joins with a corresponding channel at an orifice that is narrower than the corresponding channel.
In some embodiments, the cooling structure includes a first element, and a second element directly bonded to the first element without an intervening adhesive. In some embodiments, the first element includes an inlet, an outlet, and a plurality of first channels in fluid communication with the plurality of nozzles. The second element includes a plurality of second channels and the plurality of nozzles, and the plurality of second channels corresponds to the plurality of channels extending into the cooling structure from the bonding surface. In some embodiments, at least some nozzles of the plurality of nozzles are tapered to have wider openings on a first side and narrower openings on a second side, and the narrower openings are in fluid communication with the plurality of second channels.
In some embodiments, at least one nozzle of the plurality of nozzles includes a first portion having an approximately constant cross-sectional area downstream portion and a second portion directly disposed over the first portion, where the second portion has a tapering cross-sectional area upstream portion.
In some embodiments, the bonded structure further includes a hydrophilic layer disposed over surfaces of the plurality of nozzles. In some embodiments, the bonded structure further includes a conformal layer of silicon dioxide lining the plurality of nozzles.
In some embodiments, the bonded structure further includes a direct bond between a back side of the integrated device die and the bonding surface of the cooling structure without an intervening adhesive.
In some aspects, the techniques described herein relate to a cooling structure including a first semiconductor layer including an inlet and a first cavity, a second semiconductor layer including a plurality of nozzles and a second cavity, and an outlet. The nozzles fluidly connect the first cavity and the second cavity, and the inlet is fluidly coupled to the first cavity and the outlet is fluidly coupled to the second cavity. The first semiconductor layer is directly bonded to the second semiconductor layer.
In some embodiments, the first cavity includes a plurality of first channels and at least one support structure, and the second cavity includes a plurality of second channels and at least one support structure. In some embodiments, the first channels extend parallel to the second channels. In some embodiments, the first channels extend perpendicular to the second channels. In some embodiments, the cooling structure is directly bonded to a semiconductor element. In some embodiments, the at least one support structure of the second semiconductor layer is directly bonded to the semiconductor element. In some embodiments, an exposed outer surface of the first semiconductor layer and the second semiconductor layer is enveloped by an encapsulant. In some embodiments, a heat spreader is disposed on a top surface of the encapsulant, and the top surface of the encapsulant is disposed on a side of the first semiconductor layer opposite the semiconductor element. In some embodiments, the heat spreader includes a metal. In some embodiments, coefficients of thermal expansion of the first semiconductor layer and the second semiconductor layer match a coefficient of thermal expansion of the semiconductor element. In some embodiments, the semiconductor element includes one of a semiconductor wafer or a semiconductor dic.
In some embodiments, the nozzles are exposed to the first cavity on a first side of the nozzles and to the second cavity on a second side of the nozzles, and the first side of each of the nozzles has an opening size that is greater than an opening size of the second side of each of the nozzles. In some embodiments, the nozzles include one or more sidewalls formed with wet etching. In some embodiments, the cooling structure further includes a hydrophilic layer disposed over the one or more sidewalls. In some embodiments, the cooling structure further includes a conformal layer of silicon oxide disposed over the one or more sidewalls. In some embodiments, the one or more sidewalls include first sidewalls and second sidewalls disposed directly over the first sidewalls, and the first sidewalls include approximately vertical sidewalls and the second sidewalls include sloped sidewalls.
In some embodiments, the nozzles include circular openings. In some embodiments, the nozzles include rectangular openings.
In some aspects, the techniques described herein relate to a method of forming a cooling structure, the method including forming an inlet and an outlet in a first substrate, forming a first channel in the first substrate, forming a plurality of nozzles, including a first nozzle, in a second substrate, forming a second channel in the second substrate, and bonding the first substrate to the second substrate such that at least the first nozzle is in fluid communication with the first channel and the second channel. The first channel can be in fluid communication with the inlet, and the second channel can be in fluid communication with the outlet. Forming the first nozzle can include forming a first portion and a second portion over the first portion, where the first portion includes first sidewalls and a first orifice, and the second portion includes second sidewalls and a second orifice. The first sidewalls can be approximately perpendicular to the first orifice of the first portion, and the second sidewalls can be oblique relative to the second orifice of the second portion.
In some embodiments, the method further includes depositing a conformal hydrophilic layer to line the plurality of nozzles.
In some embodiments, the first portion is formed before the second portion. In some embodiments, the second portion is formed before the first portion.
In some embodiments, a first angle between the first sidewalls and the first orifice is in a range between approximately 85° and 95°, and a second angle between the second sidewalls and the second orifice is in a range between approximately 45° and 80°.
In some embodiments, forming the first nozzle includes dry etching the first portion and wet etching the second portion.
In some embodiments, the first portion includes a first height perpendicular to the first orifice, the second portion includes a second height perpendicular to the second orifice, and the second height is less than the first height. In some embodiments, the first orifice includes a diameter, and the first height is approximately between 2 and 5 times a value of the diameter.
In some embodiments, the method further includes forming an inorganic dielectric bonding layer on the second substrate at a bonding interface.
In some embodiments, bonding the first substrate to the second substrate includes directly bonding the first substrate to the second substrate without an intervening adhesive. In some embodiments, directly bonding includes forming an oxide bonding layer on the first substrate at a bonding interface or on the second substrate at the bonding interface.
In some embodiments, the techniques described herein relate to a method of forming a liquid-cooled package including the method of forming the cooling structure and bonding the second substrate of the cooling structure to a semiconductor element. In some embodiments, the second channel is exposed to the semiconductor element. In some embodiments, bonding the second substrate to the semiconductor element includes directly bonding the second substrate to the semiconductor element without an intervening adhesive. In some embodiments, the semiconductor element includes one of a wafer or a semiconductor die. In some embodiments, the first substrate and the second substrate include bulk materials, the semiconductor element includes a semiconductor bulk material, and the bulk materials are the same as the semiconductor bulk material.
In some aspects, the techniques described herein relate to a cooling structure including a semiconductor structure having a bonding surface for bonding to an integrated device die and a back surface opposite the bonding surface. The semiconductor structure includes a plurality of cavities extending into the semiconductor structure from the bonding surface. The cooling structure further includes a plurality of nozzles, where each nozzle of the plurality of nozzles is disposed over and in fluid communication with a corresponding cavity of the plurality of cavities. Each nozzle includes a first portion and a second portion over the first portion, the first portion having first sidewalls and a first orifice, and the second portion having second sidewalls and a second orifice. The first sidewalls are approximately perpendicular to the first orifice, and the second sidewalls are oblique relative to the second orifice of the second portion.
In some embodiments, a first angle between the first sidewalls and the first orifice is in a range between approximately 85° and 95°, and a second angle between the second sidewalls and the second orifice is in a range between approximately 45° and 80°.
In some embodiments, each nozzle of the plurality of nozzles joins with the corresponding cavity at the first orifice and the second orifice, and the first orifice and the second orifice are narrower than the corresponding cavity.
In some embodiments, the semiconductor structure includes a first element and a second element directly bonded to the first element without an intervening adhesive. In some embodiments, the first element includes an inlet, an outlet, and a first plurality of channels in fluid communication with the plurality of nozzles, and the second element includes a second plurality of channels and the plurality of nozzles. In some embodiments, the plurality of nozzles is tapered to have wider openings on a first side and narrower openings on a second side, and the narrower openings are in fluid communication with the plurality of cavities. In some embodiments, the techniques described herein relate to a bonded structure including the cooling structure and the integrated device die, where the cooling structure is directly bonded to a back side of the integrated device die without an intervening adhesive.
In some embodiments, the cooling structure further includes a conformal hydrophilic layer over the plurality of nozzles. In some embodiments, the conformal hydrophilic layer includes silicon dioxide.
In some embodiments, the first portion is dry etched and the second portion is wet etched.
In some embodiments, the first portion includes a first height perpendicular to the first orifice, the second portion includes a second height perpendicular to the second orifice, and the second height is less than the first height. In some embodiments, the first orifice includes a diameter, and the first height is approximately between 2 and 5 times a value of the diameter.
Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” “include,” “including” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled,” as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Likewise, the word “connected,” as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Moreover, as used herein, when a first element is described as being “on” or “over” a second element, the first element may be directly on or over the second element, such that the first and second elements directly contact, or the first element may be indirectly on or over the second element such that one or more elements intervene between the first and second elements. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.
Moreover, conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments.
While certain embodiments have been described, these embodiments have been presented by way of example only and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while blocks are presented in a given arrangement, alternative embodiments may perform similar functionalities with different components and/or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.
This patent application is a continuation-in-part of U.S. patent application Ser. No. 18/398,984, filed Dec. 28, 2023, titled “ELECTRONIC DEVICE COOLING STRUCTURES,” which claims the benefit of priority of U.S. Provisional Patent Application No. 63/483,944, filed Feb. 8, 2023, titled “SEMICONDUCTOR DEVICE COOLING STRUCTURES,” the disclosures of each of which are incorporated herein by reference in their entirety for all purposes. This patent application also claims the benefit of priority of U.S. Provisional Application No. 63/680,280, filed Aug. 7, 2024, titled “ELECTRONIC DEVICE COOLING STRUCTURES,” the disclosure of which is incorporated herein by reference in its entirety for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 63483944 | Feb 2023 | US | |
| 63680280 | Aug 2024 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 18398984 | Dec 2023 | US |
| Child | 18924480 | US |
