Patent Application
20250096096
Embodiments described herein relate to electronic packaging, and more specifically to multiple level electronic packages.
Today, the electronics industry uses a lot of passive and active components as part of integrated circuits for different sub-system in many products such as touch sensing, haptics module or camera module. Due to the increasing need for miniaturizing systems they are typically packaged as system in packages (SiPs), where the components are assembled/soldered on a substrate and then encapsulated using a molding compound. This helps in placing the various components required for a system together in one place and reducing the overall size of the package.
Electronic packages and methods of formation are described which include molded vertical interconnections. In an embodiment, an electronic package includes one or more electronic components encapsulated in a step molded molding compound layer including a lower step surface, a sidewall, and top surface. A via opening can be formed in the lower step surface to expose an underlying routing layer. In this manner, the molded lower step surface can reduce overall via opening height, facilitating the use of fabrication techniques such as laser drilling for via opening formation. In another embodiment, a vertical interconnect can be encapsulated within the molding compound layer, and a via opening can be formed through the molding compound layer to expose the vertical interconnect. In this manner, the vertical interconnect can reduce overall via opening height, facilitating the use of fabrication techniques such as laser drilling for via opening formation.
Embodiments describe miniaturized system in packages (SiPs), or SiPlets, that allow vertical interconnects using laser via and specialized step molding. In an embodiment an electronic package (e.g. SiP or SiPlet) includes a first-level routing layer (e.g. package substrate), a first-level electronic component (e.g. passive device, active device, etc.) on the first-level routing layer, and a first-level molding compound layer that encapsulates the first-level electronic component on the first-level routing layer. The first-level molding compound layer in accordance with some embodiments may be step molded, and include a top surface, a lower step surface and a sidewall spanning between the top surface and the lower step surface. A second-level wiring layer can be formed on the first-level molding compound layer and spanning the lower step surface, the sidewall, and the top surface of the first-level molding compound layer. A second-level electronic component may then be mounted on the second-level wiring layer. In some embodiments, a first-level via opening extends through the lower step surface of the first-level molding compound layer to the first-level routing layer. The second-level wiring layer may additionally extend into the first-level via opening and be in electrical contact with the first-level routing layer. In this manner, the step molded first-level molding compound layer can be formed using traditional laser drilling methods, with a first-level via opening height:width ratio of 1:1 or less, with a normalized height value being 1 or less and normalized width value of 1.
In one aspect, embodiments describe herein may improve the miniaturization of SiPs by stacking passives or silicon in multiple package levels within a same SiP by multi-layer molding and wiring layer formation. Such techniques may reduce form factor and increase functionality of the SiPs from one generation to another. In some embodiments this may be facilitated by a step mold structure, in which a bottom step of the mold is used to drill a blind via that is 1:1 aspect ratio or less (i.e., wider). Then a first-level routing layer circuit connections are formed along the sidewalls of the step mold to the top of the molding compound layer using suitable techniques such as sputtering, plating and/or laser direct structuring of the molding compound layer. Electronic components, such as a passives or integrated circuit (IC) silicon, can be added to the top of the molding compound layer creating a second package level. Another step mold can then optionally be assembled on the second package level allowing further addition of another vertical layer. These operations can be repeated to form additional package levels.
In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions and processes, etc., in order to provide a thorough understanding of the embodiments. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the embodiments. Reference throughout this specification to “one embodiment” means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.
The terms “over”, “to”, “between”, “spanning” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “over”, “spanning” or “on” another layer or bonded “to” or in “contact” with another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.
Referring now to
The first-level routing layer 102 in accordance with the various embodiments described herein may assume various configurations such as redistribution layers or printed circuit boards (PCBs), each including one or more metal routing layers 110 and insulation (e.g. dielectric) layers 114. Furthermore, the first-level routing layers 102 may be rigid or flexible. The first-level routing layer 102 may be formed of a variety of materials, including traditional substrates such as FR-2 (a phenolic paper impregnated with resin), FR-4 (a woven fiberglass impregnate with resin), RCC (resin coated copper), ABF (Ajinomoto Build-up Film) metal or metal core substrates, silicon core substrates, ceramics, polymers, etc. Metal routing layers 110 and vias 112 may be formed of suitable materials, such as copper, gold, aluminum, etc. First-level routing layers may be coreless substrates, or include cores. First-level routing layers 102 can also be formed using thin film techniques. For example, the insulation layer(s) 114 may be formed of a photoimageable dielectric material including polymers (e.g. polyimide, epoxy, epoxy blends, etc.) or inorganic materials (e.g. oxide, nitride), while the metal routing layers 110 and vias 112 may be formed of a suitable metal, including copper.
In accordance with embodiments, one or more electronic components 120, 122 can be mounted onto the top side 104 of the first-level routing layer 102, for example using solder bumps 124. For example, electronic components 120 can be an active silicon device, while electronic components 122 are passive devices, such as resistors, capacitors, inductors, etc. However, this is exemplary, and a variety of electronic components can be integrated. It is to be appreciated that while the electronic components 120, 122 are mounted onto a pre-formed first-level routing layer 102, that this is not required and a first-level routing layer 102 can be subsequently formed, for example, as a redistribution layer (RDL) using an embedded wafer level packaging process.
Still referring to the embodiment illustrated in
Following the formation of the first-level molding compound layer 130 one or more via openings 135 may be formed through the lower step surface(s) 134 of the first-level molding compound layer 130 to the first-level routing layer 102, such as to landing pad(s) 116. In accordance with embodiments, the first-level via opening 135 has a height:width ratio of 1:1 or less, with the height value being 1 or less. Thus, conventional laser drilling equipment may be utilized. In an exemplary embodiment, a thickness of the first-level molding compound layer 130 between the lower step surface 134 and the first-level routing layer 102 is less than 100 μm, such as 80 μm. In order to maintain the 1:1 or less aspect ratio, a maximum width of the first-level via opening 135 between laterally opposite sidewalls 138 is thus, the same or greater distance. In the exemplary embodiment of an 80 μm deep via opening 135, a maximum width of the via opening 135 (for example at the top surface 134 where the via opening has straight or inwardly tapered sidewalls 138) is 80 μm or more.
In accordance with embodiments, a second-level wiring layer 210 is formed on the first-level molding compound layer 130 and spanning the lower step surface 134, the sidewall 136, and the top surface 132 of the first-level molding compound layer. The second-level wiring layer 210 can extend into the first-level via opening and be in electrical contact with the first-level routing layer. The second-level wiring layer 210 can fully or partially fill the first-level via opening 135.
The second-level wiring layer 210 may be formed using a variety of techniques, and combinations thereof, including sputtering, evaporation, plating, and laser direct structuring (LDS). Furthermore, the second-level wiring layer 210 may including a single layer or multiple layers. For example, the second-level wiring layer 210 may include a nucleation layer and bulk layer. Where LDS is used, the first-level molding compound layer 130 is a laser direct structuring (LDS) compatible material including a first dispersed non-conductive metal organic compound, while the second-level wiring layer 210 comprises metal particles of a first metal in the first dispersed non-conductive metal organic compound, which may form the entirety of the second-level wiring layer 210 or a nucleation layer onto which a bulk layer is grown, for example with plating. The second level wiring layer 210 may also be formed by applying a masking layer on top of the mold and sputter coating a layer of metal on the wiring area. Another method of applying the wiring layer would be coat the sputter layer and then laser etch the areas to form the various circuits.
The wiring layers in accordance with embodiments, inclusive of the second-level wiring layer 210 may include one or more layers and materials to form wiring traces, via connections, and landing pads. For example, the wiring layers can include copper layers, stainless steel layers, as well as plated nickel/gold or nickel/palladium/gold layers for landing pad formation.
Still referring to
Referring now to
The LDS additive, and laser parameters are selected so that upon application of the laser to the molding compound, a conducting path is formed corresponding to the laser pattern. As shown in
Referring now to
The one or more first-level electronic components 120, 122 can then be encapsulated in a first-level molding compound layer 130 at operation 3020. For example, this may be a step molding operation in which a top mold cavity has a profiled surface, resulting in a first-level molding compound layer 130 including a top surface 132, lower step surface 134 and a sidewall 136 spanning between the top surface 132 and the lower step surface 134 as shown in
In accordance with embodiments, the via openings 135 are formed using a suitable technique such as etching or laser drilling. Exemplary laser sources include CO2 lasers, Nd:YAG lasers, combinations thereof, etc. Traditional laser drilling may be accomplished with via opening diameters as low as 25 μm (˜0.001 mils) with Nd:YAG lasers and 50-70 μm (˜0.002-0.003 mils) with CO2 lasers, for example. It has been observed that laser via opening quality can be affected when aspect ratios exceed a 1:1 aspect ratio of height:width (i.e. width/diameter being less than height). In accordance with embodiments, via openings 135 are characterized by a height:width aspect ratio of 1:1 or less, with the normalized height value being 1 or less with a normalized width value of 1. For example, a via opening with maximum width or diameter of 50-100 μm may have a corresponding maximum height of 50-100 μm or less to maintain the aspect ratio. Specifically, a via opening with maximum width of 80 μm may have a corresponding maximum height of 80 μm or less. The height thus, corresponds to the thickness of the first-level molding compound layer between the lower step surface 134 and the first-level routing layer 102. The step mold in accordance with embodiments may facilitate the integration of laser drilling while maintaining a specified aspect ratio.
Referring now to
As shown in
A second-level via opening 235 including sidewalls 238 may then be formed in the second-level molding compound layer 230 and extend through the second lower step surface 234 to the second-level wiring layer 210 as shown in
Up until this point electronic package 100 configurations including step molded layers have been described to facilitate the inclusion of laser drilled via openings to accomplish stacking of electronic components in multiple package levels. Alternatively, laser drilled via openings can be made to expose underlying vertical interconnects, such as metal (e.g. copper) pins, metal blocks, interposers, PCB bar, etc. As such, the underlying vertical interconnect can provide the additional height to facilitate inclusion of the laser drilled via openings with specified aspect ratios.
As illustrated a first-level molding compound layer 130 encapsulates the one or more first-level electronic components and the one or more first-level vertical interconnects 160 on the first-level routing layer 102. Similar to previous embodiments, the first-level molding compound layer 130 can include a top surface 302 which can be a level top surface, though the first-level molding compound layer may not be step molded. Following the formation of the first-level molding compound layer 130, one or more first-level via openings are formed partially through the first-level molding compound layer 130 to the one or more first-level vertical interconnects 160, such as to the top contact pads 168.
A second-level wiring layer 210 may be formed on the top surface 132 of the first-level molding compound layer 130 and within the first-level via opening 135 as previously described. Specifically, the second-level wiring layer 210 may be in electrical contact with the first-level routing layer 102 through the first-level vertical interconnect 160. This sequence can be repeated for additional package levels, including mounting of one or more second-level electronic components 220, 222 and second level vertical interconnects 260 on the second-level wiring layer 210, followed by formation of the second-level molding compound layer 230, second-level via opening 235 formation, and formation of a third-level wiring layer 310 as previously described. The via openings may have similar height:width ratios as previously described. In the illustrated embodiment, one or more third-level electronic components 322 are mounted on the third-level wiring layer 310, followed by encapsulation with a third-level molding compound layer 330 with level top surface 302.
The illustrated embodiment of
It is to be appreciated that while the illustrated embodiments have assumed mounting of the first-level electronic components onto an existing first-level routing layer 102, that such as fabrication sequence is not strictly required, and instead the first-level electronic components can be mounted onto a carrier substrate that is subsequently removed after formation of the top molding compound layer, followed by the formation of the first-level routing layer 102.
In utilizing the various aspects of the embodiments, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for miniaturization of electronic packages (e.g. SiPs) by stacking passives or silicon in multiple package levels within a same electronic package. Although the embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that the appended claims are not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as embodiments of the claims useful for illustration.
