Patent Application
20140042627
The present disclosure relates to a secure electronic structure, an integrated circuit which includes the secure electronic structure and methods of forming the same. More particularly, the present disclosure relates to an electronic structure containing a via array as a physical unclonable function.
In the electronics industry, security in an electronic device has become a major concern of manufacturers and users of such devices. In this regard, it is useful to be able to distinguish each electronic device, especially the integrated circuit within these devices, from each other. This is particularly true for devices such as computers, personal hand held devices, cellular phones, chip cards, and other devices that contain sensitive information. Developers of electronic devices continuously strive to provide systems and methods that make their products impervious to unauthorized access or use.
At the same time, most applications have cost limitations that must be taken into account. For example, if a complicated authentication process requiring storage and computing resources were employed on an integrated circuit, the costs incurred may not justify the cost of security accomplished, particularly if the end product were a low cost and mass produced consumer product.
According to the prior art, a key in a binary code may be stored on a secure integrated circuit in a non-volatile memory array on the circuit. At initialization of the circuit (boot up), the authorized user inputs a code, and initialization (boot up) continues only if the correct code is entered. The secure circuit does not function without the correct code entered at the correct step. However, the circuit may be physically delayered by an unauthorized user (e.g., an enemy) and the binary code obtained by reading the individual device states in the non-volatile memory array. The circuit is then not secure and can be used by the unauthorized user, and the system security has been broken.
One approach to solve the above identified problems is to employ a physical unclonable function (PUF) to provide a unique, secure bit, word or function for use in generating security keys. A PUF may eliminate the need for storage of a public or private key on a device. PUFs are known in the art to be implemented by circuits, components, processes or other entities capable of generating an output, such as a digital bit, word or a function that is resistant to cloning.
Typically, the PUF can be generated based on inherent physical characteristics of a device such as for example individual physical characteristics of a transistor such as a threshold voltage of the transistor which varies due to local process variations during manufacturing. There is no need to store the PUF within the device, because the PUF can be generated repeatedly. Moreover, it is nearly impossible to clone a device having a PUF implemented in a manner to generate the same PUF output with another device.
Although PUFs have been implemented within electronic devices, there exists a need to create an electronic structure having a physical unclonable function embodied in the physical structure, which is easy to evaluate but hard to predict, and which is formed using standard integrated circuit manufacturing methods and materials. It is desirable to fabricate the PUF during standard integrated circuit manufacturing and to add a minimum number of additional process steps in order to complete the PUF structure, so the PUF is inexpensive to manufacture.
It is desirable to have a system or method of storing a code on the secure integrated circuit that is randomly generated.
Embodiments of the present disclosure describe secure integrated circuits, physical unclonable function structures, and methods to make such structures and circuits.
In one embodiment, the present disclosure provides a secure electronic structure including a via array as a physical unclonable function (PUF) and an integrated circuit including the same. Specifically, the secure electronic structure of the present disclosure includes an array of electrical contact vias located between a lower level of a first regularly spaced array of conductors and an upper level of a second regularly spaced array of conductors. Each electrical contact via of the array of electrical contact vias is individually addressed through the first regularly spaced array of conductors in the lower level and the second regularly spaced array of conductors in the upper level and has a resistance value. In one embodiment, each resistance value of each electrical contact via can be combined into a distribution of resistance values, wherein the distribution of resistance values is random. This random distribution of the resistance values of the array of electrical contact vias can be used as a physical unclonable function in the electronic structure of the present disclosure.
In a second embodiment, the location of each electrical contact via is described as a matrix, and the matrix location of the high and low resistance values of each electrical contact via is randomly generated and can be used as the physical unclonable function in the electronic structure of the present disclosure.
In one aspect of the present disclosure, an electronic structure including a physical unclonable function is provided. The electronic structure of the present disclosure includes a first level including a first regularly spaced array of conductors. The structure further includes a second level including a plurality of electrical contact vias atop the first level. The structure also includes a third level including a second regularly spaced array of conductors atop the second level. In accordance with the present disclosure, each electrical contact via of the plurality of electrical contact vias in the second level is individually addressed through the first regularly spaced array of conductors in the first level and the second regularly spaced array of conductors in the third level and has a resistance value. Each resistance value of each electrical contact via in the second level forms a distribution of resistance values, wherein the distribution of resistance values is random.
In another aspect of the present disclosure, an integrated circuit is provided that includes an electronic structure having a physical unclonable function. The integrated circuit of the present disclosure includes at least one semiconductor device located upon a portion of a semiconductor substrate. In some embodiments, measurement circuits are included on the substrate to measure the resistance of each via in the via array. A first level including a first regularly spaced array of conductors is located atop the semiconductor substrate including the at least one semiconductor device. The integrated circuit further includes a second level including a plurality of electrical contact vias atop the first level. The integrated circuit also includes a third level including a second regularly spaced array of conductors atop the second level. In accordance with the present disclosure, each electrical contact via of the plurality of electrical contact vias in the second level is individually addressed through the first regularly spaced array of conductors in the first level and the second regularly spaced array of conductors in the third level and has a resistance value. Each resistance value of each electrical contact via in the second level forms a distribution of resistance values, wherein the distribution of resistance values is random.
In another aspect of the present disclosure, methods of forming an electronic structure including a physical unclonable function are provided. Each method of the present disclosure includes forming a first level comprising a first regularly spaced array of conductors embedded within a first dielectric material. Next, a second level comprising a plurality of electrical contact vias embedded within a second dielectric material is formed atop the first level. In accordance with the present disclosure, each electrical contact via of the plurality of electrical contact vias has a resistance value, wherein each resistance value of each electrical contact via forms a distribution of resistance values, and wherein the distribution of resistance values is random. Also, the matrix location of high and low resistance values of each electrical contact via in the array is random. Next, a third level comprising a second regularly spaced array of conductors is formed atop the second level, wherein each electrical contact via of the plurality of electrical contact vias in the second level is individually addressed through the first regularly spaced array of conductors in the first level and the second regularly spaced array of conductors in the third level.
The present disclosure, which provides a secure electronic structure with a physical unclonable function (PUF), an integrated circuit including the secure electronic structure and methods of fabricating the same, will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes and, as such, they are not drawn to scale. In the drawings and the description that follows, like elements are referred to by like reference numerals. For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the components, layers and/or elements as oriented in the drawing figures which accompany the present application.
In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the present invention. However, it will be appreciated by one of ordinary skill in the art that the present disclosure may be practiced with viable alternative process options without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the various embodiments of the present disclosure.
As stated above and in some embodiments of the present disclosure, a secure electronic device and an integrated circuit that includes the same are provided. More particularly, the present disclosure provides an electronic structure in which a code for authentication is stored directly on the integrated circuit itself, using a unique physical identifier (or code) fabricated within the electronic structure. The secure electronic structure of the present disclosure retains the unique code, and is generated randomly.
In the present disclosure, the electronic structure remains stable when the electronic structure is powered down, because it is hidden in the form of unique identifiers (i.e., PUFs) within the electronic structure itself. A unique physical identifier or fingerprint thus can exist on every chip due to inherently random variations. These random variations can be utilized as a unique physical identifier of each integrated circuit and must be matched with an input code when the circuit is initialized.
The electronic structure of the present disclosure which includes the PUF can be made utilizing standard semiconductor manufacturing methods and materials, while utilizing a minimum of added processing steps. Also, the electronic structure of the present disclosure has the following characteristics: (i) reliability to avoid bit errors: The electronic structure of the present disclosure is stable and the PUF value does not drift significantly over time and temperature and circuit use. (ii) Random variability: Variability of the electronic structure of the present disclosure is significant enough to enroll millions of electronic structures to give each a unique code and the PUF values are random to avoid would be attackers, i.e., unauthorized users, from guessing specific patterns. Variability is also important to the PUF stability to avoid bit errors.
As stated above, the electronic structure includes an array of electrical contact vias located between a lower level of a first regularly spaced array of conductors and an upper level of a second regularly spaced array of conductors. Each electrical contact via has a resistance value which can be addressed and measured. Each resistance value of each electrical contact via forms a distribution of resistance values, wherein the distribution of resistance values is random. This random distribution of the resistance values of the array of electrical contact vias can be used as a physical unclonable function.
Referring now to
In accordance with the present disclosure, each electrical contact via of the plurality of electrical contact vias 24 in the second level 20 can be individually addressed through the first regularly spaced array of conductors 18 in the first level 14 and the second regularly spaced array of conductors 28 in the third level 26. Also, each electrical contact via of the plurality of electrical contact vias 24 has a resistance value. In one embodiment, each resistance value of each electrical contact via contributes to a distribution of resistance values, wherein the distribution of resistance values is random. In a second embodiment, each resistance value of each electrical contact via has a specific location described as a matrix and the code consists of a 0 or 1 value at each location, or matrix cell.
Structure 10 is an example of a crossbar array, which is a widely used general structure, for example, in resistive memory arrays. There exists a body of prior art describing circuits to individually address and read each location in a crossbar array where an upper conductor (in level 26) intersects a lower conductor (in level 14), and circuits performing this function are well known. One example is described in U.S. Pat. No. 7,564,262 B2, which also lists several prior art patents. In one embodiment, a demultiplexer such as disclosed, for example, in U.S. Pat. No. 6,256,767, and the publication entitled “Nanoelectronics from the bottom up” Nature Materials, vol. 6, Nov. 2007, can be used to address and read the electronic structure of the present disclosure. In some embodiments, the demultiplexer can be wired to any of the first regularly spaced array of conductors 18 and/or the second regularly spaced array of conductors 28.
As shown in the various drawings of the present disclosure, each conductor of the second regularly spaced array of conductors 28 has a bottommost surface that is in direct contact with an uppermost surface of an electrical contact via of the plurality of electrical contact vias 24. Also, each conductor of the first regularly spaced array of conductors 18 has an uppermost surface that is in direct contact with a bottommost surface of an electrical contact via of the plurality of electrical contact vias 24.
The randomness of the resistance value of each electrical contact via of the plurality of contact vias 24 can be used herein as a PUF and thus can be used as a security code for the electronic structure of the present disclosure. Each individual via has a resistance value, and the table of resistance and location can thus be referred to as a PUF value, which remains in the electronic device during power on and power off states. When an electronic device containing the electronic structure of the present disclosure is powered on, the user can input the correct code into the system, the circuit compares the input code with that stored on the circuit. For correct matches of the code, the electronic device boots up to its normal function. When no code or an incorrect is inputted during powering on the electronic device containing the electronic structure of the present disclosure, the electronic device is disabled (boot up stops) preventing the user from obtaining access to the system.
Referring now to
As shown in
The electronic structure 10 that shown in
The various methods that can be employed in the present disclosure are now disclosed together with specific details regarding the materials that can be employed in the present disclosure in forming the electronic structure shown in
Referring first to
The substrate 12 may comprise a semiconducting material, an insulating material, a conductive material or any combination including multilayers thereof. When the substrate 12 is comprised of a semiconducting material, any semiconductor such as, for example, Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, InAs, InP and other III/V or II/VI compound semiconductors may be used. In addition to these listed types of semiconducting materials, the present disclosure also contemplates cases in which the semiconductor substrate is a layered semiconductor such as, for example, Si/SiGe, Si/SiC, silicon-on-insulators (SOIs) or silicon germanium-on-insulators (SGOIs). In some embodiments of the present disclosure, the semiconducting material may include one or more semiconductor devices formed thereon. For clarity the one or more semiconductor devices are not shown in the drawings.
When the substrate 12 is an insulating material, the insulating material can be an organic insulator, an inorganic insulator or a combination thereof including multilayers. When the substrate 12 is a conducting material, the substrate may include, for example, polySi, an elemental metal, alloys of elemental metals, a metal silicide, a metal nitride or combinations thereof including multilayers. When the substrate 12 comprises a combination of an insulating material and a conductive material, the substrate may represent one of interconnect levels which can positioned beneath the electronic structure of the present disclosure.
The first dielectric material 16 of the initial structure may include any interlevel or intralevel dielectric material including inorganic dielectrics and/or organic dielectrics. The first dielectric material 16 may be porous, non-porous or contain regions and/or surfaces that are porous and other regions and/or surfaces that may be non-porous. Some examples of suitable dielectrics that can be used as the first dielectric material 16 include, but are not limited to, silicon oxide, silsesquioxanes, C doped oxides (i.e., organosilicates) that include atoms of Si, C, O and H (called “SiCOH” materials), SiCOH materials containing porosity, thermosetting polyarylene ethers, or multilayers thereof. The term “polyarylene” is used in this application to denote aryl moieties or inertly substituted aryl moieties which are linked together by bonds, fused rings, or inert linking groups such as, for example, oxygen, sulfur, sulfone, sulfoxide, carbonyl and the like. In one embodiment, the first dielectric material 16 has a dielectric constant that is less than silicon oxide, i.e., less than 4.0. In another embodiment, first dielectric material 16 that can be employed in the present disclosure has a dielectric constant of 3.0 or less. All dielectric constants mentioned herein are relative to a vacuum, unless otherwise noted. Dielectrics which have a dielectric constant of less than that of silicon oxide generally have a lower parasitic cross talk as compared with dielectric materials that have a higher dielectric constant equal to, or greater than, silicon oxide. Generally, silicon oxide has a dielectric constant of 4.0.
In one embodiment, the first dielectric material 16 has a thickness from 50 nm to 1000 nm. In other embodiments, the first dielectric material 16 can have a thickness that is greater than or less than the thickness range mentioned above. The first dielectric material 16 can be formed utilizing a deposition process such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), evaporation, chemical solution deposition and spin-on coating.
After providing the first dielectric material 16, a plurality of openings can be formed into the first dielectric material 16. The plurality of openings may include a via opening, a line opening, a combined via and line opening, or any combination thereof. A via opening can be distinguished from a line opening in that the via opening has a narrower width than the line opening. In the particular embodiment illustrated in the drawings, a plurality of combined via and line openings are formed. In accordance with the present disclosure, the plurality of openings that are formed into the first dielectric material 16 are regularly spaced. By “regularly spaced” it is meant that the distance between a center point of one opening to a center point of a nearest neighboring opening is uniform and has a same value, known as the pitch.
The plurality of openings can formed by lithography and etching. When combined via and line openings are formed, a second iteration of lithography and etching can be used to form the same. The lithographic step may include forming a photoresist (organic, inorganic or hybrid) atop the first dielectric material 16. The photoresist can be formed utilizing a deposition process such as, for example, CVD, PECVD and spin-on coating. Following formation of the photoresist, the photoresist can be exposed to a desired pattern of radiation. Next, the exposed photoresist can be developed utilizing a conventional resist development process. After the development step, an etching step can be performed to transfer the pattern from the patterned photoresist into the first dielectric material 16. In one embodiment, a hard mask material such as, for example, titanium nitride and/or silicon nitride or silicon oxide, can be formed atop the first dielectric material 16 prior to forming the photoresist. In such an embodiment, the pattern may be first transferred into the hard mask material and then into the first dielectric material 16. In such an embodiment, the patterned photoresist is typically, but not necessarily always, removed from the surface of the structure after transferring the pattern into the hard mask material utilizing a resist stripping process such as, for example, ashing. The etching step used in forming the plurality of openings may include a dry etching process (including, for example, reactive ion etching, ion beam etching, plasma etching or laser ablation), a wet chemical etching process or any combination thereof. In one embodiment, reactive ion etching is used to form the plurality of openings.
Next, a diffusion barrier liner and a first conductive material are formed within each of the plurality of openings. The diffusion barrier liner (not shown) lines the wall portions within each opening and is thus positioned between the first dielectric material and the first conductive material. The first conductive material that is formed into each opening of the plurality of openings formed in the first dielectric material 16 provides the first regularly spaced array of conductors 18.
The diffusion barrier liner can include any material that can serve as a barrier to prevent conductive material ions from diffusing into the first dielectric material 16. Examples of materials that can be used as the diffusion barrier liner include, for example, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, IrTa, IrTaN, W, WN or a multilayered stack thereof. In one embodiment, the diffusion barrier liner has a thickness from 2 nm to 50 nm. In other embodiment, the diffusion barrier liner has a thickness from, with a thickness from 7 nm to 20 nm. The diffusion barrier liner can be formed by a deposition process including, for example, CVD, PECVD, physical vapor deposition (PVD), sputtering and plating.
The first conductive material includes for example, a conductive metal, an alloy comprising at least two conductive metals, a conductive metal oxide, a conductive metal nitride, a conductive metal silicide or any combination thereof. In one embodiment, the first conductive material can comprise Al, Ti, TiN, Ta, TaN, W, WN, MoN, Pt, Pd, Os, Ru, IrO2, ReO2, ReO3, or Cu. Mixtures or alloys of these conductive materials can also be employed in the present disclosure. The first conductive material can be formed by a deposition process including, for example, CVD, PECVD, PVD, sputtering, plating, chemical solution deposition and electroless plating.
After deposition of each of the diffusion barrier liner and the first conductive material, any excess diffusion barrier material and first conductive material that is located outside of each of the plurality of openings can be removed by a planarization process. In one embodiment, the planarization process includes chemical mechanical polishing (CMP). In another embodiment, the planarization process includes grinding. In a further embodiment, the planarization process includes a combination of CMP and grinding. In some embodiments and when a hard mask material is employed, the planarization process also removes remaining portions of the hard mask material that are located outside each of the plurality of opening and on the upper surface of first dielectric material 16.
Referring now to
In some embodiments, and as illustrated in
Referring now to
The array of openings 32 can be formed by lithography and etching as described above for forming the plurality of openings within the first dielectric material 16. Each opening of the array of openings 32 is located atop a conductor of the first regularly spaced array of conductors 18. The array of openings 32 that are formed at this point of the present disclosure are regular spaced as shown in the drawings. The term “regularly spaced” has the same meaning as mentioned above.
Referring now to
Exemplary materials for the diblock copolymer layer 34 are described in commonly-assigned, U.S. Pat. No. 7,605,081 issued Oct. 20, 2009, the contents of which are incorporated herein by reference. Specific examples of self-assembling block copolymers that can be used for forming the structural units of the present invention may include, but are not limited to, polystyrene-block-polymethylmethacrylate (PS-b-PMMA), polystyrene-block-polyisoprene (PS-b-PI), polystyrene-block-polybutadiene (PS-b-PBD), polystyrene-block-polyvinylpyridine (PS-b-PVP), polystyrene-block-polyethyleneoxide (PS-b-PEO), polystyrene-block-polyethylene (PS-b-PE), polystyrene-b-polyorganosilicate (PS-b-POS), polystyrene-block-polyferrocenyldimethylsilane (PS-b-PFS), polyethyleneoxide-block-polyisoprene (PEO-b-PI), polyethyleneoxide-block-polybutadiene (PEO-b-PBD), polyethyleneoxide-block-polymethylmethacrylate (PEO-b-PMMA), polyethyleneoxide-block-polyethylethylene (PEO-b-PEE), polybutadiene-block-polyvinylpyridine (PBD-b-PVP), and polyisoprene-block-polymethylmethacrylate (PI-b-PMMA). The self-assembling block copolymers are first dissolved in a suitable solvent system to form a block copolymer solution, which is then applied onto the surface of the structure shown in
After application and annealing the self-assembling block copolymer can be converted into diblock copolymer layer 34 that includes a first polymeric block copolymer component 36 and a second block copolymer component 38, which are randomly located within the diblock copolymer layer 34. In one embodiment, each first polymeric block copolymer component 36 is comprised of roughly spherical particles of a first dimension, and each second polymeric block copolymer component 38 is comprised of roughly spherical particles of a second dimension, wherein the first dimension differs from the second dimension. Each of the first dimension and second dimension is sub-lithographic. By “roughly spherical” it is meant that the component particles assemble in an ordered or partially ordered pattern, so the particle shape enables such a pattern. The anneal mentioned above may be performed, for example, at a temperature from 200° C. to 300° C. for a duration from less than 1 hour to 100 hours.
Referring now to
At this point of the present disclosure, the diblock copolymer layer 34 serves as a block copolymer mask 34′ which includes only one of polymeric block components which are randomly located therein. In some instances, and as shown in
Referring now to
As shown in
Referring now to
The resultant structure that is shown in
Referring now to
The electrical conductive material used in forming the electrical conductive vias 24A, 24B (and thus vias 24 in
In an alternate embodiment, the electrical conductive material used in forming the electrical conductive vias 24A, 24B (and thus vias 24 in
The reactive metal(s) react and release heat (via an exothermic reaction) when a current pulse is applied to the structure. Any current pulse that causes an exothermic reaction within the reactive metal(s) can be employed in the present disclosure. In one typical embodiment of the present disclosure, and for a bilayered structure of Al as the bottom layer of copper oxide as the top layer, the current pulse that can used to initiate the exothermic reaction is from 1 kA/cm2 to 10 MA/cm2. In another typical embodiment of the present disclosure, and for a bilayered structure of Al as the bottom layer and Ni as the top layer, the current pulse that can used to initiate the exothermic reaction is from 1 kA/cm2 to 10 MA/cm2.
As shown in
Referring now to
An energy source (not shown) may be connected to one of the first level and the third level. Examples of energy sources that can be used in the present disclosure include, but are not limited to, an off-chip battery, a power supply, a integrated miniature battery, capacitor, radioactive radiation cell, or another energy storage device integrated as part of the electronic structure. Upon detection of a tempering event, the energy source provides a current that flows through the electrical contact vias in the second level and removes electrical continuity.
In another embodiment of the present disclosure, the structure shown in
Electron beam lithography is then used to pattern the electron sensitive coating with a via array pattern including via patterns with different widths, such as, w1 and w2 mentioned in the previous embodiment of the present disclosure. The via patterns created in the electron beam sensitive coating are randomly oriented. Specifically, the array of via patterns can be controlled by a data file of X coordinates and Y coordinates as is known to one skilled in the art which can be inputted into a computer data base of the electron beam tool. The data file can be randomly altered based on application of a random number generator to remove via locations from the file. The array of via patterns of different widths is then transferred to the second dielectric material utilizing an etching process such as, for example, reactive ion etching. Following the transfer of the array of via patterns of different widths into the second dielectric material, the electron beam sensitive coating can be removed utilizing a conventional stripping process providing a structure similar to the one shown in
A third method embodiment can be used to form the electronic structure of the present disclosure. The third method embodiment of the present disclosure begins by first providing the structure shown in
The photoresist 50 that can be employed in the present disclosure includes any organic, inorganic or hybrid photoimageable material. Following coating of the photoresist 50, the photoresist 50 is subjected to a first lithographic patterning step using a mask to form a first pattern 52 in individual first regions 54 of the photoresist 50. The first pattern 52 can be formed by exposing the photoresist to ultraviolet radiation at a first dose that is less than an optimum dose. By “optimum dose” it is meant the dose in which is typically used in lithography to pattern the photoresist. In one embodiment, and for example, the first dose is about a half of the optimum dose.
Referring now to
The second pattern 56 can be formed by exposing the photoresist to ultraviolet radiation at a second dose which is also less than an optimum dose. In one embodiment, the first dose and the second dose add up to about the optimum dose.
The first and second patterns 52, 56 including regions 60, 62 and 64 are then transferred into the second dielectric material 22 utilizing an etching process such as reactive ion etching. After pattern transfer, photoresist 50 is stripped from the structure utilizing a conventional resist stripping process. After resist stripping, the resultant structure looks schematically similar to the structure depicted in
While the present disclosure has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present disclosure. It is therefore intended that the present disclosure not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
