Patent Application
20240429156
The semiconductor integrated circuitry (IC) industry has experienced rapid growth. Technological advances in IC design and material have produced generations of ICs where each generation has smaller and more complex circuits than previous generations. During the course of IC evolution, functional density (i.e., the number of interconnected devices per unit chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
As the semiconductor device scaling down continues, challenges in fabrication may arise. For example, a metal-insulator-metal (MIM) structure may be used to implement microelectronic components, such as capacitors. The MIM structure may be formed as a part of a copper redistribution layer (RDL) scheme. However, existing processes for implementing the copper RDL scheme may lead to subpar characteristics of the insulator layers in the MIM structure, such as poor crystallinity and/or lower-than-desired dielectric constant. As a result, the performance of the MIM structure may be degraded.
Therefore, although existing semiconductor fabrication methods have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.
Integrated Circuitry (IC) chips contain a plurality of different types of microelectronic components, such as transistors, resistors, inductors, capacitors, etc. For each of these types of microelectronic components, there may be a variety of methods of fabrication, resulting in different structures thereof. In some cases, capacitors may be implemented using a metal-insulator-metal (MIM) structure, in either a copper (Cu) redistribution layer (RDL) scheme or an aluminum copper (AlCu) RDL scheme. The MIM structure may include a plurality of metal-containing layers and a plurality of insulator layers, where each of the insulator layers is located between two respective metal-containing layers. In an existing copper RDL scheme, the MIM structure is embedded in a nitride-based material. For example, the layer directly above the MIM structure and the layer directly below the MIM structure in existing RDL schemes may both be silicon nitride. Unfortunately, silicon nitride does not promote good formation of a metal-containing layer (of the MIM structure) thereover. The situation is exacerbated when an insulator layer (of the same MIM structure) has to be formed over the poorly formed metal-containing layer, which could lead to poor crystalline quality of the insulator layer. In turn, the insulator layer may not be able to achieve a desired dielectric constant, and/or the MIM structure could experience failures such as time-dependent dielectric breakdown (TDDB). Consequently, IC device performance and/or yield may be degraded.
The present application pertains to an improved copper RDL scheme, in which a MIM structure is embedded in an oxide-based material, for example, in a silicon oxide (SiO2) material. The metal-containing layer of the MIM is formed directly on the oxide-based material, which promotes good formation of the metal-containing layer. The insulator layer that is subsequently formed over the metal-containing layer may also have a better crystal lattice structure in the present application (compared to existing copper based RDL schemes). As a result, the insulator layer may achieve a desired high dielectric constant, and failures such as TDDB may be reduced.
The process flow for implementing the copper RDL of the present disclosure is now discussed below with reference to
Referring now to
The IC structure 100 also includes an interconnection structure 120 formed over the semiconductor substrate. The interconnection structure 120 includes various conductive components, such as metal lines (e.g., metal line 130 or metal line 131), contacts, and vias, to provide horizontal and vertical electrical routing. The metal lines such as the metal line 130 are distributed in multiple levels of metal layers, such as a first metal layer (e.g., a M1 layer), a second metal layer (e.g., a M2 layer), . . . and a top metal layer. In some embodiments, the metal lines 130-131 belong to a topmost metal layer of the interconnect structure 120, and the metal lines and/or vias of the other metal layers of the interconnect structure 120 are not specifically illustrated herein for reasons of simplicity.
Among other things, the conductive components of the interconnection structure 120 may provide electrical connectivity to the electrical circuitry 115. The interconnection structure 120 also includes a dielectric material 140 to provide electrical isolation among the various conductive components, so as to prevent electrical shorting. In some embodiments, the dielectric material 140 may include an oxide material, such as silicon oxide. It may be said that the metal lines such as metal lines 130-131 are embedded in the dielectric material 140.
Referring now to
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It is understood that the above ranges of the thicknesses and the ratios are not randomly chosen but specifically configured. For example, if the thickness 180 is too low compared to the thickness 160 (i.e., the ratio of the thickness 180 and the thickness 160 is too small), then the dielectric layer 170 may not be sufficiently thick to serve as a good base layer on which to form the metal-containing layer of the MIM structure. In other words, the amount of improvement in quality of the metal-containing layer and the insulator layer of the MIM structure may be minimal. On the other hand, if the thickness 180 is too high compared to the thickness 160 (i.e., the ratio of the thickness 180 and the thickness 160 is too high), then the dielectric layer 150 may not be sufficiently thick to serve as a passivation structure. Here, by configuring the thicknesses 160 and 180 carefully, the dielectric layers 150 and 170 are optimized, in that the dielectric layer 150 can adequately serve as a passivation structure, while the dielectric layer 170 can serve as a good base material on which to form the metal-containing layer of the MIM structure.
Referring now to
The metal-containing layers and the insulator layers may each be formed by a plurality of deposition and patterning processes. For example, the metal-containing layer 210 may be formed by first depositing a layer of metal-containing material (e.g., TiN) over the upper surface of the dielectric layer 170, and subsequently patterning the deposited layer of metal-containing material using a lithography process. As a part of the lithography process, a patterned photoresist layer may be formed over the deposited layer of metal-containing material. Using the patterned photoresist layer as a mask, the deposited layer of metal-containing material may be etched. Portions of the deposited layer of metal-containing material not protected by the patterned photoresist layer are etched away, while portions of the deposited layer of metal-containing material located underneath the patterned photoresist layer are protected and may remain after the etching process is performed. The remaining portions of the deposited layer of metal-containing material forms the metal-containing layer 210. The rest of the metal-containing layers 211-212 may be formed using similar processes as those used to form the metal-containing layer 210. It is understood that each of the metal-containing layers 210-212 may serve as an electrode or a conductive plate of a capacitor of the MIM structure.
The insulator layers 220-221 may also be formed by a plurality of deposition processes (e.g., deposition processes to deposit the high-k dielectric material, such as HZO, over the respective metal-containing layers) and patterning processes. Note that each of the insulator layers 220-221 is disposed between two respective metal-containing layers. For example, the insulator layer 220 is disposed between the metal-containing layer 210 (which is located below the insulator layer 220) and the metal-containing layer 211 (which is located above the insulator layer 220). Meanwhile, the insulator layer 221 is disposed between the metal-containing layer 211 (which is located below the insulator layer 221) and the metal-containing layer 212 (which is located above the insulator layer 221). It is understood that the insulator layers 220-221 provide electrical isolation between the metal-containing layers 210-212. They also serve as the dielectric material that is sandwiched between the conductive plates/electrodes of the capacitor of the MIM structure 200.
As discussed above, existing copper RDL schemes form a bottommost one of metal-containing layer directly on an uppermost surface of a silicon nitride material. However, silicon nitride is not an ideal material for a high quality metal-containing layer to be formed directly thereon. For example, titanium nitride (as an example metal-containing layer) that is directly deposited on silicon nitride may exhibit a low amount of (111) plane in a Miller index. When an insulator layer is subsequently formed on the titanium nitride (or another suitable metal-containing layer material) with such a low amount of (111) plane, the resulting insulator layer may suffer from problems such as a low crystallinity and/or a low dielectric constant. In turn, the resulting MIM structure formed using existing copper RDL processes may suffer from reliability issues and/or defects such as time dependent dielectric breakdown (TDDB), which is when a dielectric material breaks down over time as a result of an application of a relatively low electric field. When TDDB occurs, the insulator layer may act more as a conductive layer, as electrical current may tunnel through the insulator layer. This may render the capacitor of the MIM structure non-functional, or at least function sub-optimally to the extent that it functions at all.
In comparison, the copper RDL process of the present disclosure forms the MIM structure 200 over an oxide-based material (e.g., silicon oxide), rather than over silicon nitride. For example, the metal-containing layer 210 (i.e., the bottommost one of the metal-containing layers) is deposited directly on an upper surface of the dielectric layer 170, which has a silicon oxide material composition. In embodiments where the metal-containing layer 210 has a titanium nitride material composition, the titanium nitride material of the metal-containing layer 210 (deposited directly on silicon oxide) may have a higher amount of (111) plane in the Miller index compared to titanium nitride material formed directly on silicon nitride. The insulator layer 220—which has a hafnium zirconium oxide material composition in this embodiment-is deposited directly on the titanium nitride material of the metal-containing layer 210 with the high amount of (111) plane. Hafnium zirconium oxide may have a favorable plane of (111) because it has low surface energy and stability against an epitaxial strain. As such, the hafnium zirconium oxide of the insulator layer 220 may have better/higher crystallinity and/or a greater dielectric constant. In turn, the resulting MIM structure 200 formed using the copper RDL process of the present disclosure is less likely to suffer from reliability issues and/or defects such TDDB, and therefore device performance, yield, and/or reliability may be improved.
Note that the capacitor of the MIM structure 200 is a multi-plate capacitor that may include more than just two conductive plates (or more than two metal-containing layers). For example, the capacitor of the MIM structure 200 as shown in
It is understood that
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As shown in
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Note that a portion of the RDL 400 protrudes vertically above the upper surface of the dielectric layer 250. In the cross-sectional side view of
The RDL 400 is a copper RDL in the illustrated embodiment, and as a conductive structure, it provides electrical connectivity between the components of the interconnect structure 120 (e.g., the metal line 130) and other microelectronic components. It is understood that the RDL 400 may also be used to provide electrical connectivity to the various components of the MIM structure 200 in some embodiments, depending on the exact configuration and/or location of the RDL 400.
It is also understood that one or more additional layers may optionally be formed over the RDL 400 in some embodiments. For example, a dielectric layer (e.g., a silicon nitride layer) and/or a silicon oxide layer may be formed over the RDL 400. These additional layers may serve as protective layers for the RDL 400. For reasons of simplicity, these additional optional layers are not specifically illustrated herein.
Referring now to
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A conductive structure 550 is also formed over the barrier layer 520 and fills the remainder of the opening 500. The conductive structure 550 may be formed using an electroplating process, which may involve forming a seed metal layer (e.g., a copper seed layer) on the barrier layer 520 and then forming the remainder of the conductive structure 550 on the seed metal layer. In some embodiments, an upper portion of the conductive structure 550 may be referred to as a bump pad metal 550A, and a lower portion of the conductive structure 550 may be referred to as a bump pad via 550B. In any case, the conductive structure 550 is electrically coupled to the RDL 400, and it may be used to gain electrical access to the rest of the IC structure 100. Furthermore, the conductive structure 550 may be used to connect to other conductive structures (e.g., other conductive bumps or conductive pads) that are external to the IC structure 100.
Note that although
The method 1000 includes a step 1020 to form a first portion of a second dielectric layer over the first dielectric layer. The second dielectric layer and the first dielectric layer have different material compositions. In some embodiments, a silicon oxide (SiO2) material is deposited as the first portion of the second dielectric layer.
The method 1000 includes a step 1030 to form a metal-insulator-metal (MIM) structure over the second dielectric layer. In some embodiments, the MIM structure is formed by depositing a first metal-containing layer over the second dielectric layer, depositing a first insulator layer over the first metal-containing layer, and depositing a second metal-containing layer over the first insulator layer. In some embodiments, the first metal-containing layer and the second metal-containing layer are deposited using titanium nitride (TiN). In some embodiments, the first insulator layer is deposited using hafnium zirconium oxide (HZO). In some embodiments, the forming of the MIM structure further comprises: depositing a second insulator layer over the second metal-containing layer, and depositing a third metal-containing layer over the second insulator layer.
The method 1000 includes a step 1040 to form a second portion of the second dielectric layer over the MIM structure and over the first dielectric layer, such that the MIM structure is embedded within the second dielectric layer in a cross-sectional side view. The second portion of the second dielectric layer has a same material composition as the first portion of the second dielectric layer. In some embodiments, a silicon oxide (SiO2) material is deposited as the second portion of the second dielectric layer.
The method 1000 includes a step 1050 to form a third dielectric layer over the second portion of the second dielectric layer. The third dielectric layer and the second dielectric layer have different material compositions. In some embodiments, the third dielectric layer is formed by depositing a second silicon nitride (SiN) material as the third dielectric layer.
The method 1000 includes a step 1060 to etch an opening that extends vertically through the third dielectric layer, the second dielectric layer, the MIM structure, and the first dielectric layer.
The method 1000 includes a step 1070 to form a conductive structure in the opening. In some embodiments, the conductive structure is formed by a copper electroplating (ECP) process.
It is understood that additional processes may be performed before, during, or after the steps 1010-1070 of the method 1000. For example, the method 1000 may include the following steps: depositing a passivation layer over the conductive structure and over the third dielectric layer, etching a recess in the passivation layer, the recess exposing a portion of the conductive structure, and forming a conductive via in the recess. For reasons of simplicity, other additional steps are not discussed herein in detail.
In summary, the present disclosure involves an improved copper RDL formation scheme. According to the copper RDL formation scheme of the present disclosure, the MIM structure (e.g., the MIM structure 200) is embedded in an oxide-based material, for example, in dielectric layers 170 and 240 that contain silicon oxide (SiO2). By doing so, the copper RDL scheme of the present disclosure offers advantages over conventional copper RDL schemes. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is improved reliability and/or defection reduction. In more detail, whereas existing copper RDL schemes form a metal-containing layer of the MIM structure on a nitride material, the present disclosure forms the metal-containing layer of the MIM structure directly on silicon oxide (e.g., the metal-containing layer 210 is formed directly on the dielectric layer 170, which contains silicon oxide). The formation of the metal-containing layer 210 on silicon oxide promotes the formation of a high quality metal-containing layer 210. The insulator layer 220 that is subsequently formed over the metal-containing layer 210 may also have a better crystal lattice structure in the present application compared to existing copper based RDL schemes. As a result, the insulator layer 220 may achieve a desired high dielectric constant and is less likely to break/fail. As such, failures such as TDDB may be reduced, and device performance and/or reliability may be improved. Other advantages include compatibility with existing fabrication and/or packaging processes, so the present disclosure does not require additional processing and is therefore easy and cheap to implement.
Thus, the present disclosure provides a device. The device includes a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer. The second dielectric layer and the first dielectric layer have different material compositions. A metal-insulator-metal (MIM) structure is embedded in the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer. The third dielectric layer and the second dielectric layer have different material compositions. The first dielectric layer or the third dielectric layer may contain silicon nitride (SiN), the second dielectric layer may contain silicon oxide (SiO2).
The present disclosure also provides a structure. The structure includes a first silicon nitride layer. A silicon oxide layer is located over the first silicon nitride layer. A metal-insulator-metal (MIM) structure is embedded in the silicon oxide layer. The MIM structure includes a plurality of metal-containing layers and insulator layers. Each of the insulator layers is located between two adjacent ones of the metal-containing layers. A second silicon nitride layer is located over the silicon oxide layer. A conductive structure extends vertically through the second silicon nitride layer, the silicon oxide layer, the MIM structure, and the first silicon nitride layer in a cross-sectional side view. The conductive structure contains copper but not aluminum.
The present disclosure further provides a method. A first dielectric layer is provided. A first portion of a second dielectric layer is formed over the first dielectric layer. The second dielectric layer and the first dielectric layer have different material compositions. A metal-insulator-metal (MIM) structure is formed over the second dielectric layer. A second portion of the second dielectric layer is formed over the MIM structure and over the first dielectric layer, such that the MIM structure is embedded within the second dielectric layer in a cross-sectional side view. The second portion of the second dielectric layer has a same material composition as the first portion of the second dielectric layer. A third dielectric layer is formed over the second portion of the second dielectric layer. The third dielectric layer and the second dielectric layer have different material compositions. An opening is etched that extends vertically through the third dielectric layer, the second dielectric layer, the MIM structure, and the first dielectric layer. A conductive structure is formed in the opening.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the detailed description that follows. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
