Patent Application
20250216336
This disclosure relates generally to semiconductor fabrication and more specifically to film metrology.
Device formation within microelectronic workpieces typically involves a series of manufacturing techniques related to the formation, patterning and removal of a number of layers of materials on a substrate. To meet the physical and electrical specifications of current and next generation semiconductor devices, various process flows are being developed to reduce feature size while maintaining structure integrity for various patterning processes. Many characterization techniques have therefore been developed for these process flow processes.
The present disclosure relates to a method of endpoint detection and an apparatus of executing the same.
According to a first aspect of the disclosure, a method of endpoint detection is provided. The method includes receiving a wafer classification model that includes wafer types, product types and end-point detection (EPD) algorithms. Each EPD algorithm corresponds to a respective wafer type and a respective product type. Initial data of a wafer measured by an optical instrument are received. The wafer classification model is executed based on the initial data to determine a wafer type, a product type and a EPD algorithm for the wafer or to determine whether the wafer or the optical instrument is faulty. An etching process is executed on the wafer to obtain a product. During the etching process, the EPD algorithm is run to obtain an etching depth using data associated with the etching process measured by sensors so that an endpoint time of the etching process is determined by the etching depth or a maximum endpoint time. A post-etching outlier model is executed to determine whether the product is faulty.
In some embodiments, when the wafer type, the product type and the EPD algorithm for the wafer are available in the wafer classification model, the wafer type, the product type and the EPD algorithm are determined for the wafer.
In some embodiments, when the wafer type, the product type and the EPD algorithm for the wafer are unavailable in the wafer classification model, the wafer or the optical instrument is determined to be faulty.
In some embodiments, an instrument diagnosis is executed to determine whether the optical instrument is faulty.
In some embodiments, when the optical instrument is faulty, a fault of the optical instrument is determined.
In some embodiments, when the optical instrument is not faulty, a fault of the wafer is determined by an incoming outlier model.
In some embodiments, when the product is faulty, whether an etching tool is faulty is determined based on an etching rate.
In some embodiments, when the etching tool is not faulty, an instrument diagnosis is executed to determine whether the optical instrument is faulty.
In some embodiments, when the optical instrument is not faulty, whether a reference wafer is faulty is determined.
In some embodiments, when the reference wafer is not faulty, the wafer is determined to be faulty prior to the etching process.
In some embodiments, an etching rate EPD algorithm is executed based on emission optical spectroscopy (OES) data and voltage-current (VI) data to obtain the etching rate.
In some embodiments, whether a structure of the wafer is uncovered by the etching process is determined using the data associated with the etching process.
In some embodiments, after the structure of the wafer is uncovered, the EPD algorithm is run to obtain the etching depth.
In some embodiments, the structure of the wafer includes a top of a transistor gate.
In some embodiments, when the etching depth reaches a target depth before the maximum endpoint time, the etching process is terminated when the target depth is reached.
In some embodiments, when the etching depth does not reach a target depth at the maximum endpoint time, the etching process is terminated at the maximum endpoint time.
In some embodiments, the initial data are normalized based on a reference wafer or an average of a plurality of wafers.
In some embodiments, the optical instrument includes a reflectometer.
In some embodiments, the initial data include reflectometry data, and the data associated with the etching process include emission optical spectroscopy (OES) data and reflectometry data.
According to a second aspect of the disclosure, an apparatus is provided. The apparatus includes a controller having a processor that is programmed to receive a wafer classification model that includes wafer types, product types and end-point detection (EPD) algorithm. Each EPD algorithm corresponds to a respective wafer type and a respective product type. Initial data of a wafer measured by an optical instrument are received. The wafer classification model is executed based on the initial data to determine a wafer type, a product type and an EPD algorithm for the wafer or to determine whether the wafer or the optical instrument is faulty. An etching process is executed on the wafer to obtain a product. During the etching process, the EPD algorithm is run to obtain an etching depth using data associated with the etching process measured by sensors so that an endpoint time of the etching process is determined by the etching depth or a maximum endpoint time. A post-etching outlier model is executed to determine whether the product is faulty.
Note that this summary section does not specify every embodiment and/or incrementally novel aspect of the present disclosure or claimed invention. Instead, this summary only provides a preliminary discussion of different embodiments and corresponding points of novelty. For additional details and/or possible perspectives of the invention and embodiments, the reader is directed to the Detailed Description section and corresponding figures of the present disclosure as further discussed below.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “top,” “bottom,” “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
The order of discussion of the different steps as described herein has been presented for clarity's sake. In general, these steps can be performed in any suitable order. Additionally, although each of the different features, techniques, configurations, etc. herein may be discussed in different places of this disclosure, it is intended that each of the concepts can be executed independently of each other or in combination with each other. Accordingly, the present invention can be embodied and viewed in many different ways.
In the drawings, like reference numerals designate identical or corresponding parts throughout the several views. Additionally, as used herein, the words “a”, “an” and the like generally carry a meaning of “one or more”, unless stated otherwise.
Furthermore, the terms, “approximately”, “approximate”, “about” and similar terms generally refer to ranges that include the identified value within a margin of 20%, 10%, or preferably 5%, and any values therebetween.
Key to many semiconductor flow processes is endpoint detection (EPD). Particularly, EPD reliability is critical in dry etch processes. Reflectometry is a simple technique, and yet reflectometry EPD is complex with many possible failure modes, making un-assisted troubleshooting difficult. No fault detection and classification (FDC) system for reflectometry currently exists. No dry etch in-situ reflectometer systems have been used for classification before.
Additionally, it is hard to meet the reflectometer EPD accuracy requirement without pattern-specific EPD configurations. Customers usually require plasma etch EPD solutions to be self-contained (e.g. not reliant on fab controller input). Information about the wafer pattern is not part of the plasma etch recipe, so the EPD system needs to be able to determine this information itself. For example in conventional technology, reflectometry without a classifier can be highly dependent on the wafer pattern/structure and pass/step.
Techniques herein utilize FDC to determine faults in, for example, three independent failure sources for EPD, including incoming wafer variations, etching rate (ER) variations that are too large to be compensated by EPD, and reflectometer system failures. As a result, manufacturability, in-situ performance and reliability of reflectometry EPD systems can be improved using FDC. System faults can be identified before they occur. Failures can be addressed with minimal input from engineers. System up time can be increased with the cost of operation reduced. Wafer patterns can be determined based on measurements taken by the reflectometry EPD system. Pre-etch measurement can be used for reflectometer FDC, improving system robustness.
Compared with existing techniques or practices, deployment of the EPD system in the present disclosure is simplified. Therefore, best possible EPD accuracy is achieved, and a pre-etch measurement system can enable other applications, such as FDC and etch rate monitoring.
In box 103, reflectivity measurement is conducted on the wafer to obtain an incoming reflectivity spectrum 105 that is used to run a wafer classification model 107 in box 111. The wafer classification model 107 can include information such as wafer types, product types and end-point detection (EPD) algorithms, and each EPD algorithm corresponds to a respective wafer type and a respective product type. For instance, wafer types can include information such as a wafer pattern of an incoming wafer which can characterized by the incoming reflectivity spectrum 105. Product types can include information such as what the wafer will become after the dry etching treatment, e.g. what pattern a corresponding product will have. The wafer classification model 107 can be configured to identify a corresponding wafer type and a corresponding product type (e.g. 113) of an incoming wafer based on the incoming reflectivity spectrum 105. Then, the wafer classification model 107 can be configured to select a corresponding EPD algorithm (e.g. 115) for the incoming wafer based on the corresponding wafer type and the corresponding product type (e.g. 113). The incoming reflectivity spectrum 105 and the wafer classification model 107 can be received from a third party or oneself, e.g. measured by an in-situ reflectometer of a corresponding etching tool.
In one embodiment, the EPD algorithm 115 can include a virtual metrology (VM) model. The VM model can be include an equation that calculates a critical dimension (CD), such as etching depth, on the wafer using reflectometer spectra as inputs for example. In another embodiment, the EPD algorithm 115 may be a conventional EPD algorithm that correlates reflectometer spectra with a change in wafer structure, without using virtual metrology methods. For instance, the EPD algorithm 115 may describe a wavelength range and a reflectivity value that indicates the target etching depth is reached, without modeling or predicting the depth outside of that range.
In box 123, an incoming outlier model 121 is executed to determine whether the wafer passes in oval 125. If not, an alarm is set off in box 127 and reported to a user. If yes, the process 100 proceeds to box 130 in which the EPD algorithm 115 is executed. Box 130 may begin with box 131 in which an etching process is started. During the etching process, data associated with the etching process, such as emission optical spectroscopy (OES) data and reflectometry data, are collected. The OES data and the reflectometry data can then be used to detect a top of a transistor gate in box 133.
In oval 135, if the top of the transistor gate is detected, meaning that the top of the transistor gate is uncovered by the etching process, the process 100 proceeds to box 141. Otherwise, an alarm is set off in box 137 and reported to a user. It should be understood that the top of the transistor gate is used for illustrative purposes only and that other structures (e.g. a specific material, a specific layer, a specific topography, etc.) of the wafer can be used as well.
In box 141, the EPD algorithm 115 is run to obtain an etching depth such as a recess depth. In oval 143, whether the EPD algorithm 115 is completed (e.g. whether a target depth is reached) before a maximum endpoint time is determined. If yes, the etching process is terminated when the target depth is reached. Otherwise, if the etching depth does not reach the target depth at the maximum endpoint time, an alarm is set off in box 147 and reported to a user. The process 100 proceeds to box 149 by running to an end of the etching process, e.g. terminating the etching process. In either case, a product and one or more reflectance spectra 151 are obtained.
It should be noted that boxes 131, 133, 135, 137 and 141 is one embodiment of box 130 for illustrative purposes. As discussed earlier, the EPD algorithm 115 can include a virtual metrology (VM) model having an equation or an algorithm without an equation. When the EPD algorithm 115 uses virtual metrology, then the optimal model (e.g. a corresponding VM model) will be determined by the wafer classification model 107 and sent to box 141. When the EPD algorithm 115 does not use virtual metrology, then the wafer classification model 107 will determine what other information is needed for the optimal EPD result. For example, this could be a specific wavelength range to use or a certain reflectivity value that indicates the target depth is reached. For the same reasons that different VM models are necessary, these kinds of values could vary between wafer/product types.
Particularly, the EPD algorithm 115 can be informed by the wafer classification model 107 to decide which EPD method to use (e.g. an equation versus an algorithm), which specific model (if any), whether or not to include a gate top detection step, and so on. In other words, the EPD algorithm 115 can include a plurality of embodiments (e.g. various VM equations and equation-less algorithms), and which embodiment of the EPD algorithm 115 is used for a specific wafer is determined by the wafer classification model 107, for example by analyzing the incoming reflectivity spectrum 105.
In box 155, a post-etching outlier model 153 is run to determine whether the product is an outlier in oval 157. If not, the process 100 proceeds to box 165 by running a next wafer. If yes, the process 100 proceeds to box 161 by running a failure detection and classification (FDC) model, which will be further explained in
In oval 205, whether the ER is within a range is determined. When the ER is outside the range, the etching tool is faulty so an etching tool trouble shooting is run in box 207. When the ER is within the range, the process 200 proceeds to box 211 to run instrument diagnosis for the reflectometer. Table 1 below shows some examples of reflectometer FDC items.
Referring back to
If the reference wafer spectrum is outside the range, the reference wafer is checked and determined to be faulty in box 223. If the reference wafer spectrum is within the range, the process 200 proceeds to box 225 in which the incoming wafer is determined to be faulty. In other words, the incoming wafer, prior to the etching process, had at least one faulty/defect that is undetected or undetectable by the incoming outlier model.
If classification is unsuccessful, the wafer does not belong to any of the wafer types in the wafer classification model 107. As a result, a corresponding wafer type, a corresponding product type and a corresponding EPD algorithm cannot be identified for the wafer. In other words, the wafer cannot be classified by the wafer classification model 107. Accordingly, the process 300 proceeds to box 307 in which etching is aborted and FDC is performed, for example using the process 200 in
In other words, the etching time can be calculated when the incoming film thickness 405, the target recess depth 407 and the ER 204 are known. As a result, the etching process can be terminated based on the (calculated) etching time so that the etching process is executed for the duration of the etching time in box 413.
Further, a controller 170 may optionally be included in the examples of
It will be recognized that the controller 170 may be coupled to various components of a corresponding etching tool to receive inputs from and provide outputs to the components. For example, the controller 170 can be configured to receive the incoming reflectivity spectrum 105 from an in-situ reflectometer of the etching tool. The controller 170 can also be configured to adjust knobs and control settings for the etching tool. Of course the adjustments can be manually made as well.
It will also be recognized that the controller 170 may be coupled to various components of the process 100 to receive inputs from and provide outputs to the components. For example, the controller 170 can be configured to receive a wafer type and a product type 113 and/or the EPD algorithm 115 from box 111. The controller 170 can further be configured to implement box 131, box 133, oval 135 and the like. For example, the controller 170 can implement boxes 101, 103 and 111 so that a user does not have to determine the wafer type and the product type 113 and/the EPD algorithm 115 manually for each wafer. Therefore, such a process can be automated without requiring input from an engineer or technician. Of course, one or more functions of the controller 170 can also be manually accomplished.
The controller 170 can be implemented in a wide variety of manners. In one example, the controller 170 is a computer. In another example, the controller 170 includes one or more programmable integrated circuits that are programmed to provide the functionality described herein. For example, one or more processors (e.g. microprocessor, microcontroller, central processing unit, etc.), programmable logic devices (e.g. complex programmable logic device (CPLD)), field programmable gate array (FPGA), etc.), and/or other programmable integrated circuits can be programmed with software or other programming instructions to implement the functionality of a proscribed plasma process recipe. It is further noted that the software or other programming instructions can be stored in one or more non-transitory computer-readable mediums (e.g. memory storage devices, FLASH memory, DRAM memory, reprogrammable storage devices, hard drives, floppy disks, DVDs, CD-ROMs, etc.), and the software or other programming instructions when executed by the programmable integrated circuits cause the programmable integrated circuits to perform the processes, functions, and/or capabilities described herein. Other variations could also be implemented.
It should be understood that descriptions above pertaining to the controller 170 in
In the preceding description, specific details have been set forth, such as a particular geometry of a processing system and descriptions of various components and processes used therein. It should be understood, however, that techniques herein may be practiced in other embodiments that depart from these specific details, and that such details are for purposes of explanation and not limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. Nevertheless, embodiments may be practiced without such specific details. Components having substantially the same functional constructions are denoted by like reference characters, and thus any redundant descriptions may be omitted.
Various techniques have been described as multiple discrete operations to assist in understanding the various embodiments. The order of description should not be construed as to imply that these operations are necessarily order dependent. Indeed, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
“Substrate” or “wafer” as used herein generically refers to an object being processed in accordance with the invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or un-patterned, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures. The description may reference particular types of substrates, but this is for illustrative purposes only.
The substrate can be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and/or a silicon-on-insulator (SOI) substrate. The substrate may include a semiconductor material, for example, a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. The Group IV semiconductor may include Si, Ge, or SiGe. The substrate may be a bulk wafer or an epitaxial layer.
Those skilled in the art will also understand that there can be many variations made to the operations of the techniques explained above while still achieving the same objectives of the invention. Such variations are intended to be covered by the scope of this disclosure. As such, the foregoing descriptions of embodiments of the invention are not intended to be limiting. Rather, any limitations to embodiments of the invention are presented in the following claims.
Aspects of the present disclosure are related to U.S. patent application Ser. No. 17/730,751 filed on Apr. 27, 2022 entitled “AUTONOMOUS OPERATION OF PLASMA PROCESSING TOOL”, U.S. patent application Ser. No. 17/025,651 filed on Sep. 18, 2020 entitled “VIRTUAL METROLOGY FOR WAFER RESULT PREDICTION”, and U.S. patent application Ser. No. 17/710,085 filed on Mar. 31, 2022 entitled “DATA FUSION OF MULTIPLE SENSORS”, all of which are incorporated herein by reference in their entirety.
