Claims
- 1. A method of depositing controlled volumes of solder on a circuit board, comprising the steps of:
- forming a first mask over the circuit board with openings to first select circuit board contacts;
- depositing solder onto the first select circuit board contacts in volumes consistent with the height of the first mask by molten solder immersion;
- positioning a stencil over the circuit board with openings to second select circuit board contacts;
- screen depositing solder paste into openings of the stencil.
- 2. The method recited in claim 1, comprising the further step of:
- reflowing the solder on the first and second select circuit board contacts to connect placed components.
- 3. The method recited in claim 2, wherein the first mask is formed from a material not wettable by solder.
- 4. The method recited in claim 2, wherein the first select circuit board contacts are of fine pitch and the second select circuit board contacts are of coarse pitch.
- 5. The method recited in claim 2, comprising the further step of:
- selectively depositing flux to hold components, before performing the step of reflowing the solder.
- 6. The method recited in claim 2, wherein the placed components are flip-chip die.
- 7. The method recited in claim 1, wherein the first mask is formed from a material not wettable by solder.
- 8. The method recited in claim 1, wherein the first select circuit board contacts are of fine pitch and the second select circuit board contacts are of coarse pitch.
- 9. A method of attaching fine pitch terminal components to a printed circuit board, comprising the steps of:
- forming a first mask over the printed circuit board;
- depositing solder on select fine pitch board contacts in volumes consistent with the height of the first mask by molten solder immersion;
- placing a stencil over the circuit board with openings aligned to select coarse pitch board contacts;
- screen depositing a solder paste through openings in the stencil;
- depositing flux over select fine pitch circuit board contacts;
- placing components; and
- reflowing the solder to connect placed components.
- 10. The system recited in claim 9, wherein the placed components are flip-chip die.
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is a division of application Ser. No. 315,746, filed Sep. 30, 1994, now U.S. Pat. No. 5,493,075; and is related to patent application Ser. No. 08/298,983, filed Aug. 31, 1994, now U.S. Pat. No. 5,492,266, and assigned to the assignee of the present application.
US Referenced Citations (8)
Non-Patent Literature Citations (6)
Entry |
IBM TDB, vol. 37, No. 02B, Feb. 1994, "Improvements in the Sacrificial Substrate Burn-In Methodology for Known Good Die", pp. 19-20. |
IBM TDB, vol. 30, No. 7, Dec. 1987, "Fine Pitch Printing for Surface Mounted Technology", pp. 314-315. |
Research Disclosure, Nov. 1988, No. 295, "Solder Mask Elimination on Printed Circuit Boards". |
Research Disclosure, Feb. 1992, No. 334, "Ladder Pattern for Soldering Circuit Board Ground Pads". |
Sandia National Laboratories, DE93 009631, "A Maskless Flip-Chip Solder Bumping Technique", Chu et al. |
Circuits Assembly, Feb. 1993, "A Step in the Right Direction", Payne et al, pp. 59-64. |
Divisions (1)
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Number |
Date |
Country |
Parent |
315746 |
Sep 1994 |
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