Patent Application
20240413102
The packages of integrated circuits are becoming increasing complex, with more device dies integrated in the same package to achieve more functions. For example, packages may be formed to include a plurality of device dies such as processors and memory cubes in the same package. The packages can include device dies formed using different technologies and have different functions bonded to the same device die, thus forming a system. This may save manufacturing cost and achieve optimized device performance.
In a package, a top die may be bonded to a bottom die through bonding. The top die is a part of a wafer, which is sawed into a plurality of identical top dies. The bonding of the top die to the bottom die may be performed through one of a plurality of bond schemes such as solder bonding, direct metal-to-metal bonding, hybrid bonding (including both of dielectric-to-dielectric bonding and metal-to-metal bonding), or the like.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
A package including a top die bonding to a bottom package component and the method of forming the same are provided. In accordance with some embodiments of the present disclosure, a top wafer is formed to include a plurality of device dies separated from each other by scribe lines. An etching process is performed to form trenches in the scribe lines. In each of the scribe lines, there may be a single trench formed. The trench is shallow, and the etching is stopped before reaching a semiconductor substrate (such as a silicon substrate) of the wafer. A laser grooving process is performed in the trench, followed by a sawing process using a sawing blade. By forming one shallow trench instead of two deep trenches in a scribe line, the spaces needed for sawing is reduced, and more chip area may be left in the resulting device dies and outside of the seal ring. This may reduce delamination propagation.
Embodiments discussed herein are to provide examples to enable making or using the subject matter of this disclosure, and a person having ordinary skill in the art will readily understand modifications that can be made while remaining within contemplated scopes of different embodiments. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.
In accordance with some embodiments, wafer 2 includes semiconductor substrate 20 and the features formed at a top surface of semiconductor substrate 20. Semiconductor substrate 20 may be formed of crystalline silicon, crystalline germanium, crystalline silicon germanium, or the like. Semiconductor substrate 20 may also be a bulk silicon substrate or a Silicon-On-Insulator (SOI) substrate. Shallow Trench Isolation (STI) regions (not shown) may be formed in semiconductor substrate 20 to isolate the active regions in semiconductor substrate 20. Although not shown, through-vias may be (or may not be) formed to extend into semiconductor substrate 20, and the through-vias are used to electrically inter-couple the features on opposite sides of wafer 2.
In accordance with some embodiments, wafer 2 includes integrated circuit devices (not shown), which may be formed on the top surface of semiconductor substrate 20. Example integrated circuit devices may include Complementary Metal-Oxide Semiconductor (CMOS) transistors, resistors, capacitors, diodes, and/or the like. The details of the integrated circuit devices are not illustrated herein. In accordance with alternative embodiments, wafer 2 is used for forming interposers, which are free from active devices and passive devices.
An Inter-Layer Dielectric (ILD, one of dielectric layers 32) is formed over semiconductor substrate 20, and fills the space between the gate stacks of transistors (not shown) in the integrated circuit devices. In accordance with some embodiments, the ILD is formed of Phospho Silicate Glass (PSG), Boro Silicate Glass (BSG), Boron-Doped Phospho Silicate Glass (BPSG), Fluorine-Doped Silicate Glass (FSG), silicon oxide, or the like. the ILD may be formed using spin coating, Flowable Chemical Vapor Deposition (FCVD), Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), or the like.
Contact plugs (not shown) are formed in the ILD, and are used to electrically connect the integrated circuit devices to overlying metal lines and vias 34. In accordance with some embodiments, the contact plugs are formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and/or multi-layers thereof. The formation of the contact plugs may include forming contact openings in the ILD, filling a conductive material(s) into the contact openings, and performing a planarization process (such as Chemical Mechanical Polish (CMP) process) to level the top surfaces of the contact plugs with the top surface of the ILD.
Interconnect structure 30 is formed over the integrated circuits. Interconnect structure 30 includes dielectric layers 32, which includes the ILD and the dielectric layers over the ILD. Interconnect structure 30 further includes metal lines and vias 34 formed in dielectric layers 32. The dielectric layers 32 over the ILD are alternatively referred to as Inter-Metal Dielectric (IMD) layers 32 hereinafter. In accordance with some embodiments, some lower ones of dielectric layers 32 are formed of a low-k dielectric material having a dielectric constant (k-value) lower than about 3.8, and may be lower than about 3.5 or about 3.0. The IMD hence may be extreme low-k dielectric layers. Dielectric layers 32 may be formed of a carbon-containing low-k dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), or the like. In accordance with alternative embodiments of the present disclosure, some or all of dielectric layers 32 are formed of non-low-k dielectric materials such as silicon oxide, silicon carbide (SiC), silicon carbo-nitride (SiCN), silicon oxy-carbo-nitride (SiOCN), or the like. Etch stop layers (not shown), which may be formed of silicon carbide, silicon nitride, aluminum oxide, aluminum nitride, or the like, or multi-layers thereof, may be formed between IMD layers 32, and are not shown for simplicity.
Metal lines and vias 34 are formed in dielectric layers 32. The metal lines 34 at a same level are collectively referred to as a metal layer hereinafter. In accordance with some embodiments, interconnect structure 30 includes a plurality of metal layers that are interconnected through vias. Metal lines and vias 34 may be formed through single damascene and/or dual damascene processes. Metal lines and vias 34 may include diffusion barriers and copper-containing metallic materials over the corresponding diffusion barriers. The diffusion barriers may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.
Metal lines 34 include metal lines/pads 34A, which are sometimes referred to as top metal lines/pads. Top metal lines/pads 34A are also collectively referred to as being a top metal layer. The respective dielectric layer 38 may be formed of a non-low-k dielectric material such as Undoped Silicate Glass (USG), silicon oxide, silicon nitride, and/or the like.
In accordance with some embodiments, dielectric layer 40 is formed over the top metal layer. It is appreciated that the illustrated dielectric layers 38, 40, and 42 are examples, and the wafer 2 may include different materials and layers than illustrated. Dielectric layer 40 represents the possible dielectric layer(s) that may be adopted in wafer 2. In accordance with some embodiments, dielectric layer 40 is formed of or comprises an inorganic dielectric material such as silicon oxide, silicon oxynitride, silicon oxy-carbide, silicon oxy carbo-nitride, USG, or the like.
In accordance with some embodiments, dielectric layer 42 is formed as a top surface layer of wafer 2. Dielectric layer 42 may be used for fusion bonding, and hence is alternatively referred to as bond film 42 hereinafter. Bond film 42 may be deposited using Plasma-Enhanced Chemical Vapor Deposition (PECVD), Atomic Layer Deposition (ALD), High Density Plasma Chemical Vapor Deposition (HDPCVD), Plasma Enhanced ALD (PECVD), or the like. Bond film 42 may be formed of or comprise a silicon-containing dielectric material. In accordance with some embodiments, the material of bond film 42 may be expressed as SiOxNyCz, with x being in the range between about 0 and about 2, y being in the range between about 0 and about 1.33, and z being in the range between about 0 and about 1. At least one or more of values x, y, and z is greater than zero. For example, bond film 42 may be formed of or comprises SiON, SiN, SiOCN, SiCN, SiOC, SiC, SiO2, or the like. Bond film 42 may be formed of a dielectric material different from, or same as, the dielectric material of dielectric layer 40.
As also shown in
Referring to
In accordance with some embodiments, each device die 4 may include a single seal ring. Alternatively, each device die 4 may include a plurality of seal rings, with outer seal ring(s) encircling the respective inner seal ring(s)s. When more than one seal ring is formed for each of device dies 4, the illustrated seal ring 50 is the outmost seal ring that is closest to the scribe lines.
Referring back to
In accordance with some embodiments, seal rings 50 are electrically connected to semiconductor substrate 20 through the respective contact plugs. There may be (or may not be) silicide regions between and physically joining the contact plugs and semiconductor substrate 20. In accordance with alternative embodiments, the contact plugs are in physical contact with semiconductor substrate 20. In accordance with yet alternative embodiments, the contact plugs are spaced apart from semiconductor substrate 20 by a dielectric layer such as a contact etch stop layer (underlying the ILD), the ILD, and/or the like.
In accordance with some embodiments, dummy conductive features 52 are formed in scribe line 6, and outside of the seal rings 50 of device dies 4. In accordance with alternative embodiments, no dummy conductive features 52 are formed, and hence dummy conductive features 52 are illustrated as being dashed to indicate that these features may be or may not be formed. In accordance with some embodiments, dummy conductive features 52 are referred to as testing conductive features, which are used for testing the functionality of device dies. The testing may be performed by probing dummy conductive pads 54, which are the top surface features of dummy conductive features 52. The testing is performed before the subsequently discussed singulation process of wafer 2.
In accordance with some embodiments, there may be some dummy conductive features 56 formed in scribe lines 6, which conductive feature are also dummy features. In accordance with some embodiments, dummy conductive features 56 are formed at or close to the center of the respective scribe line 6. In accordance with some embodiments, as aforementioned, dummy conductive features 52 include dummy metal pads 54, whose top surfaces are coplanar with the top surface of bond film 42. The top surfaces of dummy conductive features 56, on the other hand, may be level with or lower than the bottom surface of bond film 42, and may be level with or lower than the top surface of lower surface of any underlying dielectric layer. Accordingly, between the bottom surface of bond film 42 and the topmost surfaces of dummy conductive features 56, there is one or more dielectric layer(s). Dummy conductive features 56 may be electrically connected to dummy conductive features 52, or may electrically decoupled from dummy conductive features 52.
Referring to
Referring to
The patterned etching mask 58 covers entireties of device dies 4, and further extend directly over (and overlap) some portions of scribe lines 6. In accordance with some embodiments in which dummy conductive features 52 are formed, etching mask 58 may cover some or all of dummy conductive features 52. Dummy conductive features 56 may be directly underlying trench 60.
An anisotropic etching process is then performed to etch wafer 2, so that trench 60 further extends down into the top portion of wafer 2. Bond film 42 is etched-through. In accordance with some embodiments, trench 60 extends to a same level of the bottom surface of bond film 42 (within process variation). In accordance with some embodiments, the etching includes a dry etching process, which may be a plasma etching process. In accordance with some embodiments, depending on the material of bond film 42 and dielectric layer 40, the etching gas may include the mixture of NF3 and NH3, the mixture of HF and NH3, or gases such as CF4, NF3, SF6, CHF3, ClF3, or combinations thereof. Other gases such as O2, N2, H2, NO, and the like, may also be added. Sputtering gas such as argon may be added, so that some sputtering may be used to enhance the anisotropic effect.
In the etching process, dielectric layer 40 may be used as an etch stop layer in accordance with some embodiments when dielectric layer 40 is formed of a dielectric material that is different from the dielectric material of bond film 42. In accordance with some embodiments in which bond film 42 is formed of a same dielectric material as dielectric layer 40, or bond film 42 and dielectric layer 40 comprise different dielectric materials, but the difference is not adequate to result in enough etching selectivity, the etching may also be performed using a time mode to stop the etching.
The bottom of trench 60 is higher than the top surface of substrate 20. In accordance with some embodiments, the etching is stopped at a level higher than the topmost surface of dummy conductive features 56. Accordingly, a dielectric layer, which may be a remaining portion of dielectric layer 40, may be left over dummy conductive features 56 at the time the etching is stopped. In accordance with alternative embodiments, the etching is stopped at a time after the topmost surface of the dummy conductive features 56 is exposed. In the etching process, dummy conductive features 56 may not be etched. Accordingly, the bottom of trench 60 may also be level with (within process variation) or lower than the topmost surface of dummy conductive features 56, which possible bottoms of trench 60 are illustrated using dashed lines 60B1 and 60B2 in
Also, as shown in
In accordance with some embodiments, between dummy conductive features 56 and dummy conductive features 52, a chip region that is free from metallic features may be formed, and is referred to as a metal-free strip hereinafter. When a scribe line includes two dummy conductive features 52 on the opposing sides of dummy conductive features 56, there are two metal-free strips, each being on a side of the dummy conductive features 56. When viewed in the top view of wafer 2, for example, as shown in
Referring to the top view of wafer 2 as shown in
After the etching process, the etching mask 58 as shown in
After the backside grinding process, wafer 2 is detached from back-grinding tape 64. Next, as shown in
In accordance with some embodiments, the laser grooving process 68 is performed until the bottom of trench 70 at least reaches, or may extend into semiconductor substrate 20. During the laser grooving process 68, dummy conductive features 56 (
In accordance with some embodiments, a plurality of trenches 70 are formed in wafer 2, each in one of scribe lines 6 and in a corresponding trench 60. In the top view of wafer 2, the trenches 70 are also interconnected as a grid. In the top view, trenches 70 are inside, and are narrower than, the corresponding trenches 60, and the edges of trenches 70 are spaced apart from the edges of trenches 60, as can also be realized from
In the laser grooving process, dummy conductive features 52, when formed, are not removed, and are laterally spaced apart from trenches 60 and 70. Laser grooving tends to cause protrusion on the top surfaces of the regions surrounding the regions that receive the laser beam. If the laser grooving is performed on the wafer 2 as shown in
In addition, since trench 60 is shallow, it is easy to remove the residue of etching mask 58 (such as photoresist) that is possibly left in trench 60. Otherwise, if deep trenches are formed, for example, with two deep trenches formed on opposite sides of dummy conductive features 56 and extending into substrate 20, since the deep trenches have high aspect ratios, it is difficult to remove the residues of the photoresist.
Referring to
As shown in
In accordance with some embodiments, device die 4 includes step 76, which is formed outside of seal ring 50, and may be on the outer side of dummy conductive features 52 if they are formed. The step 76 is formed in addition to step 78, which is formed adjacent to the top surface and a sidewall of semiconductor substrate 20.
The bonding of device die 4 to the package component 84 may include hybrid bonding, which includes the bonding of dielectric layer 86 to bond film 42 through dielectric-to-dielectric bonding, and the bonding of bond pads 46 to bond pads 88 through direct metal-to-metal bonding. The dielectric-to-dielectric bonding may include fusion bonding, which includes the formation of Si—O—Si bonds. The dummy bond pads 54 of dummy conductive features 52 may be also be bonded to dummy bond pads 88D of bond pads 88. In accordance with some embodiments, before the bonding process, dummy bond pads 88D may be electrically floating. After the bonding process, the combined feature including dummy bond pads 88D and dummy bond pads 54 may be or may not be electrically floating.
Device die 4 may then be encapsulated in encapsulant 90. In accordance with some embodiments, encapsulant 90 includes a molding compound, a molding underfill, or the like. In accordance with alternative embodiments, encapsulant 90 is formed of an inorganic material(s). For example, encapsulant 90 may include adhesion layer 90A, which may be formed of or comprise silicon nitride, and dielectric region 90B, which may be formed of or comprise silicon oxide.
In accordance with some embodiments, device die 4 includes a plurality of different widths W6, W7, and W8 measured at different levels. In accordance with some embodiments, width W6 is measured at a level in semiconductor substrate 20, width W7 is measured at a level in one of dielectric layers such as dielectric layer 38, and width W8 is measured at a level in bond film 42. Due to the formation of trenches before the die-saw processes, Width W6 is greater than width W7, and width W7 is greater than width W8.
Device die 4 includes portions 74 remaining outside of seal ring 50. The remaining portion 74A on the left side of the left portion of seal ring 50 has width W9, and the remaining portion 74B on the right side of the right portion of seal ring 50 has width W10. In accordance with some embodiments, width W9 is equal to width W10. In accordance with some embodiments, due to the formation of a single trench (rather than two trenches), it is possible to allow widths W9 and W10 to have greater values. For example, widths W9 and W10 may be greater than about 1.5 μm, and may be in the range between about 1.5 μm and about 90 μm. Since the remaining portions 74 are wider with greater widths W9 and W10, if delamination occurs at cutting line 72 during the die-saw processes, for example, between the low-k dielectric layers 32, the propagation path is longer before the delamination may propagate to seal ring 50. The integrated circuit devices in the active areas of the device dies, which active areas are inside seal rings, is less likely to be adversely affected.
Also, due to the formation of a single trench (rather than two trenches), it is possible to allow width W9 to be different from width W10. The width difference |(W9−W10)| may be greater than about 1.0 μm, and may be in the range between about 1.0 μm and about 80 μm. The width difference may be generated by making spacing S1 (
In accordance with some embodiments, width W9 is different from width W10. For example,
Similarly, the remaining portion of device die 4A on the side facing toward device die 4B has width W9′, and the remaining portion of device die 4A on the side facing away device die 4B has width W10′. In accordance with some embodiments, width W9′ is smaller than width W10′, while width W9′ may also be equal to width 10′ in accordance with alternative embodiments.
In above-illustrated embodiments, some processes and features are discussed in accordance with some embodiments of the present disclosure to form a three-dimensional (3D) package. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.
The embodiments of the present disclosure have some advantageous features. By forming shallow trenches in scribe lines, performing laser grooving in the shallow trenches, and then sawing the wafer, less space is needed in scribe lines for the die-saw process since a single trench, rather than two trenches, is formed in one scribe line. Accordingly, outside of the seal ring, more chip areas are left in the resulting dies, and the propagation path of delamination is longer. Delamination and cracks are less likely to propagate to seal rings. The device die is thus more reliable. Furthermore, by forming shallow trenches instead of forming deep trenches, it is easier to clean the residue inside the shallow trench.
In accordance with some embodiments of the present disclosure, a method comprises etching a portion of a wafer to form a first trench in a scribe line of the wafer, wherein the scribe line is between a first device die and a second device die of the wafer, and wherein after the etching, a top surface of the portion of wafer in the scribe line is underlying and exposed to the first trench, and the first trench is between opposing sidewalls of the wafer; performing a laser grooving process to form a second trench extending from the top surface further down into the wafer, wherein the second trench is laterally between the opposing sidewalls of the wafer; and performing a die-saw process to saw the wafer, wherein the die-saw process is performed from a bottom of the second trench, and wherein the die-saw process results in the first device die to be separated from the second device die.
In an embodiment, the scribe line has a middle line in middle of the first device die and the second device die, and wherein the first trench crosses the middle line. In an embodiment, the scribe line comprises a dummy conductive feature, and wherein the first trench overlaps the dummy conductive feature. In an embodiment, the etching is stopped before the dummy conductive feature is exposed. In an embodiment, the wafer comprises a top surface dielectric layer, and an underlying dielectric layer underlying the top surface dielectric layer, and wherein the etching stops on an additional top surface of the underlying dielectric layer. In an embodiment, the die-saw process is performed at a position closer to the first device die than the second device die.
In an embodiment, the first device die comprises a first seal ring, and the second device die comprises a second seal ring, and wherein the wafer further comprises a test conductive feature in the scribe line, and the test conductive feature is between the first seal ring and the first trench. In an embodiment, at a time when the first trench finishes formation, the scribe line has a single trench therein. In an embodiment, the etching is performed through an anisotropic etching process. In an embodiment, the second trench formed by the laser grooving process reaches a semiconductor substrate of the wafer.
In accordance with some embodiments of the present disclosure, a structure comprises a device die comprising a semiconductor substrate; a seal ring over the semiconductor substrate and encircling an active area of the device die; a first dielectric layer over the semiconductor substrate; a second dielectric layer over the first dielectric layer, wherein the second dielectric layer extends lateral beyond the first dielectric layer; and a first bond pad in the second dielectric layer. In an embodiment, the structure further comprises a package component overlying and bonding to the device die, wherein the package component comprises a second bond pad bonding to the first bond pad; and a third dielectric layer, wherein the second bond pad is in the third dielectric layer, and wherein the third dielectric layer is bonded to the second dielectric layer of the device die.
In an embodiment, the structure further comprises an encapsulant encapsulating the device die, wherein the encapsulant contacts a top surface of the first dielectric layer to form an interface. In an embodiment, a first portion of the encapsulant overlaps a second portion of the first dielectric layer. In an embodiment, the structure further comprises a test conductive feature outside of the seal ring. In an embodiment, the structure further comprises a package component overlying and bonding to the device die, wherein the test conductive feature is further bonded to an additional bond pad in the package component. In an embodiment, the device die comprises a first portion and a second portion outside of, and on opposing sides of the seal ring, wherein the first portion is narrower than the second portion.
In accordance with some embodiments of the present disclosure, a structure comprises a device die comprising a semiconductor substrate, wherein the device die has a first width measured at a first level of the semiconductor substrate; a first dielectric layer over the semiconductor substrate, wherein the device die has a second width measured at a second level of the first dielectric layer, and the second width is smaller than the first width; and a second dielectric layer over the first dielectric layer, wherein the device die has a third width measured at a third level of the second dielectric layer, and the third width is smaller than the second width; and a package component over and bonding to the device die.
In an embodiment, each of the first width, the second width, and the third width is measured from a first outmost edge of the device die to an opposing outmost edge of the device die. In an embodiment, the device die further comprises a seal ring proximate edges of the device die; and a test conductive feature outside of the seal ring, wherein the seal ring is in physical contact with the package component.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application claims the benefit of the following provisionally filed U.S. patent application: Application No. 63/507,150, filed on Jun. 9, 2023, and entitled “Cost Effective Dummy for Hybrid Bonding-Extra Low K Integrity;” which application is hereby incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63507150 | Jun 2023 | US |
