Patent Application
20170336467
Generally, the present disclosure relates to the field of integrated circuits and semiconductor devices and, more particularly, to gate protection for HV-stress application for SOI devices.
The fabrication of advanced integrated circuits, such as CPUs, storage devices, application specific integrated circuits (ASICs) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors (FETs), wherein, for many types of complex circuitry, metal-oxide-semiconductor (MOS) technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, complementary MOS (CMOS) technology, millions of N-channel transistors and P-channel transistors are formed on a substrate including a crystalline semiconductor layer.
A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits. As the channel length is reduced, the thickness of the gate dielectric is also reduced. The scaling of the gate dielectric is limited by several factors, such as defects, power supply voltage, time-dependent dielectric breakdown and leakage currents.
Typically, metal gate CMOS transistors are developed for low-voltage applications, such as processors and system on chip (SoC) devices. But these devices are connected to the outside world and require input/output (I/O or IO) transistors that support higher bias voltages. Modern technologies particularly require high performance transistors. Such high performance transistors typically require shallow source/drain (S/D) implants. IO transistors are typically formed using the same S/D implants. These S/D implants exhibit breakdown voltages in the range of 6-9 V. This is sufficient for operation, since typical IO voltages range today from 1.8 V to 2.5 V or 3.3 V. However. IO devices carrying these IO transistors must have thicker gate oxide layers so that the devices can operate at the higher IO voltages.
However plasma-induced damages of gate dielectrics, such as so-called antenna effects, occurring during the overall processing of the semiconductor devices pose severe problems and may significantly affect yield and reliability of the semiconductor devices. The damages comprise plasma charging damages that particularly occur when electrical charges are collected from the plasma by the gate electrode and flow through the gate dielectric. For example, the antenna effect is caused by polysilicon, metal or contact etching and ion implantation. During manufacturing, gate protection diodes may be used in order to prevent damage of the gate oxides due to plasma processes, namely mainly etch processes. For example, this particularly applies for back end of line (BEOL), which is the second portion of integrated circuit (IC) fabrication. Here the individual devices, such as transistors, capacitors, resistors, etc., get interconnected with wiring on the wafer, e.g., the metallization layer. Common metals are copper interconnect and aluminum interconnect. BEOL processing is a stage of processing that is generally understood to begin when the first layer of metal is deposited on the wafer. BEOL processing includes formation of contacts, insulating layers, e.g., dielectrics, metal levels, and bonding sites for chip-to-package connections. These gate protection diodes are active elements connected in parallel to the transistor gate-to-bulk connection. The realization of these protection diodes is commonly done with the S/D diodes as standalone elements. Consequently, there can be no higher voltages applied to transistor gates as is defined by the breakdown voltage of the protection diodes.
Commonly, for testing the above devices, electrical test structures are used. Electrical test structures are not only used for electrical parameter determination, but are also used for establishing reliability assessments which are required for monitoring such devices. One possibility for test measurements is to directly contact the test structure on a silicon wafer. Another possibility is to conduct the measurements after dicing and packaging of the test structure.
A device under test (DUT) is a die on a wafer or the resulting packaged part, a circuit element or block to be characterized by the test measurements. A DUT may also include a number of these circuit elements and blocks connected together to form a single unit, such as an array of MOSFETs. A test structure includes a DUT and a peripheral circuitry required for carrying out the test measurements. A macro test structure or macro may include one or more test structures. Test structures within a macro may share peripheral circuits and I/O pads to improve silicon area utilization and test efficiency.
This is shown in
However, the test structure 100 may also be interfaced with some testing equipment provided on a testing area, as shown in
In principle, DUTs such as the ones shown in
In order to obtain reasonable measurement times, the reliability investigation makes use of voltage acceleration. Voltage acceleration typically includes higher voltages which are to be applied to the respective gates of the transistors of the IO devices. This is also called a stress test. For such stress tests, so-called overvoltages are applied, which are, e.g., surges, fast, short duration electrical transients. These overvoltages to be used for the stress tests may need to have different magnitudes depending upon the devices to be tested. For logic transistors, the required overvoltages are relatively small, i.e., ranging from 4-5 V for a 1.0 V transistor. However, the overvoltages required for 3.3 V transistors rather range in the region of 13-15 V in order to achieve reasonable voltage acceleration factors.
This is shown in
In view of the above requirements for selecting the appropriate stress overvoltages for the transistors and possible other DUTs to be tested, the problem arises that the gate protection diodes do not allow such high stress overvoltage application when applied to the DUTs, e.g., the gate protection diodes may be destroyed by applying the stress overvoltages.
Therefore, and in view of the most recent 22FDX technology, there is a need of finding an alternative solution for protecting the test structures.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally the subject matter disclosed herein relates to test structures for a semiconductor device including a device under test including a transistor, the transistor having a gate electrode, a source electrode, a drain electrode and a bulk electrode, a first fuse and a second fuse provided in series, wherein one terminal of the first fuse is connected to the gate electrode, one terminal of the second fuse is connected to the bulk electrode, the other terminal of the first fuse and the other terminal of the second fuse being connected to each other, a first input/output pad connected to the first terminal of the first fuse and to the gate electrode of the transistor, a second input/output pad connected to the first terminal of the second fuse and to the bulk electrode of the transistor, a third input/output pad connected to the second terminal of the first fuse and the second terminal of the second fuse. It should be understood that the terms input/output pad, contact pad and contacting pad are used synonymously throughout this text.
The subject matter disclosed herein also relates to a fuse for test structures in integrated semiconductor technology, including a symmetrical body having two terminals each of a maximum width of 100-500 nm, the terminals connected by a melting wire, the melting wire having a thickness or diameter of 20-1000 nm and the melting wire having a length of 0.1-10 μm. It should be understood that, while the 22FDX technology may be a prominent example for an integrated semiconductor technology for applying the present disclosure, the present disclosure is not limited to 22FDX technology, but instead may be applied in all integrated semiconductor technologies.
The subject matter disclosed herein also relates to a semiconductor device with a test structure including a power line, a silicon-on-insulator (SOI) substrate comprising a semiconductor layer and a semiconductor bulk substrate comprising a doped region, a transistor formed in and above the SOI substrate and comprising a gate dielectric formed over the semiconductor layer and a gate electrode formed over the gate dielectric, the transistor having a gate electrode, a source electrode, a drain electrode and a bulk electrode, wherein the test structure includes a device under test including the transistor, a first fuse and a second fuse provided in series, wherein one terminal of the first fuse is connected to the gate electrode, one terminal of the second fuse is connected to the bulk electrode, the other terminal of the first fuse and the other terminal of the second fuse being connected to each other, a first input/output pad connected to the first terminal of the first fuse and to the gate electrode of the transistor, a second input/output pad connected to the first terminal of the second fuse and to the bulk electrode of the transistor, and a third input/output pad connected to the second terminal of the first fuse and the second terminal of the second fuse.
The subject matter disclosed herein also relates to a method of manufacturing a semiconductor device with a test structure including providing a silicon-on-insulator (SOI)) semiconductor substrate comprising a semiconductor layer and a semiconductor bulk substrate comprising a doped region, forming a transistor in and above the SOI substrate, the transistor comprising a gate dielectric formed over the semiconductor layer and a gate electrode formed over the gate dielectric, the transistor having a gate electrode, a source electrode, a drain electrode and a bulk electrode, providing the test structure including a device under test including the transistor, providing a first fuse and a second fuse in series, connecting one terminal of the first fuse to the gate electrode, connecting one terminal of the second fuse to the bulk electrode, connecting the other terminal of the first fuse and the other terminal of the second fuse to each other, providing a first input/output pad connected to the first terminal of the first fuse and to the gate electrode of the transistor, providing a second input/output pad connected to the first terminal of the second fuse and to the bulk electrode of the transistor, and providing a third input/output pad connected to the second terminal of the first fuse and the second terminal of the second fuse.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The following embodiments are described in sufficient detail to enable those skilled in the art to make use of the disclosure. It is to be understood that other embodiments would be evident, based on the present disclosure, and that system, structure, process or mechanical changes may be made without departing from the scope of the present disclosure. In the following description, numeral-specific details are given to provide a thorough understanding of the disclosure. However, it would be apparent that the embodiments of the disclosure may be practiced without the specific details. In order to avoid obscuring the present disclosure, some well-known circuits, system configurations, structure configurations and process steps are not disclosed in detail.
The present disclosure will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details which are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary or customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition shall be expressively set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present methods are applicable to a variety of technologies, e.g., NMOS, PMOS, CMOS, etc. The techniques and technologies described herein may be utilized to fabricate MOS integrated circuit devices, including NMOS integrated circuit devices, PMOS integrated circuit devices and CMOS integrated circuit devices. The application of the disclosed protection may be applied in particular but is not limited to transistor DUTs, capacitor DUTs, metal-oxide-metal capacitor DUTs inversion capacitor DUTs, comb-meander test structure DUTs, etc.
In view of the problems discussed above with respect to
In summary a test structure design and a fuse design for use in integrated semiconductor technology, in particular 22FDX technology, is disclosed. The test structure disclosed allows for sufficient overvoltage application for accelerated life test of transistors with higher I/O voltages in modern process technologies. It provides a functional solution for ZG device test structures, in particular in 22FDX technology. In particular, it provides sufficient gate oxide protection during manufacturing against plasma-induced damage. Furthermore, implant changes during technology development are not influencing the protection scheme.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a shorthand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required. Accordingly, the protection sought herein is as set forth in the claims below.
