Patent Grant
8759170
This document relates generally to semiconductor devices and device fabrication, including devices having a high-K dielectric.
The semiconductor device industry has a market-driven need to reduce the size of devices used in products such as processor chips, mobile telephones, and memory devices such as dynamic random access memories (DRAMs). Currently, the semiconductor industry relies on the ability to reduce or scale the dimensions of its basic devices. This includes scaling a dielectric layer in devices such as capacitors and silicon-based metal oxide semiconductor field effect transistors (MOSFETs), which have primarily been fabricated using silicon dioxide. Thermally-grown SiO2 provides an electrically and thermodynamically stable material, where the interface of the SiO2 layer with underlying silicon provides a high quality interface as well as desirable electrical isolation properties. However, increased scaling in microelectronic devices has made the use of SiO2 less useful because of its band gap behavior and the resulting possibility of shorting.
To scale a dielectric region to reduce feature sizes and to provide higher density electronic devices, the dielectric region may have a reduced equivalent oxide thickness (teq). The equivalent oxide thickness quantifies the electrical properties, such as capacitance, of a dielectric in terms of a representative physical thickness. Teq is defined as the thickness of a theoretical SiO2 layer that would be required to have the same capacitance density as a given dielectric, ignoring leakage current and reliability considerations.
A SiO2 layer of thickness t, deposited on a silicon surface may have a teq larger than its thickness t. This teq results from the capacitance in the surface on which the SiO2 is deposited due to the formation of a depletion/inversion region. This depletion/inversion region can result in teq being from 3 to 6 Angstroms (Å) larger than the SiO2 thickness, t. Thus, with the semiconductor industry driving to someday scale a gate dielectric equivalent oxide thickness to less than 10 Å, the physical thickness requirement for a SiO2 layer used for a gate dielectric may be approximately 4 to 7 Å. Additional requirements on a SiO2 layer would depend on the electrode used in conjunction with the SiO2 dielectric. Using a conventional polysilicon electrode may result in an additional increase in teq for the SiO2 layer. Thus, designs for future devices may be directed towards a physical SiO2 dielectric layer of about 5 Å or less. Such a reduced thickness in a SiO2 oxide layer creates additional problems.
SiO2 is used as a dielectric layer in devices, in part, due to its electrical isolation properties in a SiO2—Si based structure. This electrical isolation is due to the relatively large band gap of SiO2 (8.9 eV), making it a good insulator from electrical conduction. Significant reductions in its band gap may eliminate it as a material for a dielectric region in an electronic device. As the thickness of a SiO2 layer decreases, the number of atomic layers or monolayers of the material decreases. At a certain thickness, the number of monolayers will be sufficiently small that the SiO2 layer will not have a complete arrangement of atoms as in a larger or bulk layer. As a result of incomplete formation relative to a bulk structure, a thin SiO2 layer of only one or two monolayers may not form a full band gap. The lack of a full band gap in a SiO2 dielectric may cause an effective short between an underlying electrode and an overlying electrode. This undesirable property sets a limit on the physical thickness to which a SiO2 layer can be scaled. The minimum thickness due to this monolayer effect is thought to be about 7-8 Å. Therefore, for future devices to have a teq less than about 10 Å, other dielectrics than SiO2 may be considered for use as a dielectric region in such future devices.
In many cases, for a typical dielectric layer, the capacitance is determined as for a parallel plate capacitance: C=κ∈0A/t, where κ is the dielectric constant, ∈0 is the permittivity of free space, A is the area of the capacitor, and t is the thickness of the dielectric. The thickness, t, of a material is related to its teq for a given capacitance, with SiO2 having a dielectric constant κox=3.9, as
t=(κ/κox)teq=(κ/3.9)teq.
Thus, materials with a dielectric constant greater than that of SiO2, 3.9, will have a physical thickness that can be considerably larger than a desired teq, while providing the desired equivalent oxide thickness. For example, an alternative dielectric material with a dielectric constant of 10 could have a thickness of about 25.6 Å to provide a teq of 10 Å, not including any depletion/inversion layer effects. Thus, a reduced equivalent oxide thickness for transistors can be realized by using dielectric materials with higher dielectric constants than SiO2.
The reduced equivalent oxide thickness required for lower device operating voltages and smaller device dimensions may be realized by a significant number of materials, but additional fabricating requirements make determining a suitable replacement for SiO2 difficult. For example, silicon-based devices may employ a dielectric material grown on a silicon substrate or a silicon layer, which places significant constraints on the substitute dielectric material. During the formation of the dielectric on the silicon layer, there exists the possibility that a small layer of SiO2 could be formed in addition to the desired dielectric. The result would effectively be a dielectric layer consisting of two sublayers in parallel with each other and the silicon layer on which the dielectric is formed. In such a case, the resulting capacitance would be that of two dielectrics in series. As a result, the teq of the dielectric layer would be the sum of the SiO2 thickness and a multiplicative factor of the thickness, t, of the dielectric being formed, written as
teq=tSiO
Thus, if a SiO2 layer is formed in the process, the teq is again limited by a SiO2 layer. In the event that a barrier layer is formed between the silicon layer and the desired dielectric, and the barrier layer prevents the formation of a SiO2 layer, the teq would be limited by the layer with the lowest dielectric constant. However, whether a single dielectric layer with a high dielectric constant or a barrier layer with a dielectric constant greater than SiO2 is employed, the layer interfacing with the silicon layer should provide a high quality interface.
One of the advantages of using SiO2 as a dielectric layer in a device has been that the formation of the SiO2 layer results in an amorphous dielectric. Having an amorphous structure for a dielectric tends to reduce leakage current associated with grain boundaries in polycrystalline dielectrics that provide high leakage paths. Additionally, grain size and orientation changes throughout a polycrystalline dielectric can cause variations in the film's dielectric constant, along with uniformity and surface topography problems. Materials having a high dielectric constant relative to SiO2 may also have a crystalline form, at least in a bulk configuration. Good candidates for replacing SiO2 as a dielectric in a device are those that can be fabricated as a thin layer with an amorphous form and that have high dielectric constants.
Capacitor applications have used high-K dielectric materials, which are insulating materials having a dielectric constant greater than silicon dioxide. Such high-κ dielectric materials include silicon oxynitride (SiON, κ˜6), alumina (Al2O3, κ˜9), and oxide/nitride composites (SiO2/Si3N4, κ˜6). Other possible candidates include metal oxides (κ˜8-80), nitrides (κ˜7-30), oxynitrides (κ˜6-25), silicates (κ˜6-20), carbides (κ˜6-15), and complex titanates (κ˜>100). Factors for selecting appropriate materials include physical, chemical and thermal stability as well as etch-ability and stoichiometric reproducibility. In field effect transistor (FET) applications, there are other factors to consider while addressing device scalability. The selected dielectric should provide stable amorphous and adherent films in the thickness range of 1 nm to 100 nm at temperatures ranging from room temperature to 1000° C. A relatively defect-free composition that is uniform and reproducible with a fixed charge density and trap density of less than 1011 cm−2 in films of such composition is a factor. Another factor includes dielectric materials that provide a stable non-reactive interface with a silicon substrate such that the interface has an interface state density much less than 1011 cm−2. Such interface state densities may occur when silicon bonds at the interface are saturated with high strength covalent bonds with molecular elements of the dielectric material. Yet another factor deals with current transport through the dielectric that should be controlled by tunneling, which is independent of temperature, rather than by trap-assisted thermally dependent transport. The conductivity of the dielectric should be equal to or lower than SiO2 films when voltage is stressed to a field strength of 5×106 V/cm. To address current transport requirements, a dielectric material having a bandgap greater than 5 eV and having an electron and hole barrier height greater than 2 eV at a silicon interface may be considered. An additional factor to consider is using dielectric materials with a destructive breakdown strength greater than 6×106 V/cm. Other factors for selecting a dielectric material for use in a variety of electronic devices, such as for the dielectric in FETs, relates to processing characteristics. Such processing characteristics include compatibility with gate material, selective etch-ability, chemical inertness to contaminants, dopant and post processing environments (temperature, pressure, ambients), and intrinsic properties associated with annealing of defects/damages caused by post-processing such as ion-implantation, plasma-radiation, and gate/back-end processing.
In various embodiments, mixed metal oxynitrides are constructed as dielectric films in a variety of electronic devices and systems. Most oxynitrides are thermally stable and can integrate into semiconductor device processing. With nitrogen concentration in an oxynitride film at 30% or higher, such oxynitrides are considered chemically inert. With processing conditions controlled to provide very low partial pressures of hydrogen and ON ions, oxynitride films with a wide range of nitrogen to oxygen ratio can be deposited over a silicon substrate with very low fixed charge and interface states density. On the other hand, charge trapping and transport characteristics are dependent on the relative ratio of nitrogen to oxygen content in the constructed film. Films with nitrogen concentration twice that of oxygen (for example, approximately 40 atomic percent nitrogen, approximately 20 atomic percent oxygen, and approximately 40 atomic percent metal or silicon) have a lower bandgap, higher trap density, and transport characteristics dominated by Frenkel-Poole conduction. Such materials may not be well-suited for gate dielectric applications. However, such films also exhibit higher κ values. With increasing oxygen concentration in oxynitride films, the bandgap is raised, current leakage is reduced, and the low frequency κ value is also somewhat reduced. In addition with increasing oxygen concentration, the trap density is reduced, the trap energy depth is increased, and the carrier transport ceases to be trap-assisted, exhibits tunneling conduction, with a weakened temperature dependence. In various embodiments, a dielectric layer includes an oxynitride film having approximately 30 atomic % oxygen and approximately 30-35 atomic % nitrogen. With high enough nitrogen content, oxygen-vacancy induced defects in films may be negligible when compared with metal oxides.
Silicon oxynitride (SiON) may be used as a gate dielectric and gate insulator for a non-volatile FET device. Silicon oxynitride at a composition range of Si2ON2 exhibits a dielectric constant of 6.5 and a bandgap of approximately 6.5 eV compared to a stoichiometric nitride of K=7.5 and a bandgap of 5.1 eV. Aluminum oxynitride (AlON) is expected to have a bandgap greater than 5 eV with a κ value similar to SiON. Compared to SiON, metal oxynitrides such as ZrON, HfON, LaON, and TaON and other single metal oxynitrides are expected to have a lower bandgap. In various embodiments, bimetal (or metal/silicon) oxynitrides based on Si, Al, Hf, La, and Ta are used as dielectric films in a variety of electronic devices and systems. These bimetal oxynitrides may provide a bandgap range from 5 eV to greater than 7 eV. Estimates for bandgaps include a bandgap of Si—Al—ON of greater than 7 eV, a bandgap of Si—Hf—ON of about 6.9 eV, a bandgap of Al—Hf—ON of about 6.8 eV, a bandgap of Si—Ta—ON of about 6 eV, a bandgap of Al—Ta—ON of about 6 eV. Bimetal oxynitrides Hf—Ta—ON, Hf—La—ON, Al—La—ON, Ta—La—ON, and Si—La—ON are estimated to exhibit significantly lower bandgaps. The κ value for Si—Al—ON is estimated at approximately 7 to 8, while the κ values for the other oxynitrides of this group are estimated to be in the range from about 15 to 25. Refractory metals such as tungsten, molybdenum, tantalum, niobium, chromium, vanadium, and rhenium are metals with a melting point significantly higher than non-refractory metals. Transition metals are typically considered any element with an incomplete d subshell and include generally those elements between the group 2 elements and group 13 elements of the periodic table. Examples of transition metals include hafnium, yttrium, zirconium, platinum as well as the refractory metals. In various embodiments a refractory metal and a non-refractory metal are used to form a dielectric. In some embodiments a refractory metal and a non-refractory metal are used in combination with oxygen and nitrogen to form a dielectric. In various embodiments combinations of a refractory oxide, a refractory nitride and a refractory oxynitride form a dielectric. In some embodiments the refractory-based dielectric is amorphous. In some embodiments, the refractory-based dielectric is homogenous.
In some embodiments a refractory metal and a non-refractory transition metal form a dielectric. Various embodiments may include using a refractory metal and a non-refractory transition metal to form a plurality of layers. In some embodiments, stacked dielectric layers are formed using a refractory metal and a non-refractory transition metal in combination with oxygen and/or nitrogen. Various embodiments include forming a stacked dielectric structure using refractory metal oxides, refractory metal nitrides, refractory metal oxynitrides in combination with non-refractory metal oxides, non-refractory metal nitrides, and non-refractory metal oxynitrides. In some embodiments forming a stacked dielectric structure using refractory metal oxides, refractory metal nitrides, refractory metal oxynitrides in combination with non-refractory transition metal oxides, non-refractory transition metal nitrides, and non-refractory transition metal oxynitrides. In an embodiment, one or more of the refractory metal, non-refractory metal, oxygen and nitrogen concentration is graded substantially perpendicular to direction of deposition or to a surface normal. In an embodiment, one or more of the refractory metal, non-refractory metal, oxygen and nitrogen concentration is graded substantially parallel to direction of deposition or substantially parallel to the surface of the substrate.
In an embodiment, a film of hafnium tantalum oxynitride is used as a dielectric layer for application in a variety of electronic devices, replacing the use of silicon oxide to provide a higher dielectric constant. According to various embodiments, a high-k gate dielectric includes one or more of the following: TaN, HfN, HfON, TaON, HfTaON, TaN/HfN, TaN/HfON, TaON/HfN, TaON/HfON, TaN/HfO2, Ta2O5/HfN, TaON/HfO2, Ta2O5/HfON, and Ta2O5/HfO2. In various embodiments, a dielectric layer is constructed containing hafnium tantalum oxynitride formed using atomic layer deposition with a metal electrode formed in contact with the dielectric layer. The metal electrode may also be formed by atomic layer deposition. The metal electrode may be formed by substituting a desired metal material for a previously disposed substitutable material. The metal electrode may be formed as a self aligned metal electrode on and contacting the dielectric layer. The metal electrode may be formed on the dielectric layer using a previously disposed sacrificial carbon layer on the dielectric layer and sacrificial carbon sidewall spacers adjacent to the sacrificial carbon layer.
The term hafnium tantalum oxynitride is used herein with respect to a composition that essentially consists of hafnium, tantalum, oxygen, and nitrogen in a form that may be stoichiometric, non-stoichiometric, or a combination of stoichiometric and non-stoichiometric. A hafnium tantalum oxynitride film may also be referred to as a hafnium tantalum oxygen nitrogen film. Other nomenclature for a composition that essentially consists of hafnium, tantalum, oxygen, and nitrogen may be known to those skilled in the art. In an embodiment, hafnium tantalum oxynitride may be formed substantially as a stoichiometric hafnium tantalum oxynitride film. In an embodiment, hafnium tantalum oxynitride may be formed substantially as a non-stoichiometric hafnium tantalum oxynitride film. In an embodiment, hafnium tantalum oxynitride may be formed substantially as a combination film of non-stoichiometric hafnium tantalum oxynitride and stoichiometric hafnium tantalum oxynitride. Herein, a hafnium tantalum oxynitride composition may be expressed as HfTaON, HfxTayOzNw, or other equivalent form. The expression HfTaON or its equivalent forms may be used to include HfTaON in a form that is stoichiometric, non-stoichiometric, or a combination of stoichiometric and non-stoichiometric hafnium tantalum oxynitride. The expression HfTaON or its equivalent forms may be used to include HfTaON in a form that is homogeneous and amorphous hafnium tantalum oxynitride. The expressions TaO, TayOz, or its equivalent forms may be used to include tantalum oxide in a form that is stoichiometric, non-stoichiometric, or a combination of stoichiometric and non-stoichiometric. With respect to forms that are stoichiometric, non-stoichiometric, or a combination of stoichiometric and non-stoichiometric, expressions such as TaO, TaN, TaON, TayOz, HfOz, HfNw, HfON, HfxOzNw, etc. may be used. In some embodiments, x, y, w, and z are atomic mole fractions. In various embodiments, x, y, w, and z are atomic percentages. In some embodiments, x, y, w and z represent a particular chemical composition as is known in the art. Forms that are stoichiometric, non-stoichiometric, or a combination of stoichiometric and non-stoichiometric, may include expressions such as TaN, HfN, HfON, TaON, HfTaON, TaN/HfN, TaN/HfON, TaON/HfN, TaON/HfON, TaN/HfO2, Ta2O5/HfN, TaON/HfO2, Ta2O5/HfON, and Ta2O5/HfO2. In various embodiments, a hafnium tantalum oxynitride film is doped with elements or compounds other than hafnium, tantalum, oxygen, and nitrogen.
In an embodiment, a hafnium tantalum oxynitride dielectric film may be formed using atomic layer deposition (ALD). Forming such structures using atomic layer deposition may allow control of transitions between material layers. As a result of such control, atomic layer deposited hafnium tantalum oxynitride dielectric films can have an engineered transition with a surface on which it is formed.
ALD, also known as atomic layer epitaxy (ALE), is a modification of chemical vapor deposition (CVD) and is also called “alternatively pulsed-CVD.” In ALD, gaseous precursors are introduced one at a time to the substrate surface mounted within a reaction chamber (or reactor). This introduction of the gaseous precursors takes the form of pulses of each gaseous precursor. In a pulse of a precursor gas, the precursor gas is made to flow into a specific area or region for a short period of time. Between the pulses, the reaction chamber may be purged with a gas, where the purging gas may be an inert gas. Between the pulses, the reaction chamber may be evacuated. Between the pulses, the reaction chamber may be purged with a gas and evacuated.
In a chemisorption-saturated ALD (CS-ALD) process, during the first pulsing phase, reaction with the substrate occurs with the precursor saturatively chemisorbed at the substrate surface. Subsequent pulsing with a purging gas removes precursor excess from the reaction chamber.
The second pulsing phase introduces another precursor on the substrate where the growth reaction of the desired film takes place. Subsequent to the film growth reaction, reaction byproducts and precursor excess are purged from the reaction chamber. With favorable precursor chemistry where the precursors absorb and react with each other aggressively on the substrate, one ALD cycle can be performed in less than one second in properly designed flow type reaction chambers. Typically, precursor pulse times range from about 0.5 sec to about 2 to 3 seconds. Pulse times for purging gases may be significantly longer, for example, pulse times of about 5 to about 30 seconds.
In ALD, the saturation of all the reaction and purging phases makes the growth self-limiting. This self-limiting growth results in large area uniformity and conformality, which has important applications for such cases as planar substrates, deep trenches, and in the processing of porous silicon and high surface area silica and alumina powders. Atomic layer deposition provides control of film thickness in a straightforward manner by controlling the number of growth cycles.
The precursors used in an ALD process may be gaseous, liquid or solid. However, liquid or solid precursors should be volatile. The vapor pressure should be high enough for effective mass transportation. Also, solid and some liquid precursors may be heated inside the atomic layer deposition system and introduced through heated tubes to the substrates. The necessary vapor pressure should be reached at a temperature below the substrate temperature to avoid the condensation of the precursors on the substrate. Due to the self-limiting growth mechanisms of ALD, relatively low vapor pressure solid precursors can be used, though evaporation rates may vary somewhat during the process because of changes in their surface area.
There are several other characteristics for precursors used in ALD. The precursors should be thermally stable at the substrate temperature, because their decomposition may destroy the surface control and accordingly the advantages of the ALD method that relies on the reaction of the precursor at the substrate surface. A slight decomposition, if slow compared to the ALD growth, may be tolerated.
The precursors should chemisorb on or react with the surface, though the interaction between the precursor and the surface as well as the mechanism for the adsorption is different for different precursors. The molecules at the substrate surface should react aggressively with the second precursor to form the desired solid film. Additionally, precursors should not react with the film to cause etching, and precursors should not dissolve in the film. Using highly reactive precursors in ALD contrasts with the selection of precursors for conventional CVD.
The by-products in the reaction should be gaseous in order to allow their easy removal from the reaction chamber. Further, the by-products should not react or adsorb on the surface.
In a reaction sequence ALD (RS-ALD) process, the self-limiting process sequence involves sequential surface chemical reactions. RS-ALD relies on chemistry between a reactive surface and a reactive molecular precursor. In an RS-ALD process, molecular precursors are pulsed into the ALD reaction chamber separately. A metal precursor reaction at the substrate may be followed by an inert gas pulse to remove excess precursor and by-products from the reaction chamber prior to pulsing the next precursor of the fabrication sequence.
Using RS-ALD, films can be layered in equal metered sequences that may all be substantially identical in chemical kinetics, deposition per cycle, composition, and thickness. RS-ALD sequences generally deposit less than a full layer per cycle. Typically, a deposition or growth rate of about 0.25 to about 2.00 Å per RS-ALD cycle may be realized.
Processing by RS-ALD provides continuity at an interface avoiding poorly defined nucleating regions that are typical for chemical vapor deposition (<20 Å) and physical vapor deposition (<50 Å), conformality over a variety of substrate topologies due to its layer-by-layer deposition technique, use of low temperature and mildly oxidizing processes, lack of dependence on the reaction chamber, growth thickness dependent solely on the number of cycles performed, and ability to engineer multilayer laminate films with a resolution of one to two monolayers. RS-ALD processes allow for deposition control on the order of monolayers and the ability to deposit monolayers of amorphous films.
Herein, a sequence refers to ALD material formation based on an ALD reaction of a precursor with its reactant precursor. For example, forming hafnium nitride from a HfCl4 precursor and NH3, as its reactant precursor, includes a hafnium/nitrogen sequence. In various ALD processes that form a nitride or a composition that contains nitrogen, a reactant precursor that contains nitrogen is used to supply nitrogen. Herein, a precursor that contains nitrogen and that supplies nitrogen to be incorporated in the ALD composition formed, which may be used in an ALD process with precursors supplying the other elements in the ALD composition, is referred to as a nitrogen reactant precursor. In the above example, NH3 is a nitrogen reactant precursor. Similarly, an ALD sequence for a metal oxide may be referenced with respect to the metal and oxygen. For example, an ALD sequence for hafnium oxide may also be referred to as a hafnium/oxygen sequence. In various ALD processes that form an oxide or a composition that contains oxygen, a reactant precursor that contains oxygen is used to supply the oxygen. Herein, a precursor that contains oxygen and that supplies oxygen to be incorporated in the ALD composition formed, which may be used in an ALD process with precursors supplying the other elements in the ALD composition, is referred to as an oxygen reactant precursor. With an ALD process using HfCl4 and water vapor to form hafnium oxide, water vapor is an oxygen reactant precursor. An ALD cycle may include pulsing a precursor, pulsing a purging gas for the precursor, pulsing a reactant precursor, and pulsing the reactant precursor's purging gas. An ALD cycle may include pulsing a precursor, evacuating the reactant chamber, pulsing a reactant precursor, and evacuating the reactant chamber. An ALD cycle may include pulsing a precursor, pulsing a purging gas for the precursor and evacuating the reactant chamber, pulsing a reactant precursor, and pulsing the reactant precursor's purging gas and evacuating the reactant chamber.
For example, forming tantalum oxide from a TaCl5 precursor and H2O, as its reactant precursor, forms an embodiment of a tantalum/oxygen sequence, which can also be referred to as a tantalum sequence. Additional information regarding tantalum oxides formed by ALD can be found in U.S. patent application Ser. No. 11/029,757, referenced previously.
In forming a layer of a metal species, an ALD sequence may deal with pulsing a reactant precursor to the substrate surface on which a metal-containing species has been absorbed such that the reactant precursor reacts with the metal-containing species resulting in the deposited metal and a gaseous by-product that can be removed during the subsequent purging/evacuating process. Alternatively, in forming a layer of a metal species, an ALD sequence may include reacting a precursor containing the metal species with a substrate surface. A cycle for such a metal forming sequence may include pulsing a purging gas after pulsing the precursor containing the metal species to deposit the metal. Additionally, deposition of a semiconductor material may be realized in a manner similar to forming a layer of a metal, given the appropriate precursors for the semiconductor material.
In an ALD formation of a composition having more than two elements, a cycle may include a number of sequences to provide the elements of the composition. For example, a cycle for an ALD formation of an ABOx composition, where “A” is a first element, e.g., a metal, and “B” is a second element, e.g., a metal, may include sequentially [pulsing a first precursor/a purging gas for the first precursor/a first reactant precursor/the first reactant precursor's purging gas] followed sequentially by [a second precursor/a purging gas for the second precursor/a second reactant precursor/the second reactant precursor's purging gas], which may be viewed as a cycle having two sequences. In an embodiment, a cycle may include a number of sequences for element A and a different number of sequences for element B. There may be cases in which ALD formation of an ABOx composition uses one precursor that contains the elements A and B, such that pulsing the AB containing precursor followed by its reactant precursor onto a substrate may include a reaction that forms ABOx on the substrate to provide an AB/oxygen sequence. A cycle of an AB/oxygen sequence may include pulsing a precursor containing A and B, pulsing a purging gas for the precursor, pulsing an oxygen reactant precursor to the A/B precursor, and pulsing a purging gas for the reactant precursor. A cycle may be repeated a number of times to provide a desired thickness of the composition. In an embodiment, a cycle for an ALD formation of the quaternary composition, hafnium tantalum oxygen nitrogen, may include sequentially [pulsing a first precursor/a purging gas for the first precursor/a first reactant precursor/the first reactant precursor's purging gas] followed sequentially by [a second precursor/a purging gas for the second precursor/a second reactant precursor/the second reactant precursor's purging gas/a third precursor/a purging gas for the third precursor/a third reactant precursor/the third reactant precursor's purging gas], which may be viewed as a cycle having three sequences. In an embodiment, a layer substantially of a hafnium tantalum oxynitride composition is formed on a substrate mounted in a reaction chamber using ALD in repetitive tantalum/oxygen and hafnium/nitrogen sequences using precursor gases individually pulsed into the reaction chamber. In an embodiment, a layer substantially of a hafnium tantalum oxynitride composition is formed on a substrate mounted in a reaction chamber using ALD in repetitive tantalum/nitrogen and hafnium/oxygen sequences using precursor gases individually pulsed into the reaction chamber. In an embodiment, a substantially hafnium tantalum oxynitride composition is formed by ALD having approximately 30% nitrogen and 30% oxygen concentrations in the resultant HfTaON dielectric film. In some embodiments, a substantially pure hafnium tantalum oxynitride composition is formed by ALD having approximately 20-40% nitrogen and 20-40% oxygen concentrations in the resultant HfTaON dielectric film.
Also included in the ALD system may be purging gas sources 163, 164, each of which is coupled to gas controllers 166, 167, respectively. Furthermore, additional purging gas sources may be constructed in ALD system 100, one purging gas source for each precursor gas. For a process that uses the same purging gas for multiple precursor gases, less purging gas sources are required for ALD system 100. Gas sources 150-155 and purging gas sources 163-164 are coupled by their associated gas controllers to a common gas line or conduit 170, which is coupled to the gas-distribution fixture 140 inside reaction chamber 120. Gas conduit 170 is also coupled to vacuum pump, or exhaust pump, 181 by gas controller 186 to remove excess precursor gases, purging gases, and by-product gases at the end of a purging sequence from gas conduit 170.
The vacuum pump, or exhaust pump, 182 may be coupled to chamber 120 using gas controller 187 to remove excess precursor gases, purging gases, and by-product gases at the end of a purging sequence from reaction chamber 120. For convenience, and to avoid obscuring various elements in the figure, control displays, mounting apparatus, temperature sensing devices, substrate maneuvering apparatus, and necessary electrical connections known to those skilled in the art are not shown in
In an embodiment, a hafnium tantalum oxynitride layer is structured as one or more monolayers with a thickness ranging from a monolayer to thousands of angstroms or more. The film may be processed using atomic layer deposition. Embodiments of an atomic layer deposited hafnium tantalum oxynitride layer have a larger dielectric constant than silicon dioxide. Such dielectric layers provide a significantly thinner equivalent oxide thickness compared with a silicon oxide layer having the same physical thickness. Alternatively, such dielectric layers provide a significantly thicker physical thickness than a silicon oxide layer having the same equivalent oxide thickness. This increased physical thickness aids in reducing leakage current.
Prior to forming the hafnium tantalum oxynitride film using ALD, the surface on which the hafnium tantalum oxynitride film is to be deposited may undergo a preparation stage. The surface may be the surface of a substrate for an integrated circuit. In an embodiment, the substrate used for forming a transistor may include a silicon or silicon containing material. In other embodiments, silicon germanium, germanium, gallium arsenide, silicon-on-sapphire substrates, or other suitable substrates may be used. A preparation process may include cleaning the substrate and forming layers and regions of the substrate, such as drains and sources, prior to forming a gate dielectric in the formation of a metal oxide semiconductor (MOS) transistor. Alternatively, active regions may be formed after forming the dielectric layer, depending on the over-all fabrication process implemented. In an embodiment, the substrate is cleaned to provide an initial substrate depleted of its native oxide. In an embodiment, the initial substrate is cleaned also to provide a hydrogen-terminated surface. In an embodiment, a silicon substrate undergoes a final hydrofluoric (HF) rinse prior to ALD processing to provide the silicon substrate with a hydrogen-terminated surface without a native silicon oxide layer.
Cleaning immediately preceding atomic layer deposition aids in reducing an occurrence of silicon oxide as an interface between a silicon-based substrate and a hafnium tantalum oxynitride dielectric formed using the atomic layer deposition process. The material composition of an interface layer and its properties are typically dependent on process conditions and the condition of the substrate before forming the dielectric layer. Though the existence of an interface layer may effectively reduce the dielectric constant associated with the dielectric layer and its substrate interface layer, a SiO2 interface layer or other composition interface layer may improve the interface density, fixed charge density, and channel mobility of a device having this interface layer.
The sequencing of the formation of the regions of an electronic device, such as a transistor, may follow sequencing that is generally performed in the fabrication of such devices as is well known to those skilled in the art. Included in the processing prior to forming a dielectric may be the masking of substrate regions to be protected during the dielectric formation, as is typically performed in semiconductor fabrication. In an embodiment, an unmasked region includes a body region of a transistor; however, one skilled in the art will recognize that other semiconductor device structures may utilize this process.
In various embodiments, between each pulsing of a precursor used in an atomic layer deposition process, a purging gas is pulsed into the ALD reaction chamber. Between each pulsing of a precursor, the ALD reactor chamber may be evacuated using vacuum techniques as is known by those skilled in the art. Between each pulsing of a precursor, a purging gas may be pulsed into the ALD reaction chamber and the ALD reactor chamber may be evacuated.
In an embodiment, an ALD cycle for forming HfTaON includes sequencing component-containing precursors in the order of tantalum, oxygen, hafnium, and nitrogen with appropriate purging between the different component-containing precursors. Full coverage or partial coverage of a monolayer on a substrate surface may be attained for pulsing of a metal-containing precursor. In an embodiment, an ALD cycle for forming HfTaON includes sequencing the component-containing precursors in various permutations. In an embodiment, an ALD cycle to form hafnium tantalum oxynitride includes a number, x, of tantalum/oxygen sequences and a number, y, of hafnium/nitrogen sequences. In an embodiment, an ALD cycle to form hafnium tantalum oxynitride includes a number, x, of tantalum/nitrogen sequences and a number, y, of hafnium/oxygen sequences. In an embodiment, the number of sequences x and y is determined by selecting the relative amounts of hafnium, tantalum, oxygen, and nitrogen. In an embodiment, the number of sequences x and y may be selected to form hafnium tantalum oxynitride that is a nitrogen-rich relative to the amount of oxygen in the dielectric. In an embodiment, the number of sequences x and y may be selected to form hafnium tantalum oxynitride that is oxygen-rich relative to the amount of nitrogen in the dielectric. The hafnium tantalum oxynitride may be formed as a tantalum-rich dielectric relative to the amount of hafnium in the dielectric. The hafnium tantalum oxynitride may be formed as a hafnium-rich dielectric relative to the amount of tantalum in the dielectric. The pulsing of the individual component-containing precursors may be performed independently in a non-overlapping manner using the individual gas sources 150-155 and flow controllers 156-161 of ALD system 100 of
Each precursor may be pulsed into the reaction chamber 120 for a predetermined period, where the predetermined period can be set separately for each precursor. Additionally, for various ALD formations, each precursor may be pulsed into the reaction chamber under separate environmental conditions. The substrate may be maintained at a selected temperature and the reaction chamber 120 maintained at a selected pressure independently for pulsing each precursor. Appropriate temperatures and pressures may be maintained, whether the precursor is a single precursor or a mixture of precursors.
A number of precursors containing tantalum may be used to provide the tantalum to a substrate for an integrated circuit. In an embodiment, a precursor containing a tantalum includes, but is not limited to TaCl5, (Ta(N-t-C5H11)[N(CH3)2]3, and tantalum ethoxide Ta(OC2H5)5. In an embodiment, H2 is pulsed along with a precursor to reduce carbon contamination in the fabricated film. In an embodiment, a tantalum-containing precursor is pulsed onto a substrate in an ALD reaction chamber. In various embodiments, after pulsing the tantalum-containing precursor and purging the reaction chamber of excess precursor and by-products from pulsing the precursor, a reactant precursor is pulsed into the reaction chamber. The reactant precursor may be an oxygen reactant precursor that may include, but is not limited to, one or more of water, atomic oxygen, molecular oxygen, ozone, hydrogen peroxide, a water-hydrogen peroxide mixture, alcohol, or nitrous oxide. In addition, the pulsing of the tantalum precursor may use a pulsing period that provides uniform coverage of a monolayer on the surface or may use a pulsing period that provides partial coverage of a monolayer on the surface during a tantalum sequence.
A number of precursors containing hafnium may be used to provide the hafnium to a substrate for an integrated circuit. In an embodiment, a precursor containing hafnium may include anhydrous hafnium nitride, Hf(NO3)4. In an embodiment using a Hf(NO3)4 precursor on a hydrogen-terminated silicon, the substrate temperature is maintained at a temperature ranging from about 160° C. to about 180° C. In an embodiment, a hafnium precursor includes HfCl4. In an embodiment using a HfCl4 precursor, the substrate temperature is maintained at a temperature ranging from about 180° C. to about 600° C. In an embodiment using a HfCl4 precursor, the substrate temperature is maintained at a temperature ranging from about 300° C. to about 940° C. In an embodiment, a hafnium precursor is HfI4. In an embodiment using a HfI4 precursor, the substrate temperature is maintained at a temperature of about 300° C. Hafnium oxide may be grown by ALD using a Hf[N(CH3)(C2H5)]4, which may be known as a homoleptic tetrakis(dialkylamino) hafnium(IV) compound, and water as an oxygen reactant. Other types of tetrakis(dialkylamino) hafnium compounds may also be used, such as hafnium tetrakis dimethylamine, Hf[N(CH3)2]4, or hafnium tetrakis diethylamine, Hf[N(C2H5)2]4, as a hafnium-containing precursor. In various embodiments, use of the individual hafnium-containing precursors is not limited to the temperature ranges of the above example embodiments. In addition, the pulsing of the hafnium precursor may use a pulsing period that provides uniform coverage of a monolayer on the surface or may use a pulsing period that provides partial coverage of a monolayer on the surface during a hafnium sequence.
In various embodiments, nitrogen is used as a purging gas and a carrier gas for one or more of the sequences used in the ALD formation of hafnium tantalum oxynitride. Alternatively, hydrogen, argon gas, or other inert gases may be used as the purging gas. Excess precursor gas and reaction by-products may be removed by the purge gas. Excess precursor gas and reaction by-products may be removed by evacuation of the reaction chamber using various vacuum techniques. Excess precursor gas and reaction by-products may be removed by the purge gas and by evacuation of the reaction chamber.
In an embodiment, after repeating a selected number of ALD cycles, a determination is made as to whether the number of cycles equals a predetermined number to form the desired hafnium tantalum oxynitride layer. If the total number of cycles to form the desired thickness has not been completed, a number of cycles is repeated. In an embodiment, the thickness of a hafnium tantalum oxynitride layer formed by atomic layer deposition is determined by a fixed growth rate for the pulsing periods and precursors used, set at a value such as N nm/cycle, and the number of cycles conducted. In an embodiment, depending on the precursors used for ALD formation of a HfTaON film, the process is conducted in an ALD window, which is a range of temperatures in which the growth rate is substantially constant. In an embodiment, if such an ALD window is not available, the ALD process is conducted at the same set of temperatures for each ALD sequence in the process. For a desired hafnium tantalum oxynitride layer thickness, t, in an application, the ALD process is repeated for t/N total cycles. Once the t/N cycles have completed, further ALD processing for the hafnium tantalum oxynitride layer may be terminated. In an embodiment, a hafnium tantalum oxynitride layer processed at relatively low temperatures associated with atomic layer deposition provides an amorphous layer.
In an embodiment, a HfTaON film is grown to a desired thickness by repetition of a process including atomic layer deposition of layers of Ta2O5 and HfN and/or layers of HfO2 and TaN followed by annealing. In an embodiment, a base thickness is formed according to various embodiments such that forming a predetermined thickness of a HfTaON film may be conducted by forming a number of layers having the base thickness. As can be understood by one skilled in the art, determining the base thickness depends on the application and can be determined during initial processing without undue experimentation. Relative amounts of hafnium, tantalum, oxygen, and nitrogen in a HfTaON film may be controlled by regulating the relative thicknesses of the individual layers of oxides and nitrides formed. In addition, relative amounts of hafnium, tantalum, oxygen, and nitrogen in a HfTaON film may be controlled by forming a layer of HfTaON as multiple layers of different base thickness and by regulating the relative thicknesses of the individual layers of oxides and nitrides formed in each base layer prior to annealing. As can be understood by those skilled in the art, particular effective growth rates for the selected hafnium tantalum oxynitride film can be determined during normal initial testing of the ALD system used in processing a hafnium tantalum oxynitride dielectric for a given application without undue experimentation.
In an embodiment, ALD Ta2O5 is formed using a number of precursors containing tantalum to provide the tantalum to a substrate for an integrated circuit. Such tantalum-containing precursors include, but are not limited to, a tantalum halide precursor, such as TaCl5, Ta(N-t-C5H11)[N(CH3)2]3, or tantalum ethoxide Ta(OC2H5)5. After pulsing the tantalum-containing precursor and purging the reaction chamber of excess precursor and by-products from pulsing the precursor, an oxygen reactant precursor may be pulsed into the reaction chamber. The oxygen reactant precursor may include, but is not limited to, one or more of water, atomic oxygen, molecular oxygen, ozone, hydrogen peroxide, a water-hydrogen peroxide mixture, alcohol, or nitrous oxide. After pulsing the oxygen-containing precursor, the reaction chamber may be purged of excess precursor and by-products. In addition, the pulsing of the precursors may use pulsing periods that provide uniform coverage of a monolayer on the surface or may use pulsing periods that provide partial coverage of a monolayer on the surface during a tantalum/oxygen ALD cycle.
In an embodiment, ALD HfO2 is formed using a number of precursors containing hafnium to provide the hafnium to a substrate for an integrated circuit. Such hafnium-containing precursors include, but are not limited to, a hafnium halide, such as HfCl4 and HfI4, Hf(NO3)4, Hf[N(CH3)(C2H5)]4, Hf[N(CH3)2]4, and Hf[N(C2H5)2]4. After pulsing the hafnium-containing precursor and purging the reaction chamber of excess precursor and by-products from pulsing the precursor, an oxygen reactant precursor may be pulsed into the reaction chamber. The oxygen reactant precursor may include, but is not limited to, one or more of water, atomic oxygen, molecular oxygen, ozone, hydrogen peroxide, a water-hydrogen peroxide mixture, alcohol, or nitrous oxide. In addition, the pulsing of the precursors may use pulsing periods that provide uniform coverage of a monolayer on the surface or may use pulsing periods that provide partial coverage of a monolayer on the surface during an ALD cycle forming HfO2.
In various embodiments, nitrogen is used as a purging gas and a carrier gas for one or more of the sequences. Alternatively, hydrogen, argon gas, or other inert gases may be used as the purging gas. Excess precursor gas and reaction by-products may be removed by the purge gas. Excess precursor gas and reaction by-products may be removed by evacuation of the reaction chamber using various vacuum techniques. Excess precursor gas and reaction by-products may be removed by the purge gas and by evacuation of the reaction chamber.
In an embodiment, ALD HfN is formed using a number of precursors containing hafnium to provide the hafnium to a substrate for an integrated circuit. To form hafnium nitride by ALD, a hafnium-containing precursor is pulsed onto a substrate in an ALD reaction chamber. A number of precursors containing hafnium may be used to provide the hafnium to a substrate for an integrated circuit. The hafnium-containing precursor may be a hafnium halide precursor, such as HfCl4 or HfI4. In addition to halide precursors, the hafnium nitride may be grown by ALD using Hf[N(CH3)(C2H5)]4. In an embodiment, the substrate is held at a temperature ranging from about 150° C. to about 300° C. Other types of tetrakis(dialkylamino) metal compounds may also be used, such as hafnium tetrakis dimethylamine, Hf[N(CH3)2]4, or hafnium tetrakis diethylamine, Hf[N(C2H5)2]4, as a hafnium-containing precursor. In various embodiments, after pulsing the hafnium-containing precursor and purging the reaction chamber of excess precursor and by-products from pulsing the precursor, a reactant precursor is pulsed into the reaction chamber. The reactant precursor may be a nitrogen reactant precursor including, but not limited to, ammonia (NH3). Other nitrogen reactant precursors that may be used include nitrogen-containing compositions that do not include oxygen. In various embodiments, use of the individual hafnium-containing precursors is not limited to the temperature ranges of the above embodiments. Further, forming hafnium nitride by atomic layer deposition is not limited to the abovementioned precursors. In addition, the pulsing of the hafnium precursor may use a pulsing period that provides uniform coverage of a monolayer on the surface or may use a pulsing period that provides partial coverage of a monolayer on the surface during a hafnium sequence.
In an embodiment, ALD TaN is formed using a number of precursors containing tantalum to provide the tantalum to a substrate for an integrated circuit. To form tantalum nitride by atomic layer deposition, a tantalum-containing precursor is pulsed onto a substrate in an ALD reaction chamber. Precursors containing tantalum may be used to provide the tantalum to a substrate for an integrated circuit. The tantalum-containing precursor may be a tantalum halide precursor, such as TaF5, TaCl5, or Ta(N-t-C5H11)[N(CH3)2]3. Additional information regarding metal nitride layers formed by ALD can be found in U.S. patent application Ser. No. 10/352,507, referenced previously. In an embodiment, H2 is pulsed along with the precursor to reduce carbon contamination in the deposited film. After pulsing the tantalum-containing precursor and purging the reaction chamber of excess precursor and by-products from pulsing the precursor, a reactant precursor may be pulsed into the reaction chamber. To form TaN, a nitrogen reactant precursor is pulsed. A number of precursors containing nitrogen may be used to provide nitrogen. Such nitrogen-containing precursors include, but are not limited to, nitrogen, ammonia (NH3), tert-butylamine (C4H11N), allylamine (C3H7N), 1,1-dimethylhydrazine ((CH3)2NNH2). In an embodiment, the substrate is maintained at a temperature ranging from about 400° C. to about 500° C. using tert-butylamine or allylamine as a nitrogen precursor. In an embodiment, NH3 is pulsed with the tert-butylamine and the allylamine. The addition of NH3 may enhance the deposition rate at lower temperatures. In various embodiments, use of the individual tantalum-containing precursors is not limited to the temperature ranges of the above example embodiments. Further, forming tantalum nitride by atomic layer deposition is not limited to the abovementioned precursors. In addition, the pulsing of the tantalum precursor may use a pulsing period that provides uniform coverage of a monolayer on the surface or may use a pulsing period that provides partial coverage of a monolayer on the surface during a tantalum/nitrogen sequence.
In various embodiments, nitrogen is used as a purging gas and a carrier gas for one or more of the sequences. Alternatively, hydrogen, argon gas, or other inert gases may be used as the purging gas. Excess precursor gas and reaction by-products may be removed by the purge gas. Excess precursor gas and reaction by-products may be removed by evacuation of the reaction chamber using various vacuum techniques. Excess precursor gas and reaction by-products may be removed by the purge gas and by evacuation of the reaction chamber.
In an embodiment, ALD TaON is formed using a number of precursors containing tantalum to provide the tantalum to a substrate for an integrated circuit. Such tantalum-containing precursors include, but are not limited to, a tantalum halide, such as TaF5, TaCl5, or Ta(N-t-C5H11)[N(CH3)2]3, and tantalum ethoxide Ta(OC2H5)5. After pulsing the tantalum-containing precursor and purging the reaction chamber of excess precursor and by-products from pulsing the precursor, a reactant precursor may be pulsed into the reaction chamber. A nitrogen reactant precursor may be pulsed. A number of precursors containing nitrogen may be used to provide nitrogen. Such nitrogen-containing precursors include, but are not limited to, nitrogen, ammonia (NH3), tert-butylamine (C4H11N), allylamine (C3H7N), and 1,1-dimethylhydrazine ((CH3)2NNH2). After pulsing the nitrogen-containing precursor and purging the reaction chamber of excess precursor and by-products from pulsing the precursor, an oxygen reactant precursor may be pulsed into the reaction chamber. The oxygen reactant precursor may include, but is not limited to, one or more of water, atomic oxygen, molecular oxygen, ozone, hydrogen peroxide, a water-hydrogen peroxide mixture, alcohol, or nitrous oxide. In various embodiments, the order of pulsing the precursors may vary. In various embodiments, forming tantalum oxynitride by atomic layer deposition is not limited to the abovementioned precursors. In addition, the pulsing of the precursors may use pulsing periods that provide uniform coverage of a monolayer on the surface or may use pulsing periods that provide partial coverage of a monolayer on the surface during an ALD cycle forming TaON.
In an embodiment, ALD HfON is formed using a number of precursors containing hafnium to provide the hafnium to a substrate for an integrated circuit. Such hafnium-containing precursors include, but are not limited to, a hafnium halide, such as HfCl4 or HfI4, Hf[N(CH3)(C2H5)]4, hafnium tetrakis dimethylamine, Hf[N(CH3)2]4, or hafnium tetrakis diethylamine, Hf[N(C2H5)2]4. In various embodiments, after pulsing the hafnium-containing precursor and purging the reaction chamber of excess precursor and by-products from pulsing the precursor, a nitrogen reactant precursor is pulsed into the reaction chamber. A number of precursors containing nitrogen may be used to provide nitrogen. In an embodiment, NH3 is used as the nitrogen-containing precursor. Other nitrogen reactant precursors that may be used include nitrogen-containing compositions that do not include oxygen. In an embodiment, the nitrogen-containing precursor may also include oxygen. After pulsing the nitrogen-containing precursor and purging the reaction chamber of excess precursor and by-products from pulsing the precursor, an oxygen reactant precursor may be pulsed into the reaction chamber. The oxygen reactant precursor may include, but is not limited to, one or more of water, atomic oxygen, molecular oxygen, ozone, hydrogen peroxide, a water-hydrogen peroxide mixture, alcohol, or nitrous oxide. In various embodiments, the order of pulsing the precursors varies. Further, forming hafnium oxynitride by atomic layer deposition is not limited to the abovementioned precursors. In addition, the pulsing of the precursors may use pulsing periods that provide uniform coverage of a monolayer on the surface or may use pulsing periods that provide partial coverage of a monolayer on the surface during an ALD cycle forming HfON.
In various embodiments, nitrogen is used as a purging gas and a carrier gas for one or more of the sequences. Alternatively, hydrogen, argon gas, or other inert gases may be used as the purging gas. Excess precursor gas and reaction by-products may be removed by the purge gas. Excess precursor gas and reaction by-products may be removed by evacuation of the reaction chamber using various vacuum techniques. Excess precursor gas and reaction by-products may be removed by the purge gas and by evacuation of the reaction chamber.
In various embodiments, either before or after forming a HfTaON film, other dielectric layers such as HfO, TaO, HfON, TaON, dielectric nitride layers, dielectric metal silicates, insulating metal oxides, or combinations thereof may be formed as part of a dielectric layer or dielectric stack. In some embodiments, these layers of dielectric material are provided in stoichiometric form, in non-stoichiometric form, or a combination of stoichiometric dielectric material and non-stoichiometric dielectric material. In some embodiments, these layers of dielectric material are provided in homogeneous form. In some embodiments, these layers of dielectric material are provided in amorphous form. In an embodiment, depending on the application, a dielectric stack containing a HfxTayOzNw film includes a silicon oxide layer. In an embodiment, the dielectric layer is formed as a nanolaminate. An embodiment of a nanolaminate includes a layer of a hafnium oxide and a HfxTayOzNw film, a layer of hafnium nitride and a HfxTayOzNw film, a layer of hafnium oxynitride and a HfxTayOzNw film, a layer of tantalum oxide and a HfxTayOzNw film, a layer of tantalum nitride and a HfxTayOzNw film, and a layer of tantalum oxynitride and a HfxTayOzNw film, layers of hafnium oxide, tantalum oxide, hafnium oxynitride, and tantalum oxynitride along with a HfxTayOzNw film, or various other combinations. In an embodiment, a dielectric layer is formed substantially as the hafnium tantalum oxynitride film.
In various embodiments, the structure of an interface between a dielectric layer and a substrate on which it is disposed is controlled to limit the inclusion of silicon oxide, since a silicon oxide layer might reduce the effective dielectric constant of the dielectric layer. In an embodiment, the material composition and properties for an interface layer are dependent on process conditions and the condition of the substrate before forming the dielectric layer. In an embodiment, though the existence of an interface layer effectively reduces the dielectric constant associated with the dielectric layer and its substrate, the interface layer, such as a silicon oxide interface layer or other composition interface layer, may improve the interface density, fixed charge density, and channel mobility of a device having this interface layer.
In an embodiment, a hafnium tantalum oxynitride layer is doped with other elements. The doping may be employed to enhance the leakage current characteristics of the dielectric layer containing the HfxTayOzNw film by providing a disruption or perturbation of the hafnium tantalum oxynitride structure. In an embodiment, such doping is realized by substituting a sequence of one of these elements for a hafnium sequence, a tantalum sequence, or various combinations of sequences. The choice for substitution may depend on the form of the hafnium tantalum oxynitride structure with respect to the relative amounts of hafnium atoms and tantalum atoms desired in the oxide. In an embodiment, to maintain a substantially hafnium tantalum oxynitride, the amount of dopants inserted into the oxynitride are limited to a relatively small fraction of the total number of hafnium and tantalum atoms.
After forming a dielectric having a hafnium tantalum oxynitride layer, other material may be formed upon the hafnium tantalum oxynitride layer. In an embodiment, the other material is a conductive material. The conductive material may be used as an electrode. Such electrodes may be used as capacitor electrodes, control gates in transistors, or floating gates in floating gate transistors, among others. In an embodiment, the conductive material is a metal or conductive metal nitride. In an embodiment, the conductive material is a conductive semiconductor material. In an embodiment, the conductive material is formed by ALD processes. In an embodiment, the conductive material is formed by a substitution process. In an embodiment, the conductive material is formed in a self-alignment process.
In various embodiments, a conductive layer is deposited by atomic layer deposition on a layer of HfTaON or on a dielectric layer containing a layer of HfTaON. A metal layer may be deposited by atomic layer deposition in an ALD cycle having a halide precursor containing the metal to be deposited and a reactant precursor containing hydrogen. Metal layer formation by ALD is not limited to halide precursors and hydrogen reactant precursors. In various embodiments, precursors are selected to form ALD conductive layers such as aluminum (Al), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), gold alloy, silver alloy, copper (Cu), platinum (Pt), rhenium (Re), ruthenium (Ru), rhodium (Rh), nickel (Ni), osmium (Os), palladium (Pd), iridium (Ir), cobalt (Co), germanium (Ge), or metallic nitrides such as WN, TiN or TaN. Formation of ALD conductive layers is not limited to the abovementioned materials.
In an example embodiment, a tantalum layer is formed on a HfTaON film by atomic layer deposition using a tantalum-containing precursor. In an embodiment, a tantalum halide precursor such as TaF5 or TaCl5 is used with hydrogen as a reactant precursor. In an embodiment, a TaCl5 precursor is used with an atomic hydrogen reactant precursor. The atomic hydrogen reactant precursor may be provided using a plasma. In an embodiment, the substrate temperature is held at a temperature ranging from about 250° C. to about 400° C. The hydrogen reactant precursor reacts at the substrate to remove the halogen, which forms the selected tantalum halide precursor, leaving tantalum on the substrate surface. After pulsing a tantalum-containing precursor and after pulsing its reactant precursor, the reaction chamber may be purged of excess precursor and/or by-products. In various embodiments, use of the individual tantalum-containing precursors is not limited to the temperature ranges of the above example embodiments. Further, forming tantalum by atomic layer deposition is not limited to the abovementioned precursors. In addition, the pulsing of the tantalum precursor may use a pulsing period that provides uniform coverage of a monolayer on the surface or may use a pulsing period that provides partial coverage of a monolayer on the surface. The tantalum layer may be structured as one or more monolayers. The tantalum layer may have a thickness ranging from a monolayer to thousands of angstroms or more.
In an embodiment, a metal nitride layer is deposited by atomic layer deposition using a precursor containing the metal to be deposited and a reactant precursor containing nitrogen in an ALD cycle. In an example embodiment, a tantalum nitride layer is formed with a HfTaON film by atomic layer deposition using a tantalum-containing precursor. A nitrogen-containing precursor may be used as the reactant precursor for the tantalum-containing precursor. The tantalum-containing precursor and the nitrogen-containing precursor may be selected such that their use does not form a tantalum oxide in the layer of tantalum nitride being formed. The tantalum-containing precursor and the nitrogen-containing precursor may be selected such that these precursors do not include oxygen as an elemental component. In an embodiment, a tantalum halide precursor is used with NH3 as a reactant precursor. In an embodiment, a TaCl4 precursor is used with a NH3 reactant precursor. In an embodiment, the substrate temperature is held at a temperature ranging from about 380° C. to about 500° C. In an embodiment, the substrate temperature is held at a temperature less than 600° C. After pulsing a tantalum-containing precursor and after pulsing its reactant precursor, the reaction chamber may be purged of excess precursor and/or by-products. In various embodiments, use of the individual tantalum-containing precursors is not limited to the temperature ranges of the above example embodiments. In various embodiments, forming tantalum nitride by atomic layer deposition is not limited to the abovementioned precursors, but may include other precursors containing tantalum and nitrogen. In addition, the pulsing of the tantalum precursor may use a pulsing period that provides uniform coverage of a monolayer on the surface or may use a pulsing period that provides partial coverage of a monolayer on the surface. The tantalum nitride layer may be structured as one or more monolayers. The tantalum nitride layer may have a thickness ranging from a monolayer to thousands of angstroms or more.
As shown in
After the metal layer 509 is deposited on the gate substitutable layer, a metal-substitution reaction may be induced. The reaction can be provided by annealing the structure in a non-oxidizing atmosphere such as a nitrogen gas or a forming gas. The heating urges diffusion or dissolution of the intended gate material in metal layer 509 for the substitutable material 504. The substitution process is bounded by the spacers 506 and the gate dielectric 503.
At the conclusion of the substitution reaction, the residual metal of layer 509 and the substitutable material may be removed, perhaps by using conventional planarization.
Drain and source contacts (not shown) can be formed, as well as interconnects to other transistors or components, using conventional techniques. Another heat treatment may occur after packaging the structure (e.g., an integrated circuit) in a protective housing in an attempt to minimize the resistivity of the metal gate contacts and other metal interconnections.
The metal gate substitution technique, as disclosed herein, can be applied to MOS devices, as generally illustrated in
A metal substitution reaction substitutes or replaces the substitutable material (e.g. silicon, germanium, silicon-germanium, carbon) with a metal. After the substitution, the resulting gate structure includes substantially all of the desired metal. Small amounts of the substitutable material may remain in the gate structure. The substitution reaction can be induced by heating the integrated circuit assembly to a desired temperature in a vacuum, nitrogen, argon, forming gas or other non-oxidizing atmosphere. Heating causes diffusion of the metal layer 509 into the substitutable layer. The annealing temperature for the substitution should be less than the eutectic (lowest melting) temperature of materials involved in the substitution for the reaction for substitution to occur. In an embodiment, to form a gold gate, a metal layer is formed from gold and annealed at approximately 300° C. to substitute the gold for a silicon substitutable structure. In an embodiment, to form a silver gate, a metal layer is formed from silver and annealed at approximately 500-600° C. to substitute the silver for a silicon substitutable structure. A polysilicon and germanium substitutable material may be used, which reduces the anneal temperature.
According to various embodiments, the gate substitutable material 504 shown in
Various embodiments form an integrated circuit structure using two or more substitution reactions. Relatively higher temperature substitution processes can be performed before relatively lower temperature substitution processes. One application for multiple substitution reactions is to independently adjust work functions of NMOS and PMOS transistors in CMOS integrated circuits. Multiple substitution reactions are not limited to this CMOS integrated circuit application. Additional information regarding metal substitution can be found in U.S. patent application Ser. No. 11/176,738, referenced previously.
In
In
In
In
In various embodiments, source/drain extensions may be formed after removing the carbon sidewall spacers and before replacing with non-carbon sidewall spacers. An etch barrier can be used in various embodiments to separate the sacrificial carbon gate from the sacrificial carbon sidewall spacers. In various embodiments, the carbon sacrificial gate is replaced with aluminum (Al), alloys of aluminum, tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), gold alloy, silver alloy, copper (Cu), platinum (Pt), rhenium (Re), ruthenium (Ru), rhodium (Rh), nickel (Ni), osmium (Os), palladium (Pd), iridium (Ir), cobalt (Co), germanium (Ge), or metallic nitrides such as WN, TiN or TaN covered by metals. The high-K gate dielectric formed at 802 may be one of a number of high-K gate dielectrics containing HfTaON.
In various embodiments, construction of an integrated circuit structure includes a dielectric containing HfTaON on which is disposed a self-aligned metal electrode. Additional information regarding a self-aligned metal electrode used as a transistor gate can be found in U.S. patent application Ser. No. 11/216,375, referenced previously.
Applications containing electronic devices having dielectric layers containing hafnium tantalum oxynitride film include electronic systems for use in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, which may include multilayer, multichip modules. Such dielectric layers may be configured as multiple layers containing at least one layer of HfTaON or configured substantially as a HfTaON layer. In addition, such dielectric layers may be configured in contact with a metal electrode. For a given applied voltage, the magnitude (or strength) of an electric field across the HfTaON layer is based on its dielectric constant and its thickness. In general, the strength of such an electric field decreases as the value of the dielectric constant increases, and also as dielectric thickness increases. In some embodiments, the thickness of the hafnium tantalum oxynitride layer may be adjusted to obtain a specified electric field between one or more electrodes. In various embodiments, the dielectric constant of the hafnium tantalum oxynitride layer may be adjusted to obtain a specified electric field between one or more electrodes. In some embodiments, the dielectric constant and thickness of the hafnium tantalum oxynitride layer in combination may be adjusted to obtain a specified electric field between one or more electrodes. The electric field strength across a HfTaON layer may be adjusted as desired to achieve a particular circuit function or circuit characteristic. Such circuitry can be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, and others.
In an embodiment, a gate 1050 is formed on and contacts gate dielectric 1040. In an embodiment, gate 1050 includes conductive material. In an embodiment, gate 1050 includes a conductive material structured as one or more monolayers. In an embodiment, the conductive material layer is an ALD conductive material layer. In an embodiment, the conductive material layer is a substituted metal layer. In an embodiment, the conductive material layer is a self-aligned metal layer. In an embodiment, the thickness of the conductive layer ranges from a monolayer to thousands of angstroms or more.
An interfacial layer 1031 may form between body region 1032 and gate dielectric 1040. In an embodiment, an interfacial layer is limited to a relatively small thickness compared to gate dielectric 1040, or to a thickness significantly less than gate dielectric 1040 as to be effectively eliminated. In an embodiment, forming the substrate and the source and drain regions is performed using standard processes known to those skilled in the art. In an embodiment, the sequencing of the various elements of the process for forming a transistor is conducted with fabrication processes known to those skilled in the art. In an embodiment, transistor 1000 is a MOSFET transistor. In an embodiment, transistor 1000 is a germanium MOSFET structure. In an embodiment, transistor 1000 is a silicon MOSFET structure. In an embodiment, transistor 1000 is a silicon-germanium (SiGe) MOSFET structure. In an embodiment, transistor 1000 is a gallium arsenide MOSFET structure. In an embodiment, transistor 1000 is a NMOS transistor. In an embodiment, transistor 1000 is a PMOS transistor. Transistor 1000 is not limited to the arrangement illustrated in
In an embodiment, gate dielectric 1140 includes a dielectric containing an atomic layer deposited HfxTayOzNw film formed in embodiments similar to those described herein. In an embodiment, gate dielectric 1140 is realized as a dielectric layer formed substantially of HfxTayOzNw. In an embodiment, gate dielectric 1140 is a dielectric stack containing at least one HfxTayOzNw film and one or more layers of other insulating materials.
In an embodiment, floating gate 1152 is formed on and contacts gate dielectric 1140. In an embodiment, floating gate 1152 includes conductive material. In an embodiment, floating gate 1152 is structured as one or more monolayers. In an embodiment, floating gate 1152 is an ALD layer. In an embodiment, floating gate 1152 is a substituted metal layer. In an embodiment, floating gate 1152 is a self-aligned metal layer. In an embodiment, the thickness of the floating gate layer ranges from a monolayer to thousands of angstroms or more.
In an embodiment, floating gate dielectric 1142 includes a dielectric containing a HfxTayOzNw film. In an embodiment, the HfxTayOzNw film is structured as one or more monolayers. In an embodiment, the HfxTayOzNw is formed using atomic layer deposition techniques. In an embodiment, floating gate dielectric 1142 is realized as a dielectric layer formed substantially of HfxTayOzNw. In an embodiment, floating gate dielectric 1142 is a dielectric stack containing at least one HfxTayOzNw film and one or more layers of other insulating materials.
In an embodiment, control gate 1150 is formed on and contacts floating gate dielectric 1142. In an embodiment, control gate 1150 includes conductive material. In an embodiment, control gate 1150 is structured as one or more monolayers. In an embodiment, the control gate 1150 is an ALD layer. In an embodiment, control gate 1150 is a substituted metal layer. In an embodiment, control gate 1150 is a self-aligned metal layer. In an embodiment, the thickness of the control gate layer 1150 ranges from a monolayer to thousands of angstroms or more. In an embodiment, control gate 1150 is structured as one or more monolayers.
In an embodiment, both gate dielectric 1140 and floating gate dielectric 1142 are formed as dielectric layers containing a HfxTayOzNw film structured as one or more monolayers. In an embodiment, control gate 1150 and floating gate 1152 are formed as conductive layers. In an embodiment, the control gate 1150 and floating gate 1152 are structured as one or more monolayers. In an embodiment, control gate 1150 and floating gate 1152 are ALD layers. In an embodiment, control gate 1150 and floating gate 1152 are substituted metal layers. In an embodiment, control gate 1150 and floating gate 1152 are self-aligned metal layers. In an embodiment, gate dielectric 1140, floating gate dielectric 1142, control gate 1150, and floating gate 1152 are realized by embodiments similar to those described herein, with the remaining elements of the transistor 1100 formed using processes known to those skilled in the art. In an embodiment, gate dielectric 1140 forms a tunnel gate insulator and floating gate dielectric 1142 forms an inter-gate insulator in flash memory devices, where gate dielectric 1140 and floating gate dielectric 1142 may include a hafnium tantalum oxynitride film structured as one or more monolayers. Floating gate transistor 1100 is not limited to the arrangement illustrated in
In an embodiment, dielectric layer 1220, containing a HfxTayOzNw film, and conductive layers 1210, 1220 are formed using various embodiments described herein. In an embodiment, dielectric layer 1220 is realized as a dielectric layer formed substantially of HfxTayOzNw. In an embodiment, dielectric layer 1220 is a dielectric stack containing at least one HfxTayOzNw film and one or more layers of other insulating materials. Embodiments for a hafnium tantalum oxynitride film include, but are not limited to, a capacitor in a DRAM and capacitors in analog, radio frequency (RF), and mixed signal integrated circuits. Mixed signal integrated circuits are integrated circuits that may operate with digital and analog signals.
In an embodiment, dielectric structure 1300 includes one or more layers 1305-1, 1305-2 . . . 1305-N as dielectric layers other than a HfTaON layer, where at least one layer is a HfTaON layer. In an embodiment, dielectric layers 1305-1, 1305-2 . . . 1305-N include a HfO layer, a TaO layer, a HfON layer, a TaON layer, or various combinations of these layers. In an embodiment, dielectric layers 1305-1, 1305-2 . . . 1305-N include an insulating metal oxide layer. In an embodiment, dielectric layers 1305-1, 1305-2 . . . 1305-N include an insulating nitride layer. In an embodiment, dielectric layers 1305-1, 1305-2 . . . 1305-N include an insulating oxynitride layer. In an embodiment, dielectric layers 1305-1, 1305-2 . . . 1305-N include an insulating silicate layer.
Various embodiments for a dielectric layer containing a hafnium tantalum oxynitride film structured as one or more monolayers may enhance device performance by providing devices with reduced leakage current. Such improvements in leakage current characteristics may be attained by forming one or more layers of a hafnium tantalum oxynitride in a nanolaminate structure with other metal oxides, non-metal-containing dielectrics, or combinations thereof. The transition from one layer of the nanolaminate to another layer of the nanolaminate can disrupt an ordered structure in the nanolaminate stack. The term “nanolaminate” means a composite film of ultra thin layers of two or more materials in a layered stack. Typically, each layer in a nanolaminate has a thickness of less than 20 nm and may have a thickness less than a monolayer. In an embodiment, a HfO/HfTaON nanolaminate contains alternating layers of a HfO and HfTaON. In an embodiment, a HfON/HfTaON nanolaminate contains alternating layers of a HfON and HfTaON. In an embodiment, a TaON/HfTaON nanolaminate contains alternating layers of TaON and HfTaON. In an embodiment, a TaO/HfTaON nanolaminate contains alternating layers of TaO and HfTaON. In an embodiment, a Ta2O5/HfTaON nanolaminate contains alternating layers of a Ta2O5 and HfTaON. In an embodiment, a HfO2/TaAlON nanolaminate contains alternating layers of HfO2 and TaAlON. In an embodiment, a Ta2O5/AlON/HfO2/TaON/TaAlON nanolaminate contains various permutations. In an embodiment, a HfO/TaON/TaO/HfON/HfTaON nanolaminate contains various permutations of hafnium oxide layers, tantalum oxynitride layers, tantalum oxide layers, hafnium oxynitride layers, and hafnium tantalum oxynitride layers.
In an embodiment, the sequencing of the layers in dielectric structure 1300 structured as a nanolaminate depends on the application. The effective dielectric constant associated with nanolaminate structure 1300 is that attributable to N capacitors in series, where each capacitor has a thickness defined by the thickness and composition of the corresponding layer. In an embodiment, by selecting each thickness and the composition of each layer, a nanolaminate structure may be formed with a predetermined dielectric constant. Embodiments for structures such as nanolaminate structure 1300 is used as nanolaminate dielectrics in flash memory devices as well as other integrated circuits. In an embodiment, a layer of the nanolaminate structure 1300 is used to store charge in a flash memory device. The charge storage layer of a nanolaminate structure 1300 in a flash memory device may be a silicon oxide layer.
In an embodiment, transistors, capacitors, and other devices include dielectric films containing a layer of a hafnium tantalum oxynitride composition with an electrode. In an embodiment, the hafnium tantalum oxynitride layer is an atomic layer deposited hafnium tantalum oxynitride layer. In an embodiment, the electrode is an atomic layer deposited electrode. In an embodiment, the electrode is a substituted metal layer. In an embodiment, the electrode is a self-aligned metal layer. In an embodiment, dielectric films containing a hafnium tantalum oxynitride layer with an electrode are implemented into memory devices and electronic systems including information handling devices. In various embodiments, information handling devices include wireless systems, telecommunication systems, and computers. In various embodiments, such electronic devices and electronic apparatus are realized as integrated circuits. Examples of circuits include, without limitation, transmit and receive circuitry, radio frequency transceivers, and optical transmitters and receivers.
In an embodiment, memory 1525 is realized as a memory device containing a HfTaON film structured as one or more monolayers with an electrode. In an embodiment, a HfTaON structure with a conductive layer is formed in a memory cell of a memory array. In an embodiment, such a structure is formed in a capacitor in a memory cell of a memory array. In an embodiment, such a structure is formed in a transistor in a memory cell of a memory array. In an embodiment, it will be understood that embodiments are equally applicable to any size and type of memory circuit and are not intended to be limited to a particular type of memory device. Memory types include a DRAM, SRAM (Static Random Access Memory) or Flash memories. Additionally, the DRAM could be a synchronous DRAM commonly referred to as SGRAM (Synchronous Graphics Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), SDRAM II, and DDR SDRAM (Double Data Rate SDRAM), as well as other emerging DRAM technologies.
This description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.
The terms wafer and substrate may be used interchangeably herein to refer generally to any structure on which integrated circuits are formed and also to such structures during various stages of integrated circuit fabrication. The term substrate is understood to include a semiconductor wafer; it may be used to refer to semiconductor structures during processing and may include other layers that have been fabricated thereupon. Both wafers and substrates can include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to generally include n-type and p-type semiconductors and the term insulator or dielectric is defined to include any material that is less electrically conductive than the materials referred to as conductors. The term transistor is understood generally to include an insulated gate field effect transistor such as a metal oxide field effect transistor (MOSFET) and includes complementary metal oxide field effect transistor (CMOS), p-channel (PMOS) and n-channel (NMOS) field effect transistors and other such using an electric field for producing a charge inversion layer. The term capacitor is understood to generally include capacitive structures such as used to store electric charge or to provide an electric field between conductive regions. The term composite is understood generally to include a mixture of two or more elements. The terms, refractory oxide, refractory nitride and refractory oxynitride is understood generally to mean an oxide, a nitride, and an oxynitride, respectively, that include a refractory metal. The term refractory metal-based is understood to mean a composition including a refractory metal.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Various embodiments may use permutations and/or combinations of embodiments described herein. It is to be understood that the above description is intended to be illustrative, and not restrictive, and that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Combinations of the above embodiments and other embodiments will be apparent to those of skill in the art upon studying the above description.
This application is a divisional of U.S. application Ser. No. 13/332,222, filed Dec. 20, 2011, now issued as U.S. Pat. No. 8,466,016, which is a divisional of U.S. application Ser. No. 12/581,628, filed Oct. 19, 2009, now issued as U.S. Pat. No. 8,084,371, which is a divisional of U.S. application Ser. No. 11/515,114 filed Aug. 31, 2006, now issued as U.S. Pat. No. 7,605,030, all of which are incorporated herein by reference in their entirety. This application is related to the commonly assigned applications U.S. application Ser. No. 10/229,903, entitled “ATOMIC LAYER DEPOSITED HfSiON DIELECTRIC FILMS,” filed on 28 Aug. 2002, now issued as U.S. Pat. No. 7,199,023; U.S. application Ser. No. 11/216,474, entitled “LANTHANUM ALUMINUM OXYNITRIDE DIELECTRIC FILMS,” filed on 31 Aug. 2005, now issued as U.S. Pat. No. 7,410,910, U.S. application Ser. No. 11/355,490, entitled “CONDUCTIVE LAYERS FOR HAFNIUM SILICON OXYNITRIDE FILMS,” filed on 16 Feb. 2006; U.S. application Ser. No. 11/010,529, entitled “ATOMIC LAYER DEPOSITED LANTHANUM HAFNIUM OXIDE DIELECTRICS,” filed on 13 Dec. 2004, now issued as U.S. Pat. No. 7,235,501, U.S. application Ser. No. 10/352,507, entitled “ATOMIC LAYER DEPOSITION OF METAL OXYNITRIDE LAYERS AS GATE DIELECTRICS AND SEMICONDUCTOR DEVICE STRUCTURES UTILIZING METAL OXYNITRIDE LAYER,” filed on 27 Jan. 2003, U.S. patent application Ser. No. 11/029,757, entitled “ATOMIC LAYER DEPOSITED HAFNIUM TANTALUM OXIDE DIELECTRICS,” filed on 5 Jan. 2005, now issued as U.S. Pat. No. 7,560,395, U.S. patent application Ser. No. 11/176,738, entitled “METAL-SUBSTITUTED TRANSISTOR GATES,” filed on 7 Jul. 2005, now issued as U.S. Pat. No. 7,195,999, and U.S. patent application Ser. No. 11/216,375, entitled “SELF ALIGNED METAL GATES ON HIGH-K DIELECTRICS,” filed 31 Aug. 2005, now issued as U.S. Pat. No. 7,211,492, which applications are incorporated herein by reference. This application is also related to the commonly assigned applications U.S. application Ser. No. 11/514,655, entitled “ATOMIC LAYER DEPOSITED TANTALUM ALUMINUM OXYNITRIDE FILMS”, U.S. application Ser. No. 11/514,533, entitled “ATOMIC LAYER DEPOSITED SILICON LANTHANIDE OXYNITRIDE FILMS”, now issued as U.S. Pat. No. 7,432,548, U.S. application Ser. No. 11/514,601, entitled “TANTALUM SILICON OXYNITRIDE HIGH-K DIELECTRICS AND METAL GATES”, U.S. application Ser. No. 11/514,545, entitled “ATOMIC LAYER DEPOSITED TANTALUM LANTHANIDE OXYNITRIDE FILMS”, now issued as U.S. Pat. No. 7,544,604, U.S. application Ser. No. 11/498,578, entitled “DEPOSITION OF ZrAlON FILMS”, and U.S. application Ser. No. 11/514,558 entitled “HAFNIUM ALUMINIUM OXYNITRIDE HIGH-K DIELECTRIC AND METAL GATES”, which patent applications are incorporated herein by reference.
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| 20080032424 | Ahn et al. | Feb 2008 | A1 |
| 20080032465 | Ahn et al. | Feb 2008 | A1 |
| 20080054330 | Forbes et al. | Mar 2008 | A1 |
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| 20080087945 | Forbes et al. | Apr 2008 | A1 |
| 20080102629 | Vaartstra | May 2008 | A1 |
| 20080121962 | Forbes et al. | May 2008 | A1 |
| 20080124907 | Forbes et al. | May 2008 | A1 |
| 20080124908 | Forbes et al. | May 2008 | A1 |
| 20080193791 | Ahn et al. | Aug 2008 | A1 |
| 20080217676 | Ahn et al. | Sep 2008 | A1 |
| 20090032910 | Ahn et al. | Feb 2009 | A1 |
| 20120094477 | Forbes et al. | Apr 2012 | A1 |
| Number | Date | Country |
|---|---|---|
| 1096042 | May 2001 | EP |
| WO-0197257 | Dec 2001 | WO |
| WO-0231875 | Apr 2002 | WO |
| WO-2006026716 | Mar 2006 | WO |
| Entry |
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| Number | Date | Country | |
|---|---|---|---|
| 20130279259 A1 | Oct 2013 | US |
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| Parent | 13332222 | Dec 2011 | US |
| Child | 13915341 | US | |
| Parent | 12581628 | Oct 2009 | US |
| Child | 13332222 | US | |
| Parent | 11515114 | Aug 2006 | US |
| Child | 12581628 | US |
