Patent Application
20240347429
HEMTs (high-electron-mobility Field Effect Transistors) also known as heterostructure FETs (HFETs) and modulation-doped FETs (MODFETs) refer to transistor devices that include a two-dimensional charge carrier gas channel formed from a heterojunction between layers of type III-V semiconductor. This device concept offers very low on-resistance in comparison to other device technologies. Thus, discrete HEMT devices are popular choices for switching devices in power switching applications, i.e., applications that require voltage ratings of 250V, 500V, 1000V, etc. or greater, and/or current ratings of 1 A, 5 A, 10 A, etc. or greater. The semiconductor package used to contain and protect discrete HEMT devices represents an important design consideration that impacts cost and performance of the assembly. There is a need to provide high performance and low-cost packaging solutions for HEMT devices.
A semiconductor package is disclosed. According to an embodiment, the semiconductor package comprises a metal baseplate; first and second HEMT (high electron mobility transistor) dies each comprising a main surface with source, drain and gate terminals disposed thereon; a plurality of metal package terminals; and an encapsulant body of electrically insulating material, wherein the first and second HEMT dies are mounted on the metal baseplate with the main surfaces from each of the first and second HEMT dies facing away from the metal baseplate, wherein the encapsulant body encapsulates the first and second HEMT dies, wherein outer ends from each of the metal package terminals are exposed from the encapsulant body, and wherein each of the source, drain and gate terminals from the first and second HEMT dies is electrically connected via a bond wire-free connection to at least one of the metal package terminals.
According to another embodiment, the semiconductor package comprises a first metal baseplate; first and second HEMT (high electron mobility transistor) dies each comprising a main surface with source, drain and gate terminals disposed thereon; a plurality of planar metal leads; and an encapsulant body of electrically insulating material, wherein the first HEMT die is mounted on the first metal baseplate with the main surface of the first HEMT die facing away from the first metal baseplate, wherein the second HEMT die is arranged over the first HEMT die with the main surface of the second HEMT die facing the main surface of the first HEMT die, wherein the encapsulant body encapsulates the first and second HEMT dies, and wherein outer ends from each of the planar metal leads are exposed from the encapsulant body, and wherein each of the source, drain and gate terminals from the first and second HEMT dies is electrically connected via a bond wire-free connection to at least one of the planar metal leads.
A method of forming a semiconductor package is disclosed. According to an embodiment, the method comprises providing a first metal baseplate; providing a first HEMT die comprising a main surface with source, drain and gate terminals disposed thereon; mounting the first HEMT die on the first metal baseplate with the main surface from the first HEMT die facing away from first metal baseplate; providing a plurality of metal package terminals; electrically connecting each of the source, drain and gate terminals from the first HEMT die via a bond wire-free connection to at least one of the metal package terminals; and forming an encapsulant body of electrically insulating material that encapsulates the first HEMT die and exposes outer ends of the metal package terminals.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows.
Embodiments of a semiconductor package comprising one or more HEMT dies and a corresponding method of forming the semiconductor package are disclosed herein. Due to a simple carrier structure and a bond wire-free connection technique, the semiconductor package can be produced quickly and inexpensively in comparison to other techniques without sacrificing performance. Power semiconductor packages typically utilize multilayer carrier structures, e.g., PCBs (printed circuit boards), DBCs (direct bonded copper) substrates, IMS (insulated metal) substrates or AMB (active metal brazed) substrates. These multilayer carrier structures include structured metallization layers with insulating regions. By contrast, the carrier structure disclosed herein can be a simple unstructured piece of metal, and thus relatively inexpensive in comparison to a multilayer carrier structure. The HEMT dies of the disclosed embodiments have a lateral device configuration with an electrically inactive rear surface, and thus can be mounted directly on a metal carrier without impacting the function of the HEMT die or creating an electrical short between the HEMT die and another element mounted on the same carrier. Moreover, the external package terminals of the semiconductor package are formed by planar metal structures that are attached directly to the terminals of the HEMT die, thus eliminating the need to use a costly and time-consuming wire-bonding process.
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The semiconductor substrate 102 additionally comprises a base substrate 109 disposed below the active channel region 101. The base substrate 109 is an inactive part of the semiconductor substrate 102 that is used to epitaxially grow the type III-V semiconductor material for the active channel region 101. The base substrate 109 can correspond to a commercially available semiconductor wafer, e.g., a bulk silicon wafer, a wafer comprising sapphire, SiC, ceramic, or an SOI (silicon on insulator) substrate wafer.
The semiconductor substrate 102 additionally comprises an intermediate region 111 arranged between the active channel region 101 and the base substrate 109. The intermediate region 111 may include multiple different layers of semiconductor and/or insulating material. For example, the intermediate region 111 may comprise a lattice transition region formed from type III-V semiconductor layers with varying crystalline properties, e.g., multiple layers of AlN/GaN/AlGaN with varying aluminum content and/or with electrically insulating layers, e.g., layers comprising SiO2 (silicon dioxide), Si3N4 (silicon nitride), SiONXY (silicon oxynitride), etc., that are arranged to alleviate mechanical stresses in the semiconductor substrate 102 resulting from lattice mismatch between the base substrate 109 and the active channel region 101. Separately or in combination, the intermediate region 111 may comprise one or more type III-V semiconductor layers disposed near or interfacing with the channel layer 106, e.g., layers of GaN/AlGaN, that are configured to suppress parasitic channels of the device.
The HEMT die 100 further comprises source and drain electrodes 120, 122 and a gate structure 124 disposed on an upper surface 113 of the semiconductor substrate 102. The source and drain electrodes 120, 122 may be formed from any of a variety of conductive metals such as aluminum, titanium, copper, nickel, tungsten, etc., and any alloys thereof. The gate structure 124 comprises a gate electrode 126 that is formed from an electrical conductor such as a metal, e.g., aluminum, titanium, copper, nickel, tungsten, alloys thereof, etc., or a doped semiconductor, e.g., highly doped monocrystalline or polycrystalline semiconductors. The source and drain electrodes 120, 122 and the gate electrode 126 may be electrically isolated from one another by a first dielectric layer 105 disposed on the upper surface 113 of the semiconductor substrate 102. The first dielectric layer 105 can comprise any of a variety of electrical insulators, such as SiO2 (silicon dioxide), Si3N4 (silicon nitride), SiONXY (silicon oxynitride), etc.
The working principle of the HEMT die 100 is as follows. The two-dimensional charge carrier gas 108 is the active channel of the device that conducts a load current between the source and drain electrodes 120, 122. In an on-state of the device, the source and drain electrodes 120, 122 are electrically connected to one another via the two-dimensional charge carrier gas 108. In the off-state of the device, the two-dimensional charge carrier gas 108 is locally disrupted so that the source and drain electrodes 120, 122 are not connected to one another. The device is transitioned between the on-state and the off-state by the application of a gate potential to the gate electrode 126. This influences an electric field beneath the gate, which in turn determines whether the two-dimensional charge carrier gas 108 is locally disrupted. As shown, the gate electrode 126 is disposed within a trench formed in the barrier layer 104. This brings the gate electrode 126 closer to the two-dimensional charge carrier gas 108, thereby enabling better on-off control. The HEMT die 100 may have a variety of different gate configurations, including configurations wherein the gate structure 124 comprises a doped region, e.g., p-type GaN, that is configured to deplete the two-dimensional charge carrier gas 108 and realize a normally-off device configuration.
The HEMT die 100 is configured such that a rear side 115 of the semiconductor substrate 102 is electrically inactive. Because the HEMT die 100 is configured as a lateral device, i.e., a device that is configured to flow the load current parallel to the upper surface 113 of the semiconductor substrate 102, the rear side 115 of the semiconductor substrate 102 of the semiconductor substrate 102 does not require any electrical terminal and may be electrically floating relative to the active channel region 101. In the case that the HEMT die 100 includes a body contact, this contact may be formed in the upper surface 113 of the semiconductor substrate 102. The electrical isolation between the rear side 115 of the semiconductor substrate 102 and the active channel region 101 naturally results from the usage of low-doped material in the base substrate 109. For example, the base substrate 109 may comprise a low-doped semiconductor material, e.g., material with a dopant concentration on the order of 1015 dopant atoms/cm3, 1014 dopant atoms/cm3, 1013 dopant atoms/cm3, or less, which in essence as an electrical insulator.
According to an embodiment, the electrical isolation between the rear side 115 of the semiconductor substrate 102 and the active channel region 101 is enhanced by the incorporation of one or more intermediate dielectric layers 117 within the semiconductor substrate 102. These intermediate dielectric layers 117 can comprise any of a variety of electrical insulators, such as SiO2 (silicon dioxide), Si3N4 (silicon nitride), SiOXNY (silicon oxynitride), etc., and high-K dielectric materials such as HfO2.
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The metal baseplate 200 is a solid piece of unstructured metal. Thus, the metal baseplate 200 differs from a multilayer circuit carrier that comprise an electrically insulating substrate and structured metallization layers, e.g., DCB substrates, IMS substrates, AMB substrates, PCBs, etc. The metal baseplate 200 may comprise a core region formed from a thermally conductive metal, e.g., copper, aluminum, steel, and alloys thereof. Optionally, this core region may be covered by one or more plating layers comprising, e.g., Ni, Cu, Al, Ag, Au, Pd, Pt, etc., which may act as adhesion promotors, anti-corrosion layers, etc. The metal baseplate 200 may be provided from an unstructured solid piece of metal, e.g., sheet metal, with only minimal processing being performed, e.g., a simple cutting step,
The first and second HEMT dies 100 each comprise a main surface 208 with source, drain and gate terminals 210, 212, 214 disposed thereon. The first and second HEMT dies 100 are mounted such that the main surfaces 208 face away from the metal baseplate 200 and hence the source, drain and gate terminals 210, 212, 214 face away from the metal baseplate 200. The source, drain and gate terminals 210, 212, 214 may correspond to the source, drain, and gate electrodes 120, 122, 126, respectively, from the HEMT die 100 described with reference to
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One of the planar metal plates 218 is attached to each of the source, drain and gate terminals 210, 212, 214 from the first and second HEMT dies 100. This may be done using an electrically conductive attachment material, e.g., solder, sinter, conductive glue, etc. According to the depicted embodiment, one of the planar metal plates 218 is attached to both the drain terminal 212 from the first HEMT die 100 and the source terminal 210 from the second HEMT die 100. Apart from that, one of the planar metal plates 218 is attached individually to the source terminal 210 from the first HEMT die 100, to the drain terminal 212 from the second HEMT die 100, to the gate terminal 214 from the first HEMT die 100, and to the gate terminal 214 from the second HEMT die 100. This connection scheme creates a half-bridge circuit, wherein the first HEMT die 100 corresponds to the high-side switch of the half-bridge circuit and the second HEMT die 100 corresponds to the low-side switch of the half-bridge circuit.
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In the depicted embodiment, the vertical connection elements 220 are configured as pin-rivets, i.e., cylindrical structures that comprise an interior opening for the insertion of a cylindrical metal pin. More generally, the vertical connection elements 220 can have any of a wide variety of geometries and/or configurations. For example, the vertical connection elements 220 may comprise press-fit pins, other types of stanchion shaped structures that may be affixed directly to the planar metal plates 218, or planar metal leads that may protrude out from an encapsulant body.
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In addition to the depicted embodiments, the embodiments disclosed herein include single die embodiments. In one example of a single die embodiment, the methods of
In addition to the depicted embodiments, the embodiments disclosed herein include embodiments comprising more than two dies, including any full-bridge and/or multiphase package configuration. In one example of an embodiment comprising more than two dies, a semiconductor package may comprise three of the assemblies comprising the first HEMT die 100 and the second HEMT die 100 mounted on a single metal baseplate 200 and connected in a half-bridge configuration as described above, wherein the planar metal plates 218 form parallel connections with the source terminals 210 of the three high-side switches and the drain terminals 212 of the three low-side switches, thus forming a three-phase bridge configuration. In another example of an embodiment comprising more than two dies, a semiconductor package may comprise two of the assemblies comprising the first HEMT die 100 and the second HEMT die 100 mounted on a single metal baseplate 200 and connected in a half-bridge configuration as described above, wherein the planar metal plates 218 form parallel connections with the source terminals 210 of the two high-side switches and the drain terminals 212 of the two low-side switches, thus forming a two-phase multi bridge configuration.
In addition to the depicted embodiments, the embodiments disclosed herein include an embodiment with a pair of HEMT dies 100 arranged on top of one another, e.g., as described in
In addition to the depicted embodiments, the embodiments disclosed herein include an embodiment wherein the semiconductor package is implemented as a power module. In that case, the metal baseplate 200 can surrounded by a housing and the encapsulant 220 can correspond to a potting compound such as a silicone based dielectric gel that is initially flowed around the first and second HEMT dies 100 and subsequently hardened by a curing process.
Although the present disclosure is not so limited, the following numbered examples demonstrate one or more aspects of the disclosure.
The HEMT die 100 described herein can comprise a semiconductor substrate 102 comprising any combination of type III-V semiconductor materials capable of forming a two-dimensional charge carrier gas at a heterojunction between type III-V semiconductor materials of different bandgap. These type III-V semiconductor materials include binary III-V semiconductor materials such as Gallium nitride (GaN), gallium arsenide (GaAs), aluminium nitride (AlN), aluminium arsenide (AlAs), indium nitride (InN), indium arsenide (InAs), etc., and ternary or quarternary type III-V semiconductor materials such as aluminium gallium nitride (AlGaN), aluminium gallium arsenide (AlGaAs), indium gallium nitride (InGaN), indium aluminium gallium nitride (InAlGaN), etc.
As used herein, the phrase “type III-V semiconductor material” refers to a compound material that includes at least one Group III element, such as aluminum (AI), gallium (Ga), indium (In), and boron (B) and at least one Group IV element, such as nitrogen (N), phosphorous (P), and arsenic (As), and including but not limited to any of its alloys, such as aluminum gallium nitride (AlxGa(1-x)N), indium gallium nitride (InyGa(1-y)N), aluminum indium gallium nitride (AlxInyGa(1-x-y)N), gallium arsenide phosphide nitride (GaAsaPbN(1-a-b)), and aluminum indium gallium arsenide phosphide nitride (AlxInyGa(1-x-y)AsaPbN(1-a-b)), for example. Aluminum gallium nitride and AlGaN refers to an alloy described by the formula AlxGa(1-x)N, where 0<x<1.
Spatially relative terms such as “under,” “below,” “lower,” “over,” “upper” and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as “first,” “second,” and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.
As used herein, the terms “having,” “containing,” “including,” “comprising” and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a,” “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.
With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.
