Patent Application
20100090265
The invention relates generally to electronic memory, and more specifically to a high density nanodot nonvolatile memory.
Computers and other electronic systems that handle or process information often need to store the information for a period of time while working with it. Some information is stored in volatile memory such as the dynamic random access memory that is commonly used in personal computers, while other information is stored in a more permanent way such as in hard disk drives, CD-ROM or DVD, or other long-term storage that is typically high in capacity but slow relative to most memory systems. Dynamic random access memory is characterized as volatile because data stored in such memory typically is lost when power is removed, while data stored on a hard disk drive, CD-ROM or other such storage is typically retained for a significant time in the absence of power. Some types of data storage resemble memory in their structure and operation, but are not volatile and are known as nonvolatile memories.
A variety of computer systems and electronic devices store information in such memory that is not volatile, or does not lose its content when power is disconnected. These nonvolatile memories can be reprogrammed, read, and erased electronically, and are particularly well suited to storing information such as music in digital audio players, pictures in digital cameras, and configuration data in cellular telephones. One such nonvolatile memory is commonly known as flash memory, named in part because a flash operation is used to erase the content of a block of data before it is reprogrammed, and is packaged for consumer use in products such as CompactFlash memory cards, USB flash memory drives, and other such devices.
Flash memory comprises a number of cells, each of which typically stores a single binary digit or bit of information. A typical flash memory or nonvolatile memory cell comprises a field effect transistor having an electrically isolated floating gate that controls electrical conduction between source and drain regions of the memory cell. Data is represented by a charge stored on the floating gate, and the resulting conductivity observed between the source and drain regions.
Modern flash memory cells therefore require a transistor structure including a floating gate for each bit or binary element of information stored, as well as a series of transistors used to select or access specific memory bits or words. The size and power required to operate these nonvolatile memories is therefore not trivial, and imposes limits on the physical size and capacity of a nonvolatile memory. Further, degradation of operational elements such as the tunneling of electrons onto and off of the floating gate in a nonvolatile memory cell can change the operating characteristics of nonvolatile memory over time, limiting its reliability and useful life.
Improvements in many aspects of nonvolatile data storage, including density, capacity, power consumption, and reliability are therefore desirable.
In the following detailed description of example embodiments of the invention, reference is made to specific examples by way of drawings and illustrations. These examples are described in sufficient detail to enable those skilled in the art to practice the invention, and serve to illustrate how the invention may be applied to various purposes or embodiments. Other embodiments of the invention exist and are within the scope of the invention, and logical, mechanical, electrical, and other changes may be made without departing from the scope or extent of the present invention. Features or limitations of various embodiments of the invention described herein, however essential to the example embodiments in which they are incorporated, do not limit the invention as a whole, and any reference to the invention, its elements, operation, and application do not limit the invention as a whole but serve only to define these example embodiments. The following detailed description does not, therefore, limit the scope of the invention, which is defined only by the appended claims.
One example embodiment of the invention provides a nanodot nonvolatile memory element comprising a substrate having a source and a drain region formed therein, and an insulating layer formed on the substrate. The insulating layer contains a nanocrystalline floating gate of approximately three to six nanometers in diameter formed at a distance of approximately two to five nanometers from the substrate, and a carbon nanotube control gate having a diameter of approximately six nanometers or less is formed at a distance of approximately 10-15 nanometers from the substrate. The terms floating gate and floating node are used interchangeably for purposes of this application, and the terms gate, node, and other terms that may be used in the claims are not limited by the examples presented here. In a further embodiment, at least one of the carbon nanotube control gate and the nanocrystalline floating gate are formed via a mask that is formed via self-aligning chaperonin proteins.
Current nonvolatile flash memories are constructed using features in the micron or micro-meter range in size. For example a 0.5 micron process features elements such as conductive lines, transistor components, and other features having widths as small as half a micrometer. While these sizes are extremely small by the standards of only a few decades ago and have enabled much of the power, portability, and performance of electronic devices such as portable computers, cell phones, portable digital music players, and the like, there is a demand for even smaller electronic components. One such example is demand for higher capacity storage that takes less space to store the same amount of data, or that can store significantly more data in the same space. Such a technology might enable storage of hundreds of movies on a portable digital media player that today is capable only of storing hundreds of songs, or enable storage of very large volumes of information such as detailed weather simulation data over a long period of time.
Some embodiments of the invention seek to provide higher storage capacity by providing nanodot or nano-scale nonvolatile memory elements, or memory elements that are measured in nanometers or fractions of nanometers and that are significantly smaller than today's micron-size memory elements. To further illustrate the differences between traditional lithography-formed micron scale semiconductors and nano-sized devices, a prior art flash memory element is illustrated in
An insulator material such as silicon oxide (SiO2) is used to form an insulating layer 104, which has embedded within it a floating gate 105, fabricated from a conductor such as metal or polysilicon, and a control gate 106 similarly formed of a conductive material. The floating gate is not directly electrically coupled to another conductive element of the memory cell, but is “floating” in the insulating material 104. The floating gate is separated from the region of the p-type substrate material 103 between the source 101 and the drain 102 by a thin insulative layer of controlled thickness, such as 0.01 micrometers.
In operation, the floating gate 105 is able to store a charge due to its electrical isolation from other components of the memory cell. Setting or erasing a charge level on the floating gate 105 is performed via a tunneling process known as Fowler-Nordheim tunneling, in which electrons tunnel through the oxide layer separating the floating gate 105 from the substrate 103. Most flash memory cells are categorized as NOR flash or NAND flash, based on the parallel (NOR) or serial (NAND) arrangement of memory cells and the circuitry used to perform write, read, and erase operations.
To write a bit to a NOR flash memory cell as shown in
The floating gate thereby adopts a negative charge during the write process that counteracts any control gate positive charge's effect on the region of the substrate 103 between the source 101 and drain 102, raising the memory cell's threshold voltage that must be applied to the wordline to result in conduction across an inversion region in the p-type substrate material 103. In other words, when the wordline's voltage is brought to a logic 1 or high voltage such as five volts during a read operation, the cell will not turn on due to the higher threshold voltage caused by the electrons stored on the floating gate 105 during the write operation. The read voltage applied to the control gate is larger than the threshold voltage (Vt) of an erased memory cell, but not large enough to allow conduction across a substrate 103 inversion region of a cell that has been written.
NAND memory cells are organized in strings or chains of series memory cells, such as a chain of 32 cells coupled between a source line and a bit line as illustrated in
To erase a memory cell using typical NOR flash memory circuitry, a similar tunneling of electrons takes place from the floating gate to the source 101 of the memory cell. The source is in some embodiments more deeply diffused than the drain to enhance erase performance. A positive voltage such as twelve volts is applied to the source 101, the control gate 106 is grounded, and the drain 102 is left disconnected to perform an erase in one example. The large positive voltage on the source 101 attracts the negatively charged electrons, causing them to tunnel through the insulating layer 104 and leave the floating gate. Because there is relatively little current flow between the source and drain during an erase operation, performing an erase takes very little current and consumes relatively little power. In typical flash memory erase operations, a block of bits is erased at the same time, and the power consumed depends on the size of the block erased.
In another example of memory cell erase often used in NAND memory configurations, the source 301 and drain 302 are left floating, but the substrate material 303 is brought to a high positive voltage such as 20 volts, attracting the negatively charged electrons and causing them to tunnel from the floating gates through the oxide insulating layer 304 to the substrate material 303. This method is sometimes known as “channel erase”, because the channel substrate material 303 receives electrons from the floating gate.
The floating gate of a typical prior art nonvolatile memory cell such as that of
The carbon nanotube control gate 205 of this example is on the order of five nanometers in diameter, just as the nanodot crystal of this example is on the order of five nanometers in diameter. The distance between the carbon nanotube control gate 205 and the nanodot crystal floating node is on the order of 10 nanometers, and the distance between the nanodot crystal floating node and the silicon surface of substrate 203 is approximately 2-3 nanometers. In a further embodiment, self-capacitance of the device is reduced by isolating the gate region of the nanodot memory device with a surrounding SiO2 gate region isolation insulator, such as is shown at 207, and the source 201 and drain 202 regions of the transistor are made very shallow. The resulting reduction in self-capacitance of the memory device is important to ensure an adequate memory retention window for the device.
The gate region insulator 207 and the dielectric insulator material 204 have various compositions in various embodiments of the invention, including using single or multiple layers of different insulating materials to tailor device characteristics. For example, HfO2, SiC, GeC, GeC, LaAlO3, HfSiON, and SiO2 each have different electron barrier energies, and can be used alone, in layers, or in combination within the same layer to effectively control programming voltage, programming speed, and charge retention by altering the effective barrier energy and tunnel distance of injected electrons. Similarly, tailoring the insulating layer between the nanocrystalline floating node 206 and the carbon nanotube control gate 205 allows additional control of the programming voltage and self-capacitance of the memory element.
In operation, a programming voltage of approximately five to ten volts applied to the control gate using NOR programming methods to attract “hot” electrons, which are provided by grounding the source 201 and applying a supply voltage such as two to five volts to the drain 202. The nanodot memory element can also be programmed using NAND flash methods, such as by grounding the source and drain 201 and 202, and applying a higher voltage such as 15 volts to the carbon nanotube control gate 205. The applied control gate voltage is higher using NAND programming methods, due to the absence of “hot” or high-energy electrons flowing between the grounded source and drain.
The number of electrons on the nanocrystal floating node and the node's retention of electrons is influenced by various quantum mechanical principles, due in part to the very small size of the nanocrystalline floating node. When the floating node acquires a first surplus electron or charge, the electron repels other electrons due to the electric field surrounding the negatively charged particles associated with the electrostatic repulsion of like-charged particles. The energy the second electron needs to tunnel into the floating node is therefore somewhat greater than the energy needed by the first tunneling electron, making placement of a large number of negatively charged electrons in a very small space difficult. Even should several electrons tunnel and reside in a nanocrystalline floating node dot on the order of five nanometers, the proximity of the electrons to one another results in great enough repulsive forces for the electrons to tunnel back to the source or drain, resulting in an average of no more than a few electrons in the floating node.
Although a greater number of electrons in the nanocrystalline floating node dot would be easier to detect and make reading the state of the programmed memory cell more certain and reliable by causing a greater threshold shift for conduction across the substrate between the source and drain of the memory element, principles of quantum mechanics and electrostatics limit the charge that can reside in a nano-sized floating node. Some embodiments of the invention will therefore typically have floating node programmed state charges of only one or two electrons, rather than the thousands of electrons typically present in conventional lithography-produced nonvolatile memory devices.
Arrays of nanodot or nanocrystal floating node nonvolatile memory can be manufactured using the basic nanodot structure of
A series of nanodot or nanocrystal germanium floating nodes 301 are configured in a chain between a series of source and drain elements 302, where the chain is selected for operation by coupling to the bitline 303 and source line 304. The chain can therefore be selectively addressed or isolated from the source line 304 and bitline 303 by line select transistors 305.
To perform a read operation, the word line 306 of the selected memory cell is maintained at a low but positive voltage level while the word lines of unselected memory cells are brought to a sufficiently high voltage to cause the unselected memory node to conduct irrespective of any charge that may be on the floating nodes of the individual memory cells. If the selected memory cell has an uncharged floating memory node it will activate as a result of the low positive voltage level on the wordline, but if the nanocrystal floating node has a negative charge it will raise the threshold voltage of the selected memory cell above the low positive voltage applied to the control gate such that the cell does not conduct. The state of the memory cell's floating node can therefore be determined by monitoring conductivity or current flow between the common bit line and source line.
To perform a write operation, the bitline 303 is held at a selected voltage and the source line 304 is typically grounded via line select transistors 305 coupling the chain to a grounded source line 304 and powered bitline 303. The wordlines of the memory cells not being written are brought to a sufficiently high voltage to cause the memory cells to conduct irrespective of their floating gate charges or memory states, such as five to ten volts. The selected memory cell's wordline 306 is coupled to a significantly higher voltage, such as 15-20 volts. The voltage applied to the selected memory cell's wordline causes formation of an inversion region in the substrate channel and tunneling of electrons due to the attraction of electrons to the positively charged control gate coupled to the high voltage signal. The grounded source in combination with the inversion region in the substrate material provide a source for one or two electrons to tunnel in the memory cell's inversion region, causing electrons to inject across the insulator barrier due to the high electrical field present and becoming trapped on the nanocrystal floating node.
In the example memory array of
Next, a nitride or other hard mask layer 403 is formed on the HfAlO tunnel dielectric layer, and a protein mask is formed by transferring a pattern array of small proteins known as chaperonins 404 to the surface of the nitride. In one such example, a tunnel oxide layer immersed in a chaperonin protein bath will result in a protein assembly of chaperonins on the order of 10 nanometers apart, which can be used as a self-assembly template for uniform nanocrystal distribution. Further, the proteins are able to each capture a nanocrystal, aiding in alignment and placement of nanocrystals in some fabrication examples. Here, the self-aligned chaperonin proteins 404 are formed on the surface of the nitride, but in other embodiments they are formed on other surfaces, or the pattern they form is used to create a pattern or self-assembled lithography template applied to the nitride layer 404 of
The nitride is then etched to expose the tunnel dielectric layer 402 in areas where the self-aligned chaperonin proteins don't mask the nitride layer, forming nitride peaks 403 such as are shown in
A thicker layer of HfAlO is then formed as shown at 407, which serves to separate the nanocrystal floating gates 405 from the carbon nanotube control gates or wordlines 408, shown in
Wordlines are similarly coupled to the array by using a mask to form electrical contacts and studs, as is shown in
Similarly, in
In
In
Part of the insulating layer 1010 is removed in
The extremely high density of storage which can be achieved by the structures previously presented will pose some very difficult problems in the wiring and insulation of these devices. It is desirable to provide low resistivity in the metallurgy and also provide a highly electromigration resistant conductor. The resistance will be a function of both the wiring structures and the metal to silicon and the metal to metal contact resistance. The contact resistance will be a function of both photo-lithographic processing and the contact metallurgy. In order to improve the contact resistance of the metallurgy it is desirable that the metal which is making the contact be able to reduce any residual oxides present, i.e. reduce SiO2. This can be achieved by using a layer of ether Titanium, Zirconium or Hafnium as the contact material. The reason for this selection is the high solubility of oxygen in the metallic phase. For example the solubility of Oxygen in Titanium is approximately 10 at. % at 400 C and 33 at % above 600 C. Similar or higher solubilities of oxygen are found in the case on Zirconium and Hafnium. These solid solutions are all thermodynamically able to reduce SiO2 to a significant extent.
The choice of metallurgy will be made in one embodiment depending upon the final lithographic dimensions used for the first level metal. For extremely high density first level metal an Aluminum based metallurgy will be preferred, due to the lower intrinsic electron scattering of Al in contrast to Copper. This is of little consequence at larger dimensions, but for dimension of the order of the example presented here it becomes a factor in design. Although the resistance of copper is less than Aluminum in larger lines, the same does not hold true for extremely fine conductive lines. Depending upon the array size and performance requirements it may be desirable to strap the word lines with the first metal level. The first metal level can be ether Ti—AlCu—Ti or Zr—Cu— (cap). Depending upon the absolute pitch of the metallurgy used. If a Aluminum based metallurgy is used the contact metallurgy serves both to reduce contact resistance and improve electromigration resistance. As all three reactive metals have very low solubility in Aluminum, their effect on the line resistance will be similar.
In the example using Al Cu metallurgy the process will be as follows:
If a Cu metallurgy is desired it may be deposited by either electro or electroless plating. In this example, the contact metallurgy of choice is Zirconium as the maximum solubility of Zirconium in Copper is approximately ⅓ that of Hafnium and several hundred times less than Titanium. A memory array of the density proposed here will require at least three levels of metallurgy, preferably with a low resistance and with a high electromigration resistance. To provide high electromigration resistance, a process using nano-tube via structures may be employed. In one example where a nanotube via structure is used, the first metal level is covered with the desired insulator and vias opened. If the top surface can serve as a catalyst for nanotube deposition, it is exposed to a carbon plasma of the proper composition and the nanotubes are grown in the vias. If the top surface of the first conductor is not suitable for initiating nanotube growth then a suitable catalytic material is deposited in the via bottom. This may be done for example by electroless plating selective CVD or ion implantation. After the nanotubes are grown the top metal layer is deposited and the appropriate conducting pattern etched therein.
In each of these examples, a variety of further steps may be performed, and a variety of materials, steps, and other process elements can be changed to produce other results. For example, annealing the silicon after each diffusion of n-type material will typically result in better and more uniform diffusion with fewer defects than would be achieved by omitting this step. Similarly, certain materials used in these examples may be substituted for other materials having other electrical characteristics, such as forming metallic wordlines or bitlines rather than using carbon nanotube wordlines and bitlines.
Although certain examples shown and described here, other variations exist and are within the scope of the invention. It will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations of the example embodiments of the invention described herein. It is intended that this invention be limited only by the claims, and the full scope of equivalents thereof.
