Patent Grant
11171208
This disclosure relates to integrated circuits and the fabrication of microelectronic devices, including semiconductor devices, transistors and integrated circuits. More particularly, it relates to manufacturing of three-dimensional (3D) semiconductor devices.
In the manufacturing of a semiconductor device (especially on the microscopic scale), various fabrication processes are executed such as film-forming depositions, etch mask creation, patterning, material etching and removal, and doping treatments. These processes are performed repeatedly to form desired semiconductor device elements on a substrate. Historically, with microfabrication, transistors have been created in one plane, with wiring/metallization formed above the active device plane, and have thus been characterized as two-dimensional (2D) circuits or 2D fabrication. Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, yet scaling efforts are running into greater challenges as scaling enters single digit nanometer semiconductor device fabrication nodes. Semiconductor device fabricators have expressed a desire for 3D semiconductor circuits in which transistors are stacked on top of each other.
3D integration is seen as a viable option to continue semiconductor scaling in spite of inevitable saturation in critical dimension scaling. As the contacted gate pitch reaches its scaling limit due to manufacturing variability and electrostatic device limitations, two-dimensional transistor density scaling stops. Even experimental new transistor designs, such as vertical channel gate-all-around transistors, that may be able to one day overcome these contacted gate pitch scaling limits, do not promise to get semiconductor scaling back on track because resistance, capacitance, and reliability concerns limit wire pitch scaling, thereby limiting the density with which transistors can be wired into circuits.
3D integration, i.e. the vertical stacking of multiple devices, aims to overcome these scaling limitations by increasing transistor density in volume rather than area. Device stacking has been successfully demonstrated and implemented by the flash memory industry with the adoption of 3D NAND. Mainstream CMOS VLSI scaling, as used for example in CPU (central processing unit) or GPU (graphics processing unit) products, is exploring adoption of 3D integration as a primary means of moving the semiconductor roadmap forward, and thus desires enabling technologies.
Techniques herein include methods of making 3D transistors with integrated metal lines contained in the stack.
The fabrication flow herein allows for a central metal line to be isolated with a dielectric within a self-contained 3D silicon and 3D Metal Layout Network. Such techniques provide scaling of circuits. For example, 3D metal routing can be directed through a 3D transistor stack. The description focuses on showing one-metal connection lines as an example in place of 3aD epi nano-stack. Note, however, that N metal lines are possible. Such techniques provide significant savings.
Techniques herein provide transistor/semiconductor devices and methods of forming transistor/semiconductor devices to make a metal layer with dielectric isolation within existing 3D silicon stacks. This device and method enables higher 3D density circuits to be produced at reduced cost. In one example embodiment, a process flow uses two “disposable” epi layers to form an insulated metal line in the center of the nano-stack. In another example embodiment, a process flow uses two disposable epi layers to form an insulated metal line in the center of a nano-stack, but with a reduced need of Ru metal for the metal line.
The order of discussion of the different steps as described herein has been presented for clarity sake. In general, these steps can be performed in any suitable order. Additionally, although each of the different features, techniques, configurations, etc., herein may be discussed in different places of this disclosure, it is intended that each of the concepts can be executed independently of each other or in combination with each other. Accordingly, the present application can be embodied and viewed in many different ways.
This summary section does not specify every embodiment and/or incrementally novel aspect of the present application. Instead, this summary only provides a preliminary discussion of different embodiments and corresponding points of novelty over conventional techniques. Additional details and/or possible perspectives of the disclosed embodiments are described in the Detailed Description section and corresponding Figures of the present disclosure as further discussed below.
The application will be better understood in light of the description which is given in a non-limiting manner, accompanied by the attached drawings in which:
Techniques herein provide transistor/semiconductor devices and methods of forming transistor/semiconductor devices. They include techniques for metal routing and connections for 3D logic and memory. Metal routing and connections for 3D logic and memory is a difficult issue to resolve to make multiple metal connections. Techniques herein solve this issue by providing a method to make a metal layer with dielectric isolation within existing 3D silicon stacks. This device and method enables higher 3D density circuits to be produced at reduced cost. Having a metal line contained within a 3D nano-sheet enables easier connections for 3D logic and memory. This also provides better speed performance because there is less distance for a signal to travel for a given transistor connection. In one example embodiment, a process flow uses two “disposable” epi layers to form an insulated metal line in the center of the nano-stack. In another example embodiment, a process flow uses two disposable epi layers to form an insulated metal line in the center of a nano-stack, but with reduced need of Ru metal.
Referring now to the Figures, a process flow is shown that uses SiX4 and SiX5 disposable epitaxial nano-sheets to form an insulated metal line in the center of a nano-stack.
In
In this non-limiting embodiment, this example flow has one metal layer in the center of a 3D silicon plane nano-sheet stack. Also note only the edge of one nano-sheet stack is shown. SiX4 and SiX5 materials may be selectively removed later from other layers in the stack and to become future metal layers and oxide layer respectively. Additionally, GeX4 and GeX5 materials may also be used as layer material options. A given material in the nano-sheet stack can be etch selective relative to other materials, that is, being etched without etching remaining materials. Such etching for these materials is conventionally known. For example, a vapor-phase etching tool can be used to etch a given material by adjusting chemistry and etch parameters.
First, a dielectric, such as silicon dioxide (oxide), is deposited on the substrate 108. Oxide deposition and chemical-mechanical polishing (CMP) for planarization can be executed. This covers all the nano-sheet stacks in all x, y, and z directions along the C-C′ line (
Next, an etch mask is formed on the substrate to cover a portion of the nano-sheet stacks.
Next, SiX4 material is removed from uncovered portions of the stacks. An example result is shown in
SiX5 can then be removed, similar to the SiX4 removal (
In the preceding description, specific details have been set forth, such as a particular geometry of a processing system and descriptions of various components and processes used therein. It should be understood, however, that techniques herein may be practiced in other embodiments that depart from these specific details, and that such details are for purposes of explanation and not limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. Nevertheless, embodiments may be practiced without such specific details. Components having substantially the same functional constructions are denoted by like reference characters, and thus any redundant descriptions may be omitted.
Various techniques have been described as multiple discrete operations to assist in understanding the various embodiments. The order of description should not be construed as to imply that these operations are necessarily order dependent. Indeed, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
“Substrate” or “target substrate” as used herein generically refers to an object being processed in accordance with the invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or un-patterned, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures.
This application is based on and claims the benefit of and priority to U.S. Provisional Patent Application No. 62/944,941, entitled “HIGH PERFORMANCE CIRCUIT APPLICATIONS USING STACKED 3D METAL LINES”, filed on Dec. 6, 2019, the entire contents of which are herein incorporated by reference.
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| 9515138 | Doris | Dec 2016 | B1 |
| 20190097011 | Wu | Mar 2019 | A1 |
| 20190131394 | Reznicek | May 2019 | A1 |
| 20200105751 | Dewey | Apr 2020 | A1 |
| 20200118892 | Cheng | Apr 2020 | A1 |
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| Number | Date | Country | |
|---|---|---|---|
| 20210175327 A1 | Jun 2021 | US |
| Number | Date | Country | |
|---|---|---|---|
| 62944941 | Dec 2019 | US |
