Patent Application
20080211075
This invention relates to a structure of wafer level package (WLP), and more particularly to a fan-out wafer level package with die receiving through-hole and inter-connecting through holes formed within the substrate to improve the reliability and to reduce the device size.
In the field of semiconductor devices, the device density is increased and the device dimension is reduced, continuously. The demand for the packaging or interconnecting techniques in such high density devices is also increased to fit the situation mentioned above. Conventionally, in the flip-chip attachment method, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out by using a solder composite material through a solder mask for producing a desired pattern of solder bumps. The function of chip package includes power distribution, signal distribution, heat dissipation, protection and support . . . and so on. As a semiconductor become more complicated, the traditional package technique, for example lead frame package, flex package, rigid package technique, can't meet the demand of producing smaller chip with high density elements on the chip.
Furthermore, because conventional package technologies have to divide a dice on a wafer into respective dice and then package the die respectively, therefore, these techniques are time consuming for manufacturing process. Since the chip package technique is highly influenced by the development of integrated circuits, therefore, as the size of electronics has become demanding, so does the package technique. For the reasons mentioned above, the trend of package technique is toward ball grid array (BGA), flip chip (FC-BGA), chip scale package (CSP), Wafer level package (WLP) today. “Wafer level package” is to be understood as meaning that the entire packaging and all the interconnections on the wafer as well as other processing steps are carried out before the singulation (dicing) into chips (dice). Generally, after completion of all assembling processes or packaging processes, individual semiconductor packages are separated from a wafer having a plurality of semiconductor dice. The wafer level package has extremely small dimensions combined with extremely good electrical properties.
WLP technique is an advanced packaging technology, by which the die are manufactured and tested on the wafer, and then the wafer is singulated by dicing for assembly in a surface-mount line. Because the wafer level package technique utilizes the whole wafer as one object, not utilizing a single chip or die, therefore, before performing a scribing process, packaging and testing has been accomplished; furthermore, WLP is such an advanced technique so that the process of wire bonding, die mount and under-fill can be omitted. By utilizing WLP technique, the cost and manufacturing time can be reduced, and the resulting structure of WLP can be equal to the die; therefore, this technique can meet the demands of miniaturization of electronic devices.
Though the advantages of WLP technique mentioned above, some issues still exist influencing the acceptance of WLP technique. For instance, the CTE difference (mismatching) between the materials of a structure of WLP and the mother board (PCB) becomes another critical factor to mechanical instability of the structure. A package scheme disclosed by U.S. Pat. No. 6,271,469 suffers the CTE mismatching issue. It is because the prior art uses silicon die encapsulated by molding compound. As known, the CTE of silicon material is 2.3, but the CTE of molding compound is around 40-80. The arrangement causes chip location be shifted during process due to the curing temperature of compound and dielectric layers materials are higher and the inter-connecting pads will be shifted that will causes yield and performance problem. It is difficult to return the original location during temperature cycling (it caused by the epoxy resin property if the curing Temp near/over the Tg). It means that the prior structure package can not be processed by large size, and it causes higher manufacturing cost.
Further, some technical involves the usage of die that directly formed on the upper surface of the substrate. As known, the pads of the semiconductor die will be redistributed through redistribution processes involving a redistribution layer (RDL) into a plurality of metal pads in an area array type. The build up layer will increase the size of the package. Therefore, the thickness of the package is increased. This may conflict with the demand of reducing the size of a chip.
Further, the prior art suffers complicated process to form the “Panel” type package. It needs the mold tool for encapsulation and the injection of mold material. It is unlikely to control the surface of die and compound at same level due to warp after heat curing the compound, the CMP process may be needed to polish the uneven surface. The cost is therefore increased.
Therefore, the present invention provides a fan-out wafer level packaging (FO-WLP) structure with good CTE performance and shrinkage size to overcome the aforementioned problem and also provide the better board level reliability test of temperature cycling.
The object of the present invention is to provide a fan-out WLP with excellent CTE performance and shrinkage size.
Another object of the present invention is to provide a fan-out WLP with a substrate having die receiving through-hole (window) for improving the reliability and shrinking the device size.
A structure of semiconductor device package having inter-adhesion with gap comprising: a chip with bonding pads and a sensor area embedded into a substrate with die window and inter-connecting through holes, wherein a RDL is formed over the substrate for coupling between the bonding pads and the inter-connecting through holes; a multiple rings (dam bar) formed over the substrate, the RDL, and the bonding pads area except the sensor area; an adhesive glues fill into the space of the multiple ring except the sensor area; and a transparency material bonded on the top of the multiple ring and the adhesive glues, wherein the adhesive glues adhesion between the transparency material and the multiple rings.
The RDL comprises Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy. The material of the substrate includes epoxy type FR5, FR4, BT, silicon, PCB (print circuit board) material, glass or ceramic, alloy or metal. Preferably the thickness of the multiple ring (dam bar) is over 20 um. The materials of the multiple ring (dam bar) includes the polymer modified resin, rubber resin with elastic properties. The elongation of the multiple ring is preferably over 30%. A dielectric layer is formed under the RDL, the dielectric layer includes an elastic dielectric layer, a photosensitive layer, a silicone dielectric based layer, a siloxane polymer (SINR) layer, a polyimides (PI) layer or silicone resin layer. The materials of adhesive glues include UV or thermal type with elastic property. The elongation of adhesive glues is preferably over 50%. The transparent material includes glass, crystal or high transparency plastic.
a illustrates the top view of the substrate before bonding, and after printing adhesion glue according to the present invention.
b illustrates the top view of the substrate after bonding transparency material thereon according to the present invention.
c illustrates the top view of the substrate before cutting according to the present invention.
The invention will now be described in greater detail with preferred embodiments of the invention and illustrations attached. Nevertheless, it should be recognized that the preferred embodiments of the invention is only for illustrating. Besides the preferred embodiment mentioned here, present invention can be practiced in a wide range of other embodiments besides those explicitly described, and the scope of the present invention is expressly not limited expect as specified in the accompanying claims.
The present invention discloses a structure of fan-out WLP utilizing a substrate having predetermined terminal contact metal pads 3 formed thereon and a pre-formed die (window) receiving through hole 4 formed into the substrate 2. A die is disposed within the die receiving through hole of the substrate and attached on core paste material, for example, an elastic core paste material is filled into the space between die edge and side wall of die receiving through hole of the substrate and/or under the die. A photosensitive material is coated over the die and the pre-formed substrate (includes the core paste area). Preferably, the material of the photosensitive material is formed of elastic material.
The die 6 is disposed within the die receiving through holes 4 on the substrate 2. As know, contact pads (Bonding pads) 10 are formed on the die 6. A photosensitive layer or dielectric layer 12 is formed over the die 6 and the upper surface of substrate. Pluralities of openings are formed within the dielectric layer 12 through the lithography process or exposure and develop procedure. The pluralities of openings are aligned to the contact pads (or I/O pads) 10 and the first terminal contact conductive pads 3 on the upper surface of the substrate, respectively. The RDL (redistribution layer) 14, also referred to as conductive trace 14, is formed on the dielectric layer 12 by removing selected portions of metal layer formed over the layer 12, wherein the RDL 14 keeps electrically connected with the die 6 through the I/O pads 10 and the first terminal contact conductive pads 3. The substrate 2 further comprises connecting through holes 22 formed within the substrate 2. The first terminal contact metal pads 3 are formed over the connecting through holes 22. The conductive material is re-filled into the connecting through holes 22 for electrical connection. Second terminal contact conductive pads 18 are located at the lower surface of the substrate 2 and under the connecting through holes 22 and connected to the first terminal contact conductive pads 3 of the substrate. A scribe line 28 is defined between the package units for separating each unit, optionally, there is no dielectric layer over the scribe line for better cutting quality. A protection layer 26 is employed to cover the RDL 14.
It should be noted that the die 6 including a micro lens area 60 formed on the die 6. The micro lens area 60 has a second protection layer 62 formed thereon, please refer to
The dielectric layer 12 and the core paste material 21 act as buffer area that absorbs the thermal mechanical stress between the die 6 and substrate 2 during temperature cycling due to the dielectric layer 12 has elastic property. The aforementioned structure constructs LGA type package.
Transparent base 68, for example glass cover, is formed on the protection layer 26 to cover the second protection layer 62 on the micro lens area 60, thereby creating a gap (cavity) between the glass cover 68 and micro lens area 60. The transparent base 68 may be the same as the package size (foot print) or slight bigger than the package (substrate after cutting) size. The protection layer 26, preferable the elastic materials, can be employed to adhere to the glass cover 68.
An alternative embodiment can be seen in
Preferably, the material of the substrate 2 is organic substrate likes epoxy type FR5, BT, PCB with defined through holes or Cu metal with pre etching circuit. Preferably, the CTE is the same as the one of the mother board (PCB). Preferably, the organic substrate with high Glass transition temperature (Tg) are epoxy type FR5 or BT (Bismaleimide triazine) type substrate. The Cu metal (CTE around 16) can be used also. The glass, ceramic, silicon can be used as the substrate. The elastic core paste is formed of silicone rubber, resin elastic materials.
The substrate could be round type such as wafer type, the diameter could be 200, 300 mm or higher. It could be employed for rectangular type such as panel form. The substrate 2 is pre-formed with die receiving through holes 4. The scribe line 28 is defined between the units for separating each unit. Please refer to
In one embodiment of the present invention, the dielectric layer 12 is preferably an elastic dielectric material which is made by silicone dielectric based materials comprising siloxane polymers (SINR), Dow Corning WL5000 series, and the combination thereof. In another embodiment, the dielectric layer is made by a material comprising, polyimides (PI) or silicone resin. Preferably, it is a photosensitive layer for simple process.
In one embodiment of the present invention, the elastic dielectric layer is a kind of material with CTE larger than 100 (ppm/° C.), elongation rate about 40 percent (preferably 30 percent-50 percent), and the hardness of the material is between plastic and rubber. The thickness of the elastic dielectric layer 12 depends on the stress accumulated in the RDL/dielectric layer interface during temperature cycling test.
Please refer to
The silicon die (CTE is ˜2.3) is packaged inside the package. FR5 or BT organic epoxy type material (CTE ˜16) is employed as the substrate and its CTE is the same as the PCB or Mother Board. The space (gap) between the die and the substrate is filled with filling material (prefer the elastic core paste) to absorb the thermal mechanical stress due to CTE mismatching (between die and the epoxy type FR5/BT). Further, the dielectric layers 12 include elastic materials to absorb the stress between the die pads and the PCB. The RDL metal is Cu/Au materials and the CTE is around 16 the same as the PCB and organic substrate, and the UBM 18 of contact bump is located under the terminal contact metal pads 3 of substrate. The metal land of PCB is Cu composition metal, the CTE of Cu is around 16 that is match to the one of PCB. From the description above, the present invention may provide excellent CTE (fully matching in X/Y direction) solution for the WLP.
Apparently, CTE matching issue under the build up layers (PCB and substrate) is solved by the present scheme and it provides better reliability (no thermal stress in X/Y directions for terminal pads (solder balls/bumps) on the substrate during on board level condition) and the elastic DL is employed to absorb the Z direction stress. The space (gap) between chip edge and sidewall of through holes of substrate can be used to fill the elastic dielectric materials to absorb the mechanical/thermal stress.
In one embodiment of the invention, the material of the RDL comprises Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy; the thickness of the RDL is between 2 um_and—15 um. The Ti/Cu alloy is formed by sputtering technique also as seed metal layers, and the Cu/Au or Cu/Ni/Au alloy is formed by electroplating; exploiting the electro-plating process to form the RDL can make the RDL thick enough and better mechanical properties to withstand CTE mismatching during temperature cycling. The metal pads can be Al or Cu or combination thereof. If the structure of FO-WLP utilizes SINR as the elastic dielectric layer and Cu as the RDL, according the stress analysis not shown here, the stress accumulated in the RDL/dielectric layer interface is reduced.
As shown in
The present invention includes preparing a substrate (preferably organic substrate FR4/FR5/BT) and contact metal pads are formed on top surface. The die receiving through hole is formed with the size larger than die size plus >100 um/side. The depth is the same (or about 25 um thick than) with the thickness of dice thickness.
The protection layer of micro lens is formed on the processed silicon wafer, it can improve the yield during fan-out WLP process to avoid the particle contamination. The next step is lapping the wafer by back-lapping to desired thickness. The wafer is introduced to dicing procedure to separate the dice.
Thereafter, process for the present invention includes providing a die redistribution (alignment) tool with alignment pattern formed thereon. Then, the patterned glues is printed on the tool (be used for sticking the surface of dice and substrate), followed by using pick and place fine alignment system with flip chip function to redistribute the desired dice on the tool with desired pitch. The patterned glues will stick the chips (active surface side) on the tool. Subsequently, the substrate (with die receiving through holes) is bound on the tool (stuck by patterned glues) and followed by printing elastic core paste material on the space (gap) between die and side walls of through holes of the (FR5/BT) substrate and the die back side. It is preferred to keep the surface of the core paste and the substrate at the same level. Next, the curing process is used to cure the core paste material and bonding the (glass or CCL) carrier by adhesion material. The panel bonder is used to bond the base on to the substrate and die back side. Vacuum bonding is performed, followed by separating the tool from the panel wafer.
Once the die is redistributed on the substrate (panel base), then, a clean up procedure is performed to clean the dice surface by wet and/or dry clean. Next step is to coat the dielectric materials on the surface of panel. Subsequently, lithography process is performed to open via (contact metal pads) and Al bonding pads and micro lens area or the scribe line (optional). Plasma clean step is then executed to clean the surface of via holes and Al bonding pads. Next step is to sputter Ti/Cu as seed metal layers, and then Photo Resistor (PR) is coated over the dielectric layer and seed metal layers for forming the patterns of redistributed metal layers (RDL). Then, the electro plating is processed to form Cu/Au or Cu/Ni/Au as the RDL metal, followed by stripping the PR and metal wet etching to form the RDL metal trace. Subsequently, the next step is to coat or print the top dielectric layer and to open the micro lens area or to open the scribe line (optional).
The micro lens area can be exposed after the dielectric layer is formed and after the formation of the protection layer.
The present invention provides a method to form the transparent base (glass), for example glass cover 70 of
In step 305 of
Then, in step 310, printing the ball placement or solder paste on the second contact metal 18, the heat re-flow procedure is performed to re-flow on the ball side (for BGA type). The testing is executed. Panel wafer level final testing is performed by using vertical or epoxy probe card to contact the contact metal via. After the testing, in step 315, mounting the panel (with transparent base—glass) on the blue tape frame form, the substrate 200 is sawed from the lower surface site to separate the substrate into individual units.
The next step 320 is to break the glass from the lower surface site of the substrate by a rubber puncher or roller. Then, in step 325, the packages are respectively picked and placed the package on the tray or tape and reel.
In an individual CIS (CMOS Image Sensor) package module, a sensor package with transparent base is attached on the top surfaces of a fan-out wafer level package, and a package is soldering on the Print Circuit Board by SMT process. A lens holder maybe is fixed on the printed circuit board to hold a lens. A filter, such as an IR CART, is fixed to the lens holder. Alternatively, the filter may comprise a filtering layer, for example IR filtering layer, formed upper or lower surface of the glass to act as a filter. In one embodiment, IR filtering layer comprises TiO2, light catalyzer. The glass may prevent the micro lens from particle containment. The user may use liquid or air flush to remove the particles on the glass without damaging the micron lens.
Hence, according to the present invention, the aforementioned package structure has the advantages list as follow: the BGA or LGA package structure of the present invention can prevent the micro lens from particle contamination. Moreover, CMOS/CCD image sensor package module structure may be directly cleaned to remove particle contamination. The process of manufacturing of the BGA or LGA package structure of the present invention is significantly simple.
The advantages of the present inventions are:
The process is simple for forming Panel wafer type and is easy to control the roughness of panel surface. The thickness of panel is easy to be controlled and die shift issue will be eliminated during process. The injection mold tool is omitted and warp, CMP polish process will not be introduced either. The panel wafer is easy to be processed by wafer level packaging process.
The substrate is pre-prepared with pre-form die receiving through holes, inter-connecting through holes and terminal contact metal pads (for organic substrate); the size of through hole is equal to die size plus around >100 um per/side; it can be used as stress buffer releasing area by filling the elastic core paste materials to absorb the thermal stress due to the CTE between silicon die and substrate (FR5/BT)) is difference. The packaging throughput will be increased (manufacturing cycle time was reduced) due to apply the simple build up layers on top the surface of die. The terminal pads are formed on the opposite side of the dice active surface.
The dice placement process is the same as the current process. Elastic core paste (resin, epoxy compound, silicone rubber, etc.) is refilled the space between the dice edge and the sidewall of the through holes for thermal stress releasing buffer in the present invention, then, vacuum heat curing is applied. CTE mismatching issue is overcome during panel form process (using the carrier with matching CTE that close to substrate). Only silicone dielectric material (preferably SINR) is coated on the active surface and the substrate (preferably FR45 or BT) surface. The contact pads are opened by using photo mask process only due to the dielectric layer (SINR) is photosensitive layer for opening the contacting open. The die and substrate be bonded together with carrier. The reliability for both package and board level is better than ever, especially, for the board level temperature cycling test, it was due to the CTE of substrate and PCB mother board are identical, hence, no thermal mechanical stress be applied on the solder bumps/balls; the previous failure mode (solder ball crack) during temperature cycling on board test were not obvious. The cost is low and the process is simple. It is easy to form the multi-chips package as well.
Alternatively embodiment is shown in
The die 6 is disposed within the die receiving through holes 4 on the substrate 2. As know, contact pads (Bonding pads) 10 are formed on the die 6. A photosensitive layer or first dielectric layer 12 is formed over the die 6 and the upper surface of core 2 to expose the micro-lens area. Pluralities of openings are formed within the first dielectric layer 12 through the lithography process or exposure and develop procedure. The pluralities of openings are aligned to the contact pads (or I/O pads) 10 and the first terminal contact conductive pads 3 on the upper surface of the substrate, respectively. The RDL (redistribution layer) 14, also referred to as conductive trace 14, is formed on the first dielectric layer 12 by removing selected portions of metal layer formed over the layer 12, wherein the RDL 14 keeps electrically connected with the die 6 through the I/O pads 10 and the first terminal contact conductive pads 3. The substrate 2 further comprises connecting through holes 22 formed within the substrate 2. The first terminal contact metal pads 3 are formed over the inter-connecting through holes 22. The conductive material is re-filled into the connecting through holes 22 for electrical connection. Second terminal contact conductive pads 18 are located at the lower surface of the substrate 2 and under the connecting through holes 22 and connected to the first terminal contact conductive pads 3 of the substrate. A scribe line 28 is defined between the package units for separating each unit, optionally, there is no dielectric layer over the scribe line for better cutting quality. A second dielectric layer 26 having elastic property is partially formed to cover the RDL 14. A UV glue layer 25 having elastic property is formed over the core and within the openings of the second dielectric layer 26 except the micro lens (sensor) 60 area.
It should be note that the die 6 including a micro lens area 60 formed on the die 6. The micro lens area 60 may has a second protection layer (as above embodiment) formed thereon, please refer to
Transparent cover 68, for example glass cover, is formed on the second dielectric layer 26 to expose the micro lens area 60, thereby creating a gap (cavity) 70 between the glass cover 68 and micro lens area 60. The transparent cover 68 may be the same as the package size (foot print) or slight bigger or smaller than the package (substrate after cutting) size.
The present invention includes preparing a core or substrate (preferably organic substrate, FR4/FR5/BT) and contact metal pads are formed on top surface. The die receiving through hole is formed with the size larger than die size plus >100 um/side. The depth is the same (or about 25 um thick than) with the thickness of dice thickness. A wafer lapping step is processed by back-lapping to desired thickness. The wafer is introduced to dicing procedure to separate the dice.
The process of forming the embodiment includes steps of: preparing a substrate w/die receiving window and inter-connecting through holes with contact metal pads on both side; aligning and bonding the substrate onto the die placement tools and disposing chip into die receiving window onto the die placement tools. Die attached material is formed into the gap between die edge and side wall of window and the die back side, followed by forming the DL1 (first dielectric layer) to open the bonding pads and 1st contact pads and forming RDL to couple the bonding pads to 1st contact pads. A DL2 (second dielectric layer) is formed with double ring patterns and higher thickness then DL1. It means that the second dielectric layer includes double pattern. UV glues (stencil) is printed into the space of double ring area. The nest step is to bond the transparency materials with “Panel” together by vacuum bonding with force, followed by curing the UV glues. The nest step is to cut the panel (Glass and substrate) to singulate the package.
Although preferred embodiments of the present invention have been described, it will be understood by those skilled in the art that the present invention should not be limited to the described preferred embodiments. Rather, various changes and modifications can be made within the spirit and scope of the present invention, as defined by the following claims.
The present application is a (continuation-in-part) CIP of pending U.S. application Ser. No. 11/753,006, entitled “CMOS Image Sensor Chip Scale Package with Die Receiving Through-Hole and Method of the Same” (filed May 24, 2007), which is a continuation-in-part (CIP) of co-pending U.S. application Ser. No. 11/539,215 (filed Oct. 6, 2006) and co-pending U.S. application Ser. No. 11/647,217, (filed Dec. 29, 2006). The aforementioned patent applications are commonly assigned to the assignee of the present application, and are fully incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 11753006 | May 2007 | US |
| Child | 11950921 | US | |
| Parent | 11539215 | Oct 2006 | US |
| Child | 11753006 | US | |
| Parent | 11647217 | Dec 2006 | US |
| Child | 11539215 | US |
