Patent Application
20080173792
This invention relates to a structure of image sensor, and more particularly to an image sensor module with die receiving cavity.
Digital video cameras are under development to facilitate as home appliances. Due to the quick development of the semiconductor technology, the application of the image sensor is widely used for digital still camera or movie camera. Consumers' demand has been directed to light weight, multi-function and high resolution. To meet such demand, technical levels of manufacturing camera have been improved. CCD or CMOS chip is popular device for these camera to capture image and die-bonded by means of a conductive adhesive. Typically, an electrode pad of the CCD or CMOS is wire-bonded by means of a metal wire. The wire bonding limits the size of the sensor module. The device is formed by traditional resin packaging method.
A commonly used conventional image sensor device has an array of photodiodes formed on the surface of the wafer substrate. The methods of forming such photo arrays are well known to those having ordinary skill in the art. Typically, the wafer substrate is mounted to a flat support structure and electrically connected to a plurality of electrical contacts. The substrate is electrically connected to bond pads of the support structure using wires. The structure is then enclosed in a package with a light transmissive surface that allows light to impinge on the array of photodiodes. In order to produce a flat image with relatively little distortion or little chromatic aberration requires the implementation of multiple lenses which are arranged to generate a flat optical plane. This can require many expensive optical elements.
Further, in the field of semiconductor devices, the device density is increased and the device dimension is reduced, continuously. The demand for the packaging or interconnecting techniques in such high density devices is also increased to fit the situation mentioned above. Conventionally, in the flip-chip attachment method, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out by using a solder composite material through a solder mask for producing a desired pattern of solder bumps. The function of chip package includes power distribution, signal distribution, heat dissipation, protection and support . . . and so on. As a semiconductor become more complicated, the traditional package technique, for example lead frame package, flex package, rigid package technique, can't meet the demand of producing smaller chip with high density elements on the chip. Because conventional package technologies have to divide a dice on a wafer into respective dies and then package the die respectively, therefore, these techniques are time consuming for manufacturing process. Since the chip package technique is highly influenced by the development of integrated circuits, therefore, as the size of electronics has become demanding, so does the package technique. For the reasons mentioned above, the trend of package technique is toward ball grid array (BGA), flip chip (FC-BGA), chip scale package (CSP), Wafer level package (WLP) today. “Wafer level package” is to be understood as meaning that the entire packaging and all the interconnections on the wafer as well as other processing steps are carried out before the singulation (dicing) into chips (dies). Generally, after completion of all assembling processes or packaging processes, individual semiconductor packages are separated from a wafer having a plurality of semiconductor dies. The wafer level package has extremely small-dimensions combined with extremely good electrical properties.
WLP technique is an advanced packaging technology, by which the die are manufactured and tested on the wafer, and then singulated by dicing for assembly in a surface-mount line. Because the wafer level package technique utilizes the whole wafer as one object, not utilizing a single chip or die, therefore, before performing a scribing process, packaging and testing has been accomplished; furthermore, WLP is such an advanced technique so that the process of wire bonding, die mount and under-fill can be omitted. By utilizing WLP technique, the cost and manufacturing time can be reduced, and the resulting structure of WLP can be equal to the die; therefore, this technique can meet the demands of miniaturization of electronic devices.
Therefore, the present invention provides an image sensor module to reduce the package size and cost.
The object of the present invention is to provide an image sensor module to link to MB without “connector” for BGA/LGA type.
The object of the present invention is to provide an image sensor module with PCB having cavities for super thin module application and small foot print (form factor), simple process for CIS module.
The further object of the present invention is to provide an image sensor module which is re-workable by de-soldering.
The present invention provides an image sensor module structure comprising: a substrate with a die receiving cavity formed within an upper surface of the substrate and conductive traces within the substrate; a die having a micro lens disposed within the die receiving cavity; a dielectric layer formed on the die and the substrate; a re-distribution conductive layer (RDL) formed on the dielectric layer, wherein the RDL is coupled to the die and the conductive traces, wherein the dielectric layer has an opening to expose the micro lens; a lens holder attached on the substrate, the lens holder having a lens attached an upper portion of the lens holder, a filter attached between the lens and the micro lens. The structure further comprises a passive device on the upper surface of the substrate within the lens holder.
It should be noted that an opening is formed within the dielectric layer and a top protection layer to expose the micro lens area of the die for CMOS Image Sensor (CIS). A transparent cover with coating IR filter is optionally formed over the micron lens area for protection.
The image sensor chips has been coated the protection layer (film) on the micro lens area; the protection layer (film) with the properties of water repellent and oil repellent that can away the particle contamination on the micro lens area; the thickness of protection layer (film) preferably around 0.1 um to 0.3 um and the reflection index close to air reflection index 1. The process can be executed by SOG (spin on glass) skill and it can be processed either in silicon wafer form or panel wafer form (preferably in silicon wafer form to avoid the particle contamination during further process). The materials of protection layer can be SiO2, Al2O3 or Fluoro-polymer etc.
The dielectric layer includes an elastic dielectric layer, silicone dielectric based material, BCB or PI. The silicone dielectric based material comprises siloxane polymers (SINR), silicon oxide, silicon nitride, or composites thereof. Alternatively, the dielectric layer comprises a photosensitive layer. The RDL communicates to the terminal pads downwardly the contacting via through holes structure.
The material of the substrate includes organic epoxy type FR4, FR5, BT, PCB (print circuit board), alloy or metal. The alloy includes Alloy42 (42% Ni-58% Fe) or Kovar (29% Ni-17% Co-54% Fe). Alternatively, the substrate could be glass, ceramic or silicon.
The invention will now be described in greater detail with preferred embodiments of the invention and illustrations attached. Nevertheless, it should be recognized that the preferred embodiments of the invention is only for illustrating. Besides the preferred embodiment mentioned here, present invention can be practiced in a wide range of other embodiments besides those explicitly described, and the scope of the present invention is expressly not limited expect as specified in the accompanying Claims.
The present invention discloses a structure of an image sensor module utilizing a substrate having predetermined cavity formed into the substrate. A photosensitive material is coated over the die and the pre-formed substrate. Preferably, the material of the photosensitive material is formed of elastic material. The image sensor module comprising PCB mother board with cavity for Image Sensor chip and build up layers are employed. The module with super thin structure is less than 400 um. The image sensor chips can be processed by WLP to form the protection layer on micro lens and using the build up layers to form the RDL on the module with passive components. The protection layer on micro lens may prevent the chip from particle contamination and it has water/oil repellent and the thickness of the layer is less than 0.5 um. The lens holder with IR cart can be fixed on the PCB mother board (on top the micro lens area). The high yield and high quality process can be achieved by the present invention.
The die 6 is disposed within the die receiving cavity 4 on the substrate 2 and fixed by an adhesion (die attached) material 22. As know, contact pads (Bonding pads) 28 are formed on the die 6. A photosensitive layer or dielectric layer 24 is formed over the die 6 and filling into the gap between the die 6 and the side walls of the cavity 4. Pluralities of openings are formed within the dielectric layer 24 through the lithography process or exposure and development procedure. The pluralities of openings are aligned to the contact or I/O pads 28, respectively. The RDL (re-distribution layer) 30, also referred to as metal trace, is formed on the dielectric layer 24 by removing selected portions of metal layer formed over the layer, wherein the RDL 30 keeps electrically connected with the die 6 through the I/O pads 28. A part of the material of the RDL will re-fills into the openings in the dielectric layer 24, thereby forming contact via metal over the bonding pad 28. A protection layer 26 is formed to cover the RDL 30. The aforementioned structure constructs LGA type image sensor module.
It should be noted that an opening 32 is formed within the dielectric layer 26 and the layer 24 to expose the micro lens 18 of the die 6 for CMOS Image Sensor (CIS). A protection layer 20 can be formed over the micro lens 18 on the micro lens area. The opening 32 is typically formed by photolithography process as well known to the skilled person in the art. In one case, the lower portion of the opening 32 can be opened during the formation of via opening. The upper portion of the opening 32 is formed after the deposition of the protection layer 26. Alternatively, the whole opening 32 is formed after the formation of the protection layer 26 by lithography. The image sensor chips has been coated the protection layer (film) 20 on the micro lens area; the protection layer (film) with the properties of water repellent and oil repellent that can away the particle contamination on the micro lens area. The thickness of protection layer (film) 20 is preferably around 0.1 um to 0.3 um and the reflection index close to the air reflection index 1. The process can be executed by SOG (spin on glass) skill and it can be processed either in silicon wafer form or panel wafer form (preferably in silicon wafer form to avoid the particle contamination during further process). The materials of protection layer can be SiO2, Al2O3 or Fluoro-polymer etc. Finally, a transparent cover 16 with coating IR filter is optionally formed over the micron lens 18 for protection. The transparent cover 16 is composed of glass, quartz, etc. It should be noted that the passive device 28 may be formed on the substrate and within the lens holder 12.
An alternative embodiment can be seen in
Please refer to
Alternatively, further die receiving cavity 4a is formed on the lower surface of the substrate 2 to receive the second die 40 which is DSP or MCU for auto focus, as shown in
Preferably, the material of the substrate 2 is organic substrate likes FR5, BT (Bismaleimide triazine), PCB with defined cavity or Alloy42 with pre etching circuit. The organic substrate with high Glass transition temperature (Tg) are epoxy type FR5 or BT (Bismaleimide triazine) type substrate. The Alloy42 is composed of 42% Ni and 58% Fe. Kovar can be used also, and it is composed of 29% Ni, 17% Co, 54% Fe. The glass, ceramic, silicon can be used as the substrate due to lower CTE. The dimension of the depth of the cavity 4, 4a could be larger than the thickness of the die 6, 40. It could be deeper as well.
The substrate could be round type such as wafer type, the diameter could be 200, 300 mm or higher. It could be employed for rectangular type such as panel form. The substrate 2 is formed with cavities 4 and built in circuit 8.
In one embodiment of the present invention, the dielectric layer 24 is preferably an elastic dielectric material which is made by silicone dielectric materials comprising siloxane polymers (SINR), silicon oxide, silicon nitride, and composites thereof. In another embodiment, the dielectric layer is made by a material comprising benzocyclobutene (BCB), epoxy, polyimides (PI) or resin. Preferably, it is a photosensitive layer for simple process. In one embodiment of the present invention, the elastic dielectric layer is a kind of material with CTE larger than 100 (ppm/° C.), elongation rate about 40 percent (preferably 30 percent-50 percent), and the hardness of the material is between plastic and rubber. The thickness of the elastic dielectric layer 24 depends on the stress accumulated in the RDL/dielectric layer interface during temperature cycling test.
In one embodiment of the invention, the material of the RDL comprises Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy; the thickness of the RDL is between 2 um_and—15 um. The Ti/Cu alloy is formed by sputtering technique also as seed metal layers, and the Cu/Au or CU/Ni/Au alloy is formed by electroplating; exploiting the electro-plating process to form the RDL can make the RDL thick enough to withstand CTE mismatching during temperature cycling. The metal pads 28 can be Al or Cu or combination thereof. In case of the structure of FO-WLP utilizes SINR as the elastic dielectric layer and Cu as the RDL metal. According to the stress analysis not shown here, the stress accumulated in the RDL/dielectric layer interface is reduced.
As shown in
The present invention provides the PCB (FR5/BT) with CIS die cavity. Then, the next step is to pick the CIS die (from blue tape flame) and attach the die into the cavity. Then, the attached material is cured and the die surface and metal pads is cleaned. Build up layers (RDL) process is performed to form the RDL. Then, pick and place the passive components on the PCB by picking and placing tool. Subsequently, IR reflow is used to solder PCB and passive components, followed by flux cleaning the PCB. Next is to mount the lens holder and fix the holder on the PCB, followed by module testing.
Another method further includes picking up the flip chip die (DSP or MCU) and passive components, followed by attaching the devices on the lower surface of the substrate before IR reflow is performed.
For multi-chip application, the steps include: providing the PCB (FR5/BT) with CIS die and MCU/DSP die cavities; picking the MCU die/RC and attaching on the bottom side of FR5/BT; curing and cleaning the surface and forming the build up layers; picking the CIS die and attaching on the upper side of FR5/BT; curing and cleaning the die surface and metal pads; forming Build up layers (RDL); picking and placing the passive components on the PCB; IR reflowing to solder PCB and passive components; flux cleaning the PCB; mounting the lens holder and fix the holder on the PCB; module testing.
The advantages of the present invention are:
Although preferred embodiments of the present invention have been described, it will be understood by those skilled in the art that the present invention should not be limited to the described preferred embodiments. Rather, various changes and modifications can be made within the spirit and scope of the present invention, as defined by the following Claims.
