Patent Application
20240395661
Embodiments pertain to packaging of integrated circuits (ICs). Some embodiments relate to a package substrate having a glass core.
Electronic systems often include integrated circuits (ICs) that are interconnected and packaged as a subassembly. It is desired to integrate multiple types of IC dies into a single package to create an efficient system in a package. However, as packaged electronic systems become larger due to adding more IC dies, the area form factor (e.g., X-Y dimensions) of the packages becomes larger. If the area form factor of a package becomes too large, the package can be susceptible to warping. One approach to reduce warping is to replace the organic core material of the package substrate with a glass core. But integrating system functionality into a package substrate with a glass core can increase the generated heat that needs to be removed for safe and efficient operation. It is desired to have electronic system packages that address these thermal concerns, and other technical challenges.
The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims.
To meet the demand for increased functional complexity in electronic devices, manufacturers integrate multiple types of integrated circuits (ICs) dies in a single electronic package to create an efficient electronic system in a package. The trend to package multiple IC dies into one electronic system can lead to needing large package sizes to fit all the dies. The current package technologies for electronic packaging are limited in the area form factor (e.g., X-Y dimension) that can be achieved due to warping.
The susceptibility to warping limits the number of IC dies that can be included in multi-dies assemblies and limits the size of an electronic package. Package warpage is the deviation from flatness caused by internal stress of the electronic package. Warpage can lead to different solder joint geometries between the center and the edge of the interconnected area, which can reduce the reliability. In addition, warpage can lead to solder balls bridging and interconnect opens or shorts between the solder balls which reduces the assembly yield.
Integrating increased functionality in a package substrate leads to new approaches for package architectures. One approach is to replace the organic core material of the package substrate with a glass core. The glass of the glass core may include a silicate-based glass (e.g., lithium-silicate, borosilicate, aluminum silicate, etc.). In variations, the glass panel includes a lower quality glass (e.g., glass made with soda lime), or a higher quality glass (e.g., quartz glass made with fused silica). In some examples, the glass core includes at least 70% silica.
As more functionality is integrated into electronic devices, power consumption of the devices increases. The increased power draw increases heat that needs to be moved away from the electronics package. Using glass in the substrate core as a stiffening material to reduce warpage can create challenges in managing the heat due to its reduced thermal conductivity of glass in comparison to organic cores. Using a glass core also presents an opportunity for unique architectures that enable the removal of heat using the core itself.
The electronic substrate 102 includes a top redistribution layer 130 (RDL) and a bottom RDL 132. The RDLs include multiple sublayers of conductive traces formed in an organic material. The thickness of the RDLs is exaggerated in the Figure for simplicity of the drawing. In an actual implementation, the RDLs are thin enough that the channels 108 of the core layer carry the liquid coolant close enough to the IC die 104 to absorb heat from the IC die 104. In the example of
A temperature sensor 218 monitors the temperature of the electronic device 100. A control unit 220 includes electronic circuits to control opening and closing of a control valve 222 based on the sensed temperature of the electronic device 100. When the temperature reaches or exceeds a threshold temperature, the control unit 220 opens the control valve 222 to circulate the coolant to transfer heat away from the electronic device 100. Heat exchanger 224 cools the heated coolant pulled away from the electronic device. A heat spreader 226 may be attached to the IC die of the electronic device 100 that can contact a heat sink to further dissipate heat into air above the electronic device. The control unit 220 may close the control valve 222 when the sensed temperature of the electronic device 100 drops below a specified temperature lower than the threshold temperature.
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The TGVs 138 contact the conductive traces of the RDLs. The top RDL 130, the TGVs 138, and the bottom RDL 132 can provide electrical continuity between the IC dies and the PCB. The top row of channels 108 is closer to the top RDL and fluid flowing in the channels can be used to remove heat from the IC dies attached to the top RDL 130. The bottom row of channels 108 is closer to the electronic components attached to the bottom RDL and the bottom row of channels can be used to remove heat from the electronic components attached to the bottom RDL 132.
The methods, devices, and systems described herein provide improved thermal management in electronic device that have a substrate that includes a glass core. Heat from the electronic packaging is removed by electrically non-conductive fluid flowing in channels formed in the glass core. The channels can provide a path for heat extraction that can be used alone or in addition to traditional heat spreaders and heat sinks. An example of an electronic system using assemblies with electronic packaging as described in the present disclosure is included to show an example of a higher level device application
In one embodiment, processor 610 has one or more processing cores 612 and 612N, where N is a positive integer and 612N represents the Nth processor core inside processor 610. In one embodiment, system 600 includes multiple processors including 610 and 605, where processor 605 has logic similar or identical to the logic of processor 610. In some embodiments, processing core 612 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In some embodiments, processor 610 has a cache memory 616 to cache instructions and/or data for system 600. Cache memory 616 may be organized into a hierarchal structure including one or more levels of cache memory.
In some embodiments, processor 610 includes a memory controller 614, which is operable to perform functions that enable the processor 610 to access and communicate with memory 630 that includes a volatile memory 632 and/or a non-volatile memory 634. In some embodiments, processor 610 is coupled with memory 630 and chipset 620. Processor 610 may also be coupled to a wireless antenna 678 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, an interface for wireless antenna 678 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
In some embodiments, volatile memory 632 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 634 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.
Memory 630 stores information and instructions to be executed by processor 610. In one embodiment, memory 630 may also store temporary variables or other intermediate information while processor 610 is executing instructions. In the illustrated embodiment, chipset 620 connects with processor 610 via Point-to-Point (PtP or P-P) interfaces 617 and 622. Chipset 620 enables processor 610 to connect to other elements in system 600. In some embodiments of the example system, interfaces 617 and 622 operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.
In some embodiments, chipset 620 is operable to communicate with processor 610, 605N, display device 640, and other devices 672, 676, 674, 660, 662, 664, 666, 677, etc. Buses 650 and 655 may be interconnected together via a bus bridge 672. Chipset 620 connects to one or more buses 650 and 655 that interconnect various elements 674, 660, 662, 664, and 666. Chipset 620 may also be coupled to a wireless antenna 678 to communicate with any device configured to transmit and/or receive wireless signals. Chipset 620 connects to display device 640 via interface (I/F) 626. Display 640 may be, for example, a touchscreen, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments, processor 610 and chipset 620 are merged into a single SOC. In one embodiment, chipset 620 couples with (e.g., via interface 624) a non-volatile memory 660, a mass storage medium 662, a keyboard/mouse 664, and a network interface 666 via I/F 624 and/or I/F 626, I/O devices 674, smart TV 676, consumer electronics 677 (e.g., PDA, Smart Phone, Tablet, etc.).
In one embodiment, mass storage device 662 includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 666 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
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The methods, devices, and systems described herein provide improved thermal management in electronic systems such as the example system in
Example 1 includes subject matter (such as an electronic device) comprising an electronic package substrate. The electronic package substrate includes a glass core layer having a first surface and a second surface; multiple channels within the glass core layer between the first surface and the second surface; and a first redistribution layer (RDL). The RDL includes multiple sub-layers of conductive traces formed in an organic material, and a first surface of the RDL contacts the first surface of the glass core layer.
In Example 2, the subject matter of Example 1 optionally includes a glass core layer that includes multiple glass sub-layers bonded together.
In Example 3, the subject matter of one or both of Examples 1 and 2 optionally include a glass core layer that includes multiple rows of channels in the glass core layer.
In Example 4, the subject matter of Example 3 optionally includes a first row of channels having a first width, and a second row of channels having a second width different from the first width.
In Example 5, the subject matter of one or both of Examples 3 and 4 optionally includes a second RDL contacting the second surface of the glass core layer. The multiple rows of channels include a first row of channels arranged closer to the first RDL than the second RDL and a second row of channels arranged closer to the second RDL than the first RDL.
In Example 6, the subject matter of one or any combination of Examples 1-5 optionally includes a glass core layer that includes at least one through glass via (TGV) arranged between two channels of the multiple channels.
In Example 7, the subject matter of Example 6 optionally includes a second RDL including multiple sublayers of conductive traces formed in an organic material. A first surface of the second RDL contacts the second surface of the glass core layer, and the at least one TGV provides electrical continuity between a conductive trace of the first RDL and a conductive trace of the second RDL.
In Example 8, the subject matter of one or any combination of Examples 1-7 optionally includes a cross section of a channel of the multiple channels having one of a square shape or a rectangular shape.
In Example 9, the subject matter of one or any combination of Examples 1-7 optionally includes at least one surface of a channel of the multiple channels being a curved surface.
Example 10 includes subject matter (such as an electronic system) comprising an electronic package substrate including a glass core layer including multiple microfluidic channels within the glass core layer between a first surface of the glass core layer and a second surface of the glass core layer; at least one integrated circuit (IC) mounted on the electronic package substrate; and a manifold coupled to the electronic package substrate and configured to provide fluid to the microfluidic channels.
In Example 11, the subject matter of Example 10 optionally includes an electronic package substrate that includes a first redistribution layer (RDL) arranged between the first surface of the glass core layer and the IC, and a through glass via (TGV). The first RDL includes multiple sublayers of conductive traces formed in an organic material. The TGV is arranged in the glass core layer adjacent to a first microfluidic channel of the multiple microfluidic channels. The first RDL provides electrical continuity between the TGV and the IC.
In Example 12, the subject matter of Example 10 optionally includes a first redistribution layer (RDL) arranged between the first surface of the glass core layer and the IC, and a second RDL arranged on the second surface of the glass core layer. The first and second RDL include multiple sublayers of conductive traces formed in an organic material. The glass core layer includes multiple rows of microfluidic channels, including a first row of microfluidic channels closer to the first RDL than the second RDL and a second row of microfluidic channels closer to the second RDL than the first RDL.
In Example 13, the subject matter of Example 12 optionally includes the first row of microfluidic channels having a first width, and the second row of microfluidic channels having a second width different from the first width.
In Example 14, the subject matter of one or both of Examples 12 and 13 optionally includes a printed circuit board (PCB). The electronic package substrate includes a through glass via (TGV) arranged in the glass core layer adjacent to a first microfluidic channel of the multiple microfluidic channels, and the second RDL provides electrical continuity between the TGV and the PCB.
Example 15 includes subject matter (such as a method of forming an electronic package substrate) or can optionally be combined with one or any combination of Examples 1-14 to include such subject matter, comprising forming multiple trenches in a first substrate sub-layer, wherein the multiple trenches are formed in a first surface of the substrate sub-layer; bonding a second substrate sub-layer to the first surface of the first substrate sub-layer to cover the multiple trenches to form a substrate core layer having multiple channels within the substrate core layer; and forming a first redistribution layer (RDL) on a first surface of the glass core layer, wherein the first RDL includes an organic material and multiple sublayers of conductive traces formed in the organic material.
In Example 16, the subject matter of Example 15 optionally includes the first and second substrate sub-layers are first and second glass sub-layers, and the substrate core layer is a glass core layer. The method further includes forming multiple trenches in a first surface of a third glass sub-layer and bonding the first surface of the third glass sub-layer to a second surface of the first glass sub-layer to form a monolithic glass core layer including a second layer of multiple channels in the glass core layer.
In Example 17, the subject matter of Example 16 optionally includes forming the multiple trenches of the third glass sub-layer to have at least one of a different width or depth than the multiple trenches of the third glass sub-layer, and the channels of the second layer of multiple channels have at least one of a different width or depth than the channels of the first layer of multiple channels.
In Example 18, the subject matter of one or both of Examples 16 and 17 optionally includes forming a second RDL on a second surface of the glass core layer. The second RDL includes multiple sublayers of conductive traces formed in an organic material, and wherein the first layer of multiple channels is closer to the first RDL than the second RDL, and the second layer of multiple channels is closer to the second RDL than the first RDL.
In Example 19, the subject matter of Example 18 optionally includes attaching at least one integrated circuit (IC) die on the first RDL and attaching the second RDL to a printed circuit board.
In Example 20, the subject matter of one or any combination of Examples 15-19 optionally includes the first and second substrate sub-layers are first and second glass sub-layers, and the substrate core layer is a glass core layer. The method further includes forming at least one through glass via (TGV) in the glass core layer that extends through the first and second glass sub-layers, and the at least one TGV contacts at least one conductive trace of the first RDL.
Throughout this specification, plural instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are illustrated and described as separate operations, one or more of the individual operations may be performed concurrently, and nothing requires that the operations be performed in the order illustrated. Structures and functionality presented as separate components in example configurations may be implemented as a combined structure or component. Similarly, structures and functionality presented as a single component may be implemented as separate components. These and other variations, modifications, additions, and improvements fall within the scope of the subject matter herein.
Although an overview of the inventive subject matter has been described with reference to specific example embodiments, various modifications and changes may be made to these embodiments without departing from the broader scope of embodiments of the present disclosure. Such embodiments of the inventive subject matter may be referred to herein, individually or collectively, by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single disclosure or inventive concept if more than one is, in fact, disclosed.
The embodiments illustrated herein are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed. Other embodiments may be used and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. The Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.
As used herein, the term “or” may be construed in either an inclusive or exclusive sense. Moreover, plural instances may be provided for resources, operations, or structures described herein as a single instance. Additionally, boundaries between various resources, operations, modules, engines, and data stores are somewhat arbitrary, and particular operations are illustrated in a context of specific illustrative configurations. Other allocations of functionality are envisioned and may fall within a scope of various embodiments of the present disclosure. In general, structures and functionality presented as separate resources in the example configurations may be implemented as a combined structure or resource. Similarly, structures and functionality presented as a single resource may be implemented as separate resources. These and other variations, modifications, additions, and improvements fall within a scope of embodiments of the present disclosure as represented by the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
The foregoing description, for the purpose of explanation, has been described with reference to specific example embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the possible example embodiments to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The example embodiments were chosen and described in order to best explain the principles involved and their practical applications, to thereby enable others skilled in the art to best utilize the various example embodiments with various modifications as are suited to the particular use contemplated.
It will also be understood that, although the terms “first,” “second,” and so forth may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first contact could be termed a second contact, and, similarly, a second contact could be termed a first contact, without departing from the scope of the present example embodiments. The first contact and the second contact are both contacts, but they are not the same contact.
The terminology used in the description of the example embodiments herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used in the description of the example embodiments and the appended examples, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
As used herein, the term “if” may be construed to mean “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context. Similarly, the phrase “if it is determined” or “if [a stated condition or event] is detected” may be construed to mean “upon determining” or “in response to determining” or “upon detecting [the stated condition or event]” or “in response to detecting [the stated condition or event],” depending on the context.
