Claims
- 1. An integrated circuit chip comprising a bitline architecture, the integrated circuit chip produced by the steps of:a) selecting a hybrid photoresist composition having a negative tone response and a positive tone response to exposure to actinic radiation, wherein the negative tone response predominates over the positive tone response at less than a first exposure dose D1 and at greater than a second exposure dose D2, wherein the positive tone response predominates over the negative tone response between D1 and D2, and wherein D1 is less than D2; b) depositing a layer of the selected photoresist material onto a surface, thereby forming a film; c) exposing first portions of the film to a dose less than D1, second portions of the film to a range of intermediate doses DINT, such that DINT is less than or equal to D2 and DINT is greater than or equal to D1, and third portions of the film to a dose greater than D2; and d) developing the film, wherein at least one line and at least one space are formed.
- 2. The integrated circuit chip of claim 1, the method further comprising the step of baking the film after exposing and before developing the film.
- 3. The integrated circuit chip of claim 2, the method further comprising the step of blanket exposing the film after the exposure step and before the baking step.
- 4. The integrated circuit chip of claim 2, the method further comprising the step of blanket exposing the film after the baking step and before the developing step.
- 5. The integrated circuit chip of claim 2, the method further comprising the step of image-wise exposing the film after the baking step and before the developing step.
- 6. The integrated circuit chip of claim 11, wherein changes of the exposusre dose have no effect on the size of the at least one space.
- 7. The integrated circuit chip of claim 1, the method further comprising selecting a reticle having a frequency of lines and spaces, wherein the frequency of the lines and spaces is doubled.
- 8. The integrated circuit chip of claim 1, wherein post exposure bake increases the negative tone response more than the positive tone response.
- 9. The integrated circuit chip of claim 1, wherein the positive tone response is faster than the negative tone response.
- 10. The integrated circuit chip of claim 1, the method further comprising the step of selecting the positive tone component to be less sensitive than the negative tone component to post expose bake conditions.
- 11. The integrated circuit chip of claim 1, wherein the step of selecting a hybrid photoresist composition further comprises selecting a solubility inhibitor such that a spacewidth decreases as the concentration of the solubility inhibitor increases.
- 12. The integrated circuit chip of claim 1, the method further comprising a step of utilizing a gray-scale filter during the exposure step, thereby creating areas of intermediate exposure.
RELATED APPLICATIONS
This application is a division of the earlier patent application by Hakey et al. entitled “FREQUENCY DOUBLING HYBRID PHOTORESIST HAVING NEGATIVE AND POSITIVE TONE COMPONENTS AND METHOD OF PREPARING THE SAME”, Ser. No. 08/715,287, filed Sep. 16, 1996 now U.S. Pat. No. 6,114,082, that is incorporated herein by reference. This application is a sister application to co-pending U.S. Patent Application by Holmes et al. entitled “LOW ‘K’ FACTOR HYBRID PHOTORESIST”, Ser. No. 08/715,288, filed Sep. 16, 1996, that is likewise incorporated herein by reference.
US Referenced Citations (8)
Foreign Referenced Citations (1)
Number |
Date |
Country |
5-297597 |
Nov 1993 |
JP |