Patent Application
20080308896
The present invention relates to an integrated circuit device comprising a semiconductor substrate and at least one gate electrode structure on said semiconductor substrate and to a corresponding method of fabrication.
It is possible to decrease the size of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) by introducing a metal electrode into the gate electrode of a MOSFET. One example for such a gate electrode is a Metal Inserted Poly Stack (MIPS). A MIPS comprises a gate dielectric base formed on a semiconductor substrate and a thin metal layer formed on the gate dielectric base. Typically, tantalum carbo oxynitride (Ta(CO)N) is utilized as material for said metal layer. The Ta(CO)N layer can be deposited on the gate electrode base by a Chemical Vapor Deposition (CVD) with a layer thickness of about 10 nm or less.
A p-type MIPS with a metal electrode of Ta(CO)N can achieve a work function about 4.8 eV. However, it is possible to have a p-metal electrode with a higher work function about 5.0 eV. Another disadvantage of the MIPS with a metal electrode of Ta(CO)N is the relatively high resistivity of the Ta(CO)N layer.
Aspects of the invention are listed in claims 1, 9, 17 and 22.
Exemplary embodiments of the present invention are illustrated in the drawings and are explained in more detail in the description below.
In the figures:
In
On the surface of the semiconductor substrate 10 a first insulating layer 12 of silicon dioxide is formed. If the semiconductor substrate 10 consists of silicon, the first insulating layer 12 can be formed by increasing the temperature of the semiconductor substrate 10 and exposing the semiconductor substrate 10 to an oxygen atmosphere simultaneously. Alternatively the first insulating layer 12 can be formed on the semiconductor substrate by a Physical Vapor Deposition (PVD) Process, by a Chemical Vapor Deposition (CVD) Process or by wet chemical oxidation.
In the next step of the fabrication method a second insulating layer of a high-K dielectric material is formed on the first insulating layer. Such a high-K dielectric material can be selected from the group of HfSiO, HfO, ZrSiO, ZrO, HfZrO, HfZrSiO, HfAlO, ZrAlO, HfREO or ZrREO, where RE is a rare earth element of the group Y, Sc, La, Nd, Pr, Dy, Er, Yb, Lu, Tb, Sm, Gd, Ho or Ce. The use of HfREO, ZrREO, HfAlO or ZrAlO can additionally modify the work function of the fabricated gate electrode structure. In an alternative implementation different dielectrics are used for N- and P-channel transistors on the same substrate.
In
After the deposition of the Nb(CO)N layer 16 the percentage of carbon is between 0 to 20%, the percentage of oxygen is between 2 to 30%, and the percentage of nitrogen is between 5 to 60% within the Nb(CO)N layer 16. It is possible to increase the oxygen content within the Nb(CO)N layer 16, as compounds with oxygen have a higher electro-negativity than compounds with nitrogen or carbon. However, as pure oxides of niobium are dielectric, additional carbon and nitrogen atoms are required. For the deposition of the Nb(CO)N layer 16, similar precursors can be used as for the deposition of a tantalum containing layer.
Compared to a tantalum layer for a gate electrode structure, for the Nb(CO)N layer 16 a dielectric niobium phase corresponding to the Ta3N5 phase does not exist. Therefore, all compounds of niobium with sufficient N or C content are expected to be conductive. Also, the niobium compounds should have a slightly higher work function than tantalum compounds due to the higher electro-negativity of niobium compared to tantalum.
As an alternative to the Nb(CO)N layer 16, the integrated circuit device of
In
On the second insulating layer 14 a metal layer 16 has been formed of a combination of niobium, vanadium, chromium, tungsten and/or molybdenum together with carbon, oxygen and nitrogen. This metal layer 16 serves as a metal electrode for the p-MOS structure. In this metal layer 16 the percentage of carbon is between 0 to 20%, the percentage of oxygen is between 2 to 30% and the percentage of nitrogen is between 5 to 60%. This combination of the materials carbon, oxygen and nitrogen with at least one of the metals niobium, vanadium, chromium, tungsten and/or molybdenum can be achieved by the fabrication method explained in the
On the surface of the metal layer 16 a first capping layer 20 is deposited. This first capping layer 20 contains at least one of the following materials: Mo, MoN, W, WN, TiN, or TaN. On the first capping layer 20 a second capping layer 22 of polysilicone is formed.
As the second capping layer consists of polysilicone, there is the risk that oxygen or nitrogen could diffuse from the metal layer 14 into the second capping layer 22. Therefore, the first capping layer 20 is inserted between the metal layer 16 and the second capping layer 22 of polysilicone to prevent the removal of oxygen or nitrogen from the metal layer 16 into the second capping layer 22.
In
The n-MOS structure has the same two insulating layers 12 and 14 as the p-MOS structure. Also, on the surface of the second insulating layer 14 a metal layer 16b of the material niobium, vanadium, chromium, tungsten and/or molybdenum has been deposited. However, compared to the metal layer 16a of the p-MOS structure, the metal layer 16b has the same or a decreased layer thickness. Also, the polysilicone capping layer 22 has been formed in touch with the surface of the metal layer 16b of the n-MOS structure. Thus the n-MOS structure lacks the metallic capping layer 20 of W.
The capping layer on the metal layer 16a or 16b can increase the work function of a p-MOS. Also, a capping layer of TiN, TaN, Mo, MoN, WN and/or W can prevent the reduction of the metal by the polysilicone. Thus, in the example of
