Patent Application
20240413112
Various features related to integrated circuit devices.
Electrical connections exist at each level of a system hierarchy. This system hierarchy includes interconnection of devices and/or components at a lowest system level all the way up to system level interconnections at the highest level. For example, interconnect layers can connect different devices/component together on an integrated circuit. As integrated circuits become more complex, more interconnect layers are used to provide the electrical connections between the devices/components. More recently, the number of interconnect levels for circuitry has substantially increased due to the large number of devices/components that are now interconnected in a modern electronic device. The increased number of interconnect levels involves more intricate fabrication processes.
State-of-the-art mobile application devices demand a small form factor, low cost, a tight power budget, and high electrical performance. Increasingly small form factors combined with increasingly complex circuits leads to challenges with interconnecting components of a device. For example, a device can include multiple integrated circuit devices that are interconnected to operate in conjunction with one another. In such devices, smaller integrated circuit devices have less area that can be used to provide electrical interconnects, leading to challenges with forming reliable, densely packed interconnects.
Various features related to integrated circuit devices.
One example provides an integrated device that includes a die having a contact pad and a solder cap electrically connected to the contact pad by a multi-layer interconnect pillar. The multi-layer interconnect pillar includes a base reinforcement layer, a cap reinforcement layer, and a solder layer disposed between the base reinforcement layer and the cap reinforcement layer.
Another example provides a device that includes a substrate and a die. The substrate includes an interface and the die includes a contact pad. The device also includes a multi-layer interconnect pillar disposed between the substrate and the die and electrically connected to the contact pad. The multi-layer interconnect pillar includes a base reinforcement layer, a cap reinforcement layer, and a solder layer disposed between the base reinforcement layer and the cap reinforcement layer. A solder cap is electrically connected to the multi-layer interconnect pillar and to the interface.
Another example provides a method that includes forming a base reinforcement layer of a multi-layer interconnect pillar, where the base reinforcement layer is electrically connected to a contact pad of a die. The method also includes forming a first solder layer of the multi-layer interconnect pillar, where the first solder layer is disposed over the base reinforcement layer. The method includes forming a cap reinforcement layer of the multi-layer interconnect pillar, where the cap reinforcement layer is electrically connected to the contact pad by at least the base reinforcement layer and the first solder layer. The method also includes forming a solder cap of the multi-layer interconnect pillar, where the solder cap is disposed over the cap reinforcement layer.
Various features, aspects, and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings.
In the following description, specific details are given to provide a thorough understanding of the various aspects of the disclosure. However, it will be understood by one of ordinary skill in the art that the aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams in order to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the aspects of the disclosure.
Particular aspects of the present disclosure are described below with reference to the drawings. In the description, common features are designated by common reference numbers. As used herein, various terminology is used for the purpose of describing particular implementations only and is not intended to be limiting of implementations. For example, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, some features described herein are singular in some implementations and plural in other implementations. For ease of reference herein, such features are generally introduced as “one or more” features and are subsequently referred to in the singular or optional plural (as indicated by “(s)”) unless aspects related to multiple of the features are being described.
As used herein, the terms “comprise.” “comprises,” and “comprising” may be used interchangeably with “include,” “includes,” or “including.” As used herein, “exemplary” indicates an example, an implementation, and/or an aspect, and should not be construed as limiting or as indicating a preference or a preferred implementation. As used herein, an ordinal term (e.g., “first,” “second,” “third,” etc.) used to modify an element, such as a structure, a component, an operation, etc., does not by itself indicate any priority or order of the element with respect to another element, but rather merely distinguishes the element from another element having a same name (but for use of the ordinal term). As used herein, the term “set” refers to one or more of a particular element, and the term “plurality” refers to multiple (e.g., two or more) of a particular element.
Improvements in manufacturing technology and demand for lower cost and more capable electronic devices has led to increasing complexity of integrated circuits (ICs). Often, more complex ICs have more complex interconnection schemes to enable interaction between ICs of a device. The number of interconnect levels for circuitry has substantially increased due to the large number of devices that are now interconnected in a state-of-the-art mobile application device.
These interconnections include back-end-of-line (BEOL) interconnect layers, which may refer to the conductive interconnect layers for electrically coupling to front-end-of-line (FEOL) active devices of an IC. The various BEOL interconnect layers are formed at corresponding BEOL interconnect levels, in which lower BEOL interconnect levels generally use thinner metal layers relative to upper BEOL interconnect levels. The BEOL interconnect layers may electrically couple to middle-of-line (MOL) interconnect layers, which interconnect to the FEOL active devices of an IC.
As used herein, the term “layer” includes a film, and is not construed as indicating a vertical or horizontal thickness unless otherwise stated. As used herein, the term “chiplet” may refer to an integrated circuit block, a functional circuit block, or other like circuit block specifically designed to work with one or more other chiplets to form a larger, more complex chiplet architecture.
Aspects of the present disclosure are directed to multi-layer interconnect pillars that enable electrical interconnection between two or more devices. The multi-layer interconnect pillars are configured to enable close packing of electrical interconnections (e.g., a small pitch). The multi-layer interconnect pillars include alternating reinforcement layers and solder layers. This arrangement is dimensionally stable (e.g., does not spread to cause short circuits when pitch distance between electrical interconnections is small) and limits stress introduced into the devices due to rigidity of the electrical interconnections.
In the example illustrated in
In the detailed example illustrated in
The integrated device 100 also includes a plurality of pillar bumps 132 that form a grid or array to enable electrical interconnection to another device (e.g., another die, a package substrate, or a printed circuit board). In a particular aspect, each of the pillar bumps 132 includes a multi-layer interconnect pillar 120 and a solder cap 130. Each of the solder caps 130 is electrically connected to a respective one of the contact pads 106 via a corresponding multi-layer interconnect pillar 120. As described in more detail below, the multi-layer interconnect pillars 120 are configured to enable electrical interconnection of the device 100 and another device, such as a printed circuit board, a package substrate, another die, etc. In particular, the multi-layer interconnect pillars 120 are configured to be pliable while also allowing close spacing of the pillar bumps 132. For example, a pitch 114 of the pillar bumps 132 can be less than or equal to 150 micrometers (such as less than or equal to 130 micrometers) enabling dense packing of electrical connections between the device 100 and a packaging substrate.
Using conventional solder bumps (i.e., without interconnect pillars) at such a fine pitch 114 is not feasible because when such solder bumps are heated sufficiently to reflow (e.g., to form bonds to another device), the solder bumps tend to merge, causing short circuits. An additional, and distinct, problem with using conventional solder bumps at such a fine pitch 114 is that the size of the solder bumps is so small that a stand-off distance between the die 102 and the device it is coupled to may not allow an underfill material to be adequately spread, leading to uneven stresses and insufficient support. Copper posts are sometimes used with solder bumps to mitigate some of these concerns. For example, copper posts can provide additional stand-off distance between the die 102 and a packaging substrate so that underfill material can be properly distributed. However, copper posts are much less pliable than solder bumps. As a result, when copper posts are used, various layers of the die 102 and/or a device to which the die 102 is coupled via the copper post can be damaged by stresses (e.g., thermally induced stresses due to differences in coefficients of thermal expansion) due, in part, to the rigidity of the copper post. One example of damage that can occur when copper posts are used is due to so called “extremely low k (ELK)” stress, which can cause cracking in brittle dielectric layers (e.g., layers with low dielectric constant (k) values) of the die 102. In contrast to conventional solder bumps and conventional copper posts, the multi-layer interconnect pillars 120 of the pillar bumps 132 include one or more solder layers disposed between reinforcement layers. In this stacking arrangement, the solder layers make the multi-layer interconnect pillars 120 less rigid (e.g., more compliant) than conventional copper pillars, which reduces damage such as cracking of ELK layer(s), while the reinforcement layers make the multi-layer interconnect pillars 120 more dimensionally stable than conventional solder bumps, thus enabling a fine pitch 114 between the pillar bumps 132.
As illustrated in
In some implementations, one or more under bump metallization (UBM) layers 112 are coupled to and disposed between the contact pad 106 and the base reinforcement layer 122. For example, the UBM layer(s) 112 can include seed layers and/or adhesion layers that facilitate plating of the base reinforcement layer 122.
The material used to form the reinforcement layers is selected to have a higher melting point than a solder used to form the solder layer 124 and the solder cap 130. As an example, the solder can include a lead-free solder, such as a tin/silver solder, and the reinforcement layers can include nickel, cobalt, or alloys that include either. An additional consideration in selecting the material used to form the reinforcement layers is formation of intermetallic compounds (IMCs) by diffusion of the material of a reinforcement layer into the solder. Such IMCs are generally more brittle than the solder alone and may also have other undesirable mechanical and/or electrical properties. As one example, nickel in contact with the solder cap 130 can form IMCs within the solder cap 130, and such IMCs can lead to failure of a joint between the solder cap 130 and another device and/or can make wafer-level probe testing more difficult (leading to increased manufacturing costs). To reduce the formation of IMCs between the cap reinforcement layer 126 and the solder cap 130, a barrier layer (e.g., a barrier layer 210 of
The thicknesses of the layers of the multi-layer interconnect pillar 120 are selected to provide a target stand-off distance between the die 102 and the device or substrate to which the die 102 is coupled via the solder cap 130 while retaining structural stability of the multi-layer interconnect pillar 120 and providing desired pliability characteristics of the multi-layer interconnect pillar 120. For example, a maximum thickness of the solder layer 124 (or solder layers, if more than one is used) may be limited by structural stability concerns since reflowing the solder cap 130 can also cause softening of the solder layer 124. Tests have demonstrated that a solder layer 124 with a thickness between 5 micrometers to 20 micrometers can be used without losing structural stability of the multi-layer interconnect pillar 120 during typical manufacturing and test conditions, such as heating during wafer-level probe testing or reflowing of the solder caps 130 to attach the die 102 to another device. Further, reinforcement layers can have thicknesses in the range of 1 micrometer to 5 micrometers, as one example. If the desired stand-off height is too large for use of a three-layer stack, as illustrated in
In
Although the example illustrated in
Although the example illustrated in
In
In
The copper pillar 302 of either of
As explained above, copper pillars are more rigid than a stacked arrangement of reinforcement layers and solder layers, such as described with reference to
Although the examples illustrated in
A technical benefit of the multi-layer interconnect pillars 120, 220, or 320 is that the multi-layer interconnect pillars 120, 220, or 320 provide electrical interconnections between the die and another device (e.g., in a flip chip arrangement), where the electrical interconnections are compliant so as to reduce (relative to copper pillars) interconnection stresses, such as ELK stresses. An additional technical benefit is that the multi-layer interconnect pillars 120, 220, or 320 provide enough stand-off distance between the die 102 and the other device such that underfill material or mold compound can be properly distributed. A further technical benefit is that the multi-layer interconnect pillars 120, 220, or 320 can be positioned much closer together than traditional solder bumps. In some implementations, each of the above-described technical benefits are provided. In other implementations, fewer than all of the above-described technical benefits are provided.
In some implementations, fabricating a device (e.g., any of the devices 100. 200, or 300) includes several processes.
It should be noted that the sequence of
Stage 1 of
Stage 2 illustrates a state after a photoresist layer 414 has been applied to the die 400 (or a wafer including the die 400) and patterned to form openings 416 (including an opening 416A and an opening 416B) to enable access to the contact pads 406 and/or to the UBM layer 412. In a particular example, a deposition process, a spin-on process, or a similar process can be used to apply the photoresist layer 414, and the photoresist layer 414 can subsequently be selectively cured by exposing portions of the photoresist layer 414 to light (e.g., using a mask). Uncured portions of the photoresist layer 414 can be removed to form the openings 416. In some implementations, other patterned layers can be used in addition to or instead of the photoresist layer 414 to define the openings 416. For example, a heat curable polymer layer can be cured on the die 400 and subsequently patterned by laser ablation. As another example, a polymer layer can be applied and patterned at the same time, such as via an imprint lithography technique.
Stage 3 illustrates a state after a base reinforcement layer 420 has been formed. For example, forming the base reinforcement layer 420 can include electroplating the die 400 (or a wafer including the die 400) to deposit nickel, cobalt, or an alloy that includes either or both nickel and cobalt, on to a portion of the die 400 exposed via each opening 416. To illustrate, after Stage 2 of
Stage 4 illustrates a state after a solder layer 422 has been formed on the base reinforcement layer 420. For example, forming the solder layer 422 can include electroplating the die 400 (or a wafer including the die 400) to deposit multiple metals of a lead-free solder alloy (e.g., a tin/silver alloy) on to the base reinforcement layer 420 exposed via each opening 416. To illustrate, in
Stage 5 illustrates a state after one or more intermediate reinforcement layers (e.g., intermediate reinforcement layers 424 and 428), one or more additional solder layers (e.g., additional solder layers 426 and 430), and a cap reinforcement layer 432 have been formed to define a multi-layer interconnect pillar 440. The intermediate reinforcement layer(s) 424, 428, and the cap reinforcement layer 432 can be formed using operations similar to those used to form the base reinforcement layer 420 (as described with reference to Stage 3 of
In the example illustrated at Stage 5 of
Stage 6 illustrates a state after a barrier layer 442 has been formed on the cap reinforcement layer 432 of the multi-layer interconnect pillar 440. For example, forming the barrier layer 442 can include electroplating the die 400 (or a wafer including the die 400) to deposit a material to reduce formation of IMCs between the cap reinforcement layer 432 and a solder cap formed on the multi-layer interconnect pillar 440. The barrier layer 442 can include copper. As one example, after Stage 5 of
The barrier layers 442 are optional and are omitted in some implementations. For example, if IMCs formed by the solder and the cap reinforcement layer 432 do not interfere with other process operations, such as wafer-level probe and inspection, then the barrier layer 442 can be omitted.
Stage 7 illustrates a state after a solder layer 444 has been formed on the barrier layer 442 and/or on the multi-layer interconnect pillar 440. The solder layer 444 can be formed using one or more metal deposition operations, as described above with reference to formation of the solder layer 422 in Stage 4 of
Stage 8 illustrates a state after completion of formation of a device 450 that includes solder caps 452 electrically connected to contact pads 406 of a die 400 via respective multi-layer interconnect pillars 440 (and optional barrier layers 442). For example, after Stage 7 of
Formation of the device 450 is complete at Stage 8. For example, the device 450 can include or correspond to the device 100 of
Stage 9 illustrates a state after formation of a device 470 that includes the device 450 coupled to another device 460 using the solder caps 452. For example, the device 450 can be flipped (relative to the orientation illustrated in Stage 8) and positioned such that each of the solder caps 452 is in contact with a respective electrical interface 462 (including an electrical interface 462A and an electrical interface 462B) of the device 460. In this example, the solder caps 452 can be heated to reflow and subsequently cooled to form a physical and electrical connection to the electrical interfaces 462. The electrical interfaces 462 can include, for example, contact pads, conductive lines, or other electrical interconnection interfaces.
The device 460 can include or correspond to a package substrate, a printed circuit board, or another packaged or unpackaged die. As one example, the device 450 and the device 460 are chiplets, which in Stage 9, are arranged and interconnected as a 3D stacked integrated circuit (IC). Arranging chiplets in this manner can provide various benefits as compared to providing the same functional circuitry in one monolithic chip. For example, each chiplet is smaller than a monolithic die including all of the same functional circuit blocks would be. Since yield loss in IC manufacturing tends to increase as the die size increases, using smaller dies can reduce yield loss (i.e., increase yield) of the IC manufacturing process. Another benefit is that the chiplets can be fabricated in different locations and/or by different manufacturers, and in some cases, using different fabrication technologies (e.g., different fabrication technology nodes). As an example, one die of a chiplet-based integrated device (e.g., the device 470) can include components (e.g., interconnects, transistors, etc.) that have a first minimum size, and another die of the chiplet-based integrated device (e.g., the device 470) can include components (e.g., interconnects, transistors, etc.) that have a second minimum size, where the second minimum size is greater than the first minimum size. In contrast, all of the circuitry of a monolithic die is fabricated using the same fabrication technologies and equipment. As a result, when manufacturing a monolithic die, the entire die may be subject to the tightest manufacturing constraint of the most complex component of the monolithic die. However, when using chiplets, different chiplets can be manufactured using different fabrication technologies (e.g., different fabrication technology nodes), and only the chiplet or chiplets that include the most complex components are subjected to the tightest manufacturing constraints. In this arrangement, chiplets fabricated using less expensive and/or higher yield fabrication technologies can be integrated with chiplets fabricated using more expensive and/or lower yield fabrication technologies to form a stacked IC (e.g., the device 470), resulting in overall savings. Still further, in some cases, as technology improves, the design of a chiplet can be changed. Chiplet stacking allows such new chiplet designs to be integrated with older chiplet designs to form stacked IC devices, which improves manufacturing flexibility and reduces design costs.
In the example illustrated in Stage 9 of
The example illustrated in Stage 9 also shows a material 472 (e.g., an underfill material or mold compound) disposed between the device 450 and the device 460. The material 472 supports structural integrity of the device 470. The additional stand-off height provided by the multi-layer interconnect pillars 440 (relative to using solder bumps alone) facilitates relatively even distribution of the material 472 between the device 450 and the device 460. For example, the material 472 can include an epoxy or another polymer that is applied (e.g., injected between the device 450 and the device 460) as a viscous fluid, and subsequently hardened. In this example, the stand-off height provided by the multi-layer interconnect pillars 440 allows the viscous fluid to flow evenly between and around the multi-layer interconnect pillars 440 to reduce gaps and/or bubbles in the material 472.
It should be noted that the sequence of
Stage 1 of
Stage 2 illustrates a state after a photoresist layer 514 has been applied to the die 500 (or a wafer including the die 500) and patterned to form openings 516 (including an opening 516A and an opening 516B) to enable access to the contact pads 506 and/or to the UBM layers 512. In a particular example, a deposition process, a spin-on process, or a similar process can be used to apply the photoresist layer 514, and the photoresist layer 514 can subsequently be selectively cured by exposing portions of the photoresist layer 514 to light (e.g., using a mask). Uncured portions of the photoresist layer 514 can be removed to form the openings 516. In some implementations, other patterned layers can be used in addition to or instead of the photoresist layer 514 to define the openings 516. For example, a heat curable polymer layer can be cured on the die 500 and subsequently patterned by laser ablation. As another example, a polymer layer can be applied and patterned at the same time, such as via an imprint lithography technique.
Stage 3 illustrates a state after copper pillars 518 have been formed. For example, forming a copper pillar 518 can include electroplating the die 500 (or a wafer including the die 500) to deposit copper on a portion of the die 500 exposed via each opening 516. To illustrate, after Stage 2 of
Stage 4 illustrates a state after base reinforcement layers 520 have been formed. For example, forming the base reinforcement layer 520 can include electroplating the die 500 (or a wafer including the die 500) to deposit nickel, cobalt, or an alloy that includes either or both nickel and cobalt, on the copper pillars 518. To illustrate, after Stage 3 of
Stage 5 illustrates a state after solder layers 522 have been formed on the base reinforcement layers 520. For example, forming a solder layer 522 can include electroplating the die 500 (or a wafer including the die 500) to deposit multiple metals of a lead-free solder alloy (e.g., a tin/silver alloy) on to a base reinforcement layer 520 exposed via each opening 516. To illustrate, in
Stage 6 illustrates a state after cap reinforcement layers 532 have been formed to define multi-layer interconnect pillars 540. In some implementations, one or more intermediate reinforcement layers and one or more additional solder layers are formed before the cap reinforcement layers 532 are formed, as described with reference to Stage 5 of
Stage 7 illustrates a state after barrier layers 542 have been formed on the cap reinforcement layers 532 of the multi-layer interconnect pillars 540. For example, forming a barrier layer 542 can include electroplating the die 500 (or a wafer including the die 500) to deposit a material to reduce formation of IMCs between a cap reinforcement layer 532 and a solder cap formed on a multi-layer interconnect pillar 540. The barrier layers 542 can include copper. As one example, after Stage 6 of
The barrier layers 542 are optional and are omitted in some implementations. For example, if the IMCs formed by the solder and the cap reinforcement layer 532 will not interfere with other process steps, such as wafer-level probe or inspection, then the barrier layer 542 can be omitted.
The operations associated with Stages 3-6 of
Stage 8 illustrates a state after solder layers 544 have been formed on the barrier layers 542 and/or on the multi-layer interconnect pillars 540. A solder layer 544 can be formed using one or more metal deposition operations, as described above with reference to Stage 5 of
Stage 9 illustrates a state after completion of formation of a device 550 that includes solder caps 552 (including a solder cap 552A and a solder cap 552B) electrically connected to contact pads 506 of a die 500 via respective multi-layer interconnect pillars 540 (and optional barrier layers 542). For example, after Stage 8 of
Formation of the device 550 is complete at Stage 9. For example, the device 550 can include or correspond to the device 100 of
Stage 10 illustrates a state after formation of a device 570 that includes the device 550 coupled to another device 560 using the solder caps 552. For example, the device 550 can be flipped (relative to the orientation illustrated in Stage 9) and positioned such that each of the solder caps 552 is in contact with a respective electrical interface 562 (including an electrical interface 562A and an electrical interface 562B) of the device 560. In this example, the solder caps 554 can be heated to reflow and subsequently cooled to form a physical and electrical connection to the electrical interfaces 562. The electrical interfaces 562 can include, for example, contact pads, conductive lines, or other electrical interconnection interfaces.
The device 560 can include or correspond to a package substrate, a printed circuit board, or another packaged or unpackaged die. As one example, the device 550 and the device 560 are chiplets, which in Stage 10, are arranged and interconnected as a 3D stacked IC. A material 572 (e.g., an underfill material or a mold compound) may be disposed between the device 550 and the device 560.
In the example illustrated in Stage 10 of
In some implementations, fabricating a device that includes a multi-layer interconnect pillar includes several processes.
It should be noted that the method 600 of
The method 600 includes, at 602, forming a base reinforcement layer of a multi-layer interconnect pillar, where the base reinforcement layer is electrically connected to a contact pad of a die. For example, the base reinforcement layer can be deposited onto the contact pad of the die. In some implementations, before forming the base reinforcement layer, the method 600 includes forming one or more UBM layers, where at least one of the one or more UBM layers contacts the contact pad. In such implementations, the base reinforcement layer can be deposited onto the UBM layers. Stage 3 of
The method 600 includes, at 604, forming a first solder layer of the multi-layer interconnect pillar, where the first solder layer is disposed over the base reinforcement layer. For example, the first solder layer may include a lead-free solder, such as a tin/silver alloy, which can be deposited on the base reinforcement layer using one or more electroplating operations or other metallization operations. Stage 4 of
The method 600 includes, at 606, forming a cap reinforcement layer of the multi-layer interconnect pillar, where the cap reinforcement layer is electrically connected to the contact pad by at least the base reinforcement layer and the first solder layer. For example, the cap reinforcement layer can be deposited onto the first solder layer. Stage 6 of
In other examples, one or more additional reinforcement layers between the base reinforcement layer and the cap reinforcement layer and one or more additional solder layers disposed between adjacent reinforcement layers are formed before the cap reinforcement layer is formed. Stage 5 of
In some implementations, the method 600 includes forming a copper pillar on a stack that includes at least the base reinforcement layer, the first solder layer, and the cap reinforcement layer (e.g., as illustrated for the multi-layer interconnect pillar 320B of
The method 600 includes, at 608, forming a solder cap of the multi-layer interconnect pillar, where the solder cap is disposed over the cap reinforcement layer. For example, the solder cap can be formed by deposition of a solder layer over the cap reinforcement layer (or the copper pillar when the copper pillar is over the cap reinforcement layer). The solder layer can subsequently be heated to form the solder cap. Stage 8 of
In some implementations, before forming the solder cap, the method 600 includes forming one or more barrier layers, where at least one of the one or more barrier layers contacts the cap reinforcement layer. For example, a layer of a barrier metal (e.g., copper) can be deposited on the cap reinforcement layer to form the barrier layer. In this example, the solder cap is subsequently formed on the barrier layer. Stage 6 of
In a particular example of the method 600, a photoresist layer is formed on the die (or a wafer that includes the die) and the photoresist layer is patterned to form opening(s) exposing the contact pad(s). In this example, the base reinforcement layer, the first solder layer, the cap reinforcement layer, and a solder layer of the solder cap are formed in the opening(s). In this example, after forming at least the base reinforcement layer, the first solder layer, the cap reinforcement layer, and the solder layer of the solder cap in the opening(s), the method 600 includes stripping the photoresist layer from the die (or the wafer) to expose the multi-layer interconnect pillar. Stage 2 of
In some implementations, after forming at least the base reinforcement layer, the first solder layer, the cap reinforcement layer, and the solder cap, the method 600 includes applying heat to the multi-layer interconnect pillar sufficient to soften the solder cap and one or more solder layers of the multi-layer interconnect pillar. In such implementations, the reinforcement layers limit deformation of the multi-layer interconnect pillar due to heating (e.g., due to softening of the solder).
In some implementations, the method 600 also includes, after forming at least the base reinforcement layer, the first solder layer, the cap reinforcement layer, and the solder cap, attaching the solder cap to another device to electrically connect the other device and the contact pad. For example, the solder cap and the multi-layer interconnect structure including at least the base reinforcement layer, the first solder layer, and the cap reinforcement layer can provide an electrical connection between the contact pad and an electrical interface of the other device. Stage 9 of
One or more of the components, processes, features, and/or functions illustrated in
It is noted that the figures in the disclosure may represent actual representations and/or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and/or transistors. In some instances, the figures may not be to scale. In some instances, for purpose of clarity, not all components and/or parts may be shown. In some instances, the position, the location, the sizes, and/or the shapes of various parts and/or components in the figures may be exemplary. In some implementations, various components and/or parts in the figures may be optional.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to the direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically touches object B, and object B touches object C. then objects A and C may still be considered coupled to one another—even if they do not directly physically touch each other. An object A, that is coupled to an object B, may be coupled to at least part of object B. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that an electrical current (e.g., signal, power, ground) may travel between the two objects. Two objects that are electrically coupled may or may not have an electrical current traveling between the two objects. The use of the terms “first”, “second”, “third” and “fourth” (and/or anything above fourth) is arbitrary. Any of the components described may be the first component, the second component, the third component or the fourth component. For example, a component that is referred to a second component, may be the first component, the second component, the third component or the fourth component. The terms “encapsulate”, “encapsulating” and/or any derivation means that the object may partially encapsulate or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A component that is located on top may be located over a component that is located on a bottom. A top component may be considered a bottom component, and vice versa. As described in the disclosure, a first component that is located “over” a second component may mean that the first component is located above or below the second component, depending on how a bottom or top is arbitrarily defined. In another example, a first component may be located over (e.g., above) a first surface of the second component, and a third component may be located over (e.g., below) a second surface of the second component, where the second surface is opposite to the first surface. It is further noted that the term “over” as used in the present application in the context of one component located over another component, may be used to mean a component that is on another component and/or in another component (e.g., on a surface of a component or embedded in a component). Thus, for example, a first component that is over the second component may mean that (1) the first component is over the second component, but not directly touching the second component, (2) the first component is on (e.g., on a surface of) the second component, and/or (3) the first component is in (e.g., embedded in) the second component. A first component that is located “in” a second component may be partially located in the second component or completely located in the second component. A value that is about X-XX, may mean a value that is between X and XX, inclusive of X and XX. The value(s) between X and XX may be discrete or continuous. The term “about ‘value X’”, or “approximately value X”, as used in the disclosure means within 10 percent of the ‘value X’. For example, a value of about 1 or approximately 1, would mean a value in a range of 0.9-1.1. A “plurality” of components may include all the possible components or only some of the components from all of the possible components. For example, if a device includes ten components, the use of the term “the plurality of components” may refer to all ten components or only some of the components from the ten components.
In some implementations, an interconnect is an element or component of a device or package that allows or facilitates an electrical connection between two points, elements and/or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and/or a UBM layer/interconnect. In some implementations, an interconnect may include an electrically conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground and/or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and/or sequences for forming the interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating, and/or a plating process may be used to form the interconnects.
Also, it is noted that various disclosures contained herein may be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed.
In the following, further examples are described to facilitate the understanding of the disclosure.
According to Example 1, an integrated device includes a die having a contact pad; and a solder cap electrically connected to the contact pad by a multi-layer interconnect pillar, the multi-layer interconnect pillar includes a base reinforcement layer; a cap reinforcement layer; and a solder layer disposed between the base reinforcement layer and the cap reinforcement layer.
Example 2 includes the integrated device of Example 1 and further includes one or more UBM layers coupled to and disposed between the contact pad and the multi-layer interconnect pillar.
Example 3 includes the integrated device of Example 1 or Example 2 and further includes a barrier layer coupled to and disposed between the solder cap and the multi-layer interconnect pillar.
Example 4 includes the integrated device of Example 3, wherein a material of the solder cap forms IMCs with a material of the barrier layer at a first rate, wherein the material of the solder cap forms IMCs with a material of the cap reinforcement layer at a second rate, and wherein the first rate is greater than the second rate.
Example 5 includes the integrated device of Example 3 or Example 4, wherein the barrier layer comprises copper.
Example 6 includes the integrated device of any of Examples 1 to 5, wherein the multi-layer interconnect pillar further comprises an intermediate reinforcement layer disposed between the solder layer and the base reinforcement layer and a second solder layer disposed between the intermediate reinforcement layer and the cap reinforcement layer.
Example 7 includes the integrated device of any of Examples 1 to 6, wherein the multi-layer interconnect pillar further comprises one or more intermediate reinforcement layers disposed between the cap reinforcement layer and the base reinforcement layer and one or more additional solder layers, wherein solder layers and reinforcement layers alternate in the multi-layer interconnect pillar.
Example 8 includes the integrated device of Example 7, wherein each of the one or more additional solder layers has a thickness between 5 micrometers to 20 micrometers.
Example 9 includes the integrated device of any of Examples 1 to 8, wherein the multi-layer interconnect pillar further comprises a copper pillar between the base reinforcement layer and the contact pad.
Example 10 includes the integrated device of Example 9, wherein the copper pillar has a height of 10 micrometers to 40 micrometers.
Example 11 includes the integrated device of any of Examples 1 to 10, wherein the contact pad is one of a plurality of contact pads of the die, and the solder cap is one of a plurality of solder caps, wherein each of the plurality of solder caps is electrically connected to a respective one of the plurality of contact pads, and wherein a pitch of the plurality of solder caps is less than 150 micrometers.
Example 12 includes the integrated device of Example 11, wherein the pitch is less than 130 micrometers.
Example 13 includes the integrated device of any of Examples 1 to 12, wherein the cap reinforcement layer and the base reinforcement layer comprise nickel.
Example 14 includes the integrated device of any of Examples 1 to 13, wherein the cap reinforcement layer and the base reinforcement layer comprise cobalt.
According to Example 15, a method includes forming a base reinforcement layer of a multi-layer interconnect pillar, where the base reinforcement layer is electrically connected to a contact pad of a die; forming a first solder layer of the multi-layer interconnect pillar, wherein the first solder layer is disposed over the base reinforcement layer; forming a cap reinforcement layer of the multi-layer interconnect pillar, wherein the cap reinforcement layer is electrically connected to the contact pad by at least the base reinforcement layer and the first solder layer; and forming a solder cap of the multi-layer interconnect pillar, wherein the solder cap is disposed over the cap reinforcement layer.
Example 16 includes the method of Example 15 and further includes forming one or more additional reinforcement layers between the base reinforcement layer and the cap reinforcement layer; and forming one or more additional solder layers disposed between adjacent reinforcement layers.
Example 17 includes the method of Example 15 or Example 16 and further includes forming a copper pillar of the multi-layer interconnect pillar, wherein the copper pillar is disposed over the contact pad.
Example 18 includes the method of any of Examples 15 to 17 and further includes, before forming the base reinforcement layer, forming one or more UBM layers, wherein at least one of the one or more UBM layers contacts the contact pad.
Example 19 includes the method of any of Examples 15 to 18 and further includes, before forming the solder cap, forming one or more barrier layers, wherein at least one of the one or more barrier layers contacts the cap reinforcement layer.
Example 20 includes the method of any of Examples 15 to 19 and further includes forming a photoresist layer on the die; and patterning the photoresist layer to form an opening exposing the contact pad, wherein the base reinforcement layer, the first solder layer, the cap reinforcement layer, and a solder layer of the solder cap are formed in the opening.
Example 21 includes the method of Example 20 and further includes, after forming at least the base reinforcement layer, the first solder layer, the cap reinforcement layer, and the solder layer of the solder cap in the opening, stripping the photoresist layer from the die to expose the multi-layer interconnect pillar.
Example 22 includes the method of any of Examples 15 to 21 and further includes, after forming at least the base reinforcement layer, the first solder layer, the cap reinforcement layer, and the solder cap, applying heat to the multi-layer interconnect pillar sufficient to soften the solder cap and one or more solder layers of the multi-layer interconnect pillar, wherein reinforcement layers of the multi-layer interconnect pillar limit deformation of the multi-layer interconnect pillar due to heating.
Example 23 includes the method of any of Examples 15 to 22 and further includes, after forming at least the base reinforcement layer, the first solder layer, the cap reinforcement layer, and the solder cap, attaching the solder cap to another device to electrically connect the other device and the contact pad.
According to Example 24, a device includes a substrate including an interface; a die including a contact pad; a multi-layer interconnect pillar disposed between the substrate and the die and electrically connected to the contact pad, the multi-layer interconnect pillar includes a base reinforcement layer; a cap reinforcement layer; and a solder layer disposed between the base reinforcement layer and the cap reinforcement layer. The device also includes a solder cap electrically connected to the multi-layer interconnect pillar and to the interface.
Example 25 includes the device of Example 24 and further includes one or more UBM layers coupled to and disposed between the contact pad and to the multi-layer interconnect pillar.
Example 26 includes the device of Example 24 or Example 25 and further includes a barrier layer coupled to and disposed between the solder cap and the multi-layer interconnect pillar.
Example 27 includes the device of Example 26, wherein a material of the solder cap forms IMCs with a material of the barrier layer at a first rate, wherein the material of the solder cap forms IMCs with a material of the cap reinforcement layer at a second rate, and wherein the first rate is greater than the second rate.
Example 28 includes the device of Example 26 or Example 27, wherein the barrier layer comprises copper.
Example 29 includes the device of any of Examples 24 to 28, wherein the multi-layer interconnect pillar further comprises an intermediate reinforcement layer disposed between the solder layer and the base reinforcement layer; and a second solder layer disposed between the intermediate reinforcement layer and the cap reinforcement layer.
Example 30 includes the device of any of Examples 24 to 29, wherein the multi-layer interconnect pillar further comprises one or more intermediate reinforcement layers disposed between the cap reinforcement layer and the base reinforcement layer; and one or more additional solder layers, wherein solder layers and reinforcement layers alternate in the multi-layer interconnect pillar.
Example 31 includes the device of Example 30, wherein each of the one or more additional solder layers has a thickness between 5 micrometers to 20 micrometers.
Example 32 includes the device of any of Examples 24 to 31, wherein the multi-layer interconnect pillar further comprises a copper pillar between the base reinforcement layer and the contact pad.
Example 33 includes the device of Example 32, wherein the copper pillar has a height of 10 micrometers to 40 micrometers.
Example 34 includes the device of any of Examples 24 to 33, wherein the solder cap is one of a plurality of solder caps electrically connecting the die and the substrate, and wherein a pitch of the plurality of solder caps is less than 150 micrometers.
Example 35 includes the device of Example 34, wherein the pitch is less than 130 micrometers.
Example 36 includes the device of any of Examples 24 to 35, wherein the cap reinforcement layer and the base reinforcement layer comprise nickel.
Example 37 includes the device of any of Examples 24 to 36, wherein the cap reinforcement layer and the base reinforcement layer comprise cobalt.
The various features of the disclosure described herein can be implemented in different systems without departing from the disclosure. It should be noted that the foregoing aspects of the disclosure are merely examples and are not to be construed as limiting the disclosure. The description of the aspects of the present disclosure is intended to be illustrative, and not to limit the scope of the claims. As such, the present teachings can be readily applied to other types of apparatuses and many alternatives, modifications, and variations will be apparent to those skilled in the art.
