Patent Application
20080316793
One type of memory is resistive memory. Resistive memory utilizes the Tesistance value of a memory element to store one or more bits of data. For example, a memory element programmed to have a high resistance value may represent a logic “1” data bit value and a memory element programmed to have a low resistance value may represent a logic “0” data bit value. Typically, the resistance value of the memory element is switched electrically by applying a voltage pulse or a current pulse to the memory element.
One type of resistive memory is phase change memory. Phase change memory uses a phase change material in the resistive memory element. The phase change material exhibits at least two different states. The states of the phase change material may be referred to as the amorphous state and the crystalline state, where the amorphous state involves a more disordered atomic structure and the crystalline state involves a more ordered lattice. The amorphous state usually exhibits higher resistivity than the crystalline state. Also, some phase change materials exhibit multiple crystalline states, e.g. a face-centered cubic (FCC) state and a hexagonal closest packing (HCP) state, which have different resistivities and may be used to store bits of data. In the following description, the amorphous state generally refers to the state having the higher resistivity and the crystalline state generally refers to the state having the lower resistivity.
Phase changes in the phase change materials may be induced reversibly. In this way, the memory may change from the amorphous state to the crystalline state and from the crystalline state to the amorphous state in response to temperature changes. The temperature changes of the phase change material may be achieved by driving current through the phase change material itself or by driving current through a resistive heater adjacent the phase change material. With both of these methods, controllable heating of the phase change material causes controllable phase change within the phase change material.
A phase change memory including a memory array having a plurality of memory cells that are made of phase change material may be programmed to store data utilizing the memory states of the phase change material. One way to read and write data in such a phase change memory device is to control a current and/or a voltage pulse that is applied to the phase change material. The level of current and/or voltage generally corresponds to the temperature induced within the phase change material in each memory cell.
To achieve higher density phase change memories, a phase change memory cell can store multiple bits of data. Multi-bit storage in a phase change memory cell can be achieved by programming the phase change material to have intermediate resistance values or states, where the multi-bit or multilevel phase change memory cell can be written to more than two states. If the phase change memory cell is programmed to one of three different resistance levels, 1.5 bits of data per cell can be stored. If the phase change memory cell is programmed to one of four different resistance levels, two bits of data per cell can be stored, and so on. To program a phase change memory cell to an intermediate resistance value, the amount of crystalline material coexisting with amorphous material and hence the cell resistance is controlled via a suitable write strategy.
One type of phase change memory cell is a mushroom or heater memory cell including phase change material between a bottom electrode and a top electrode. A contact couples the bottom electrode to an access device, such as a transistor or diode. The bottom electrode should heat the phase change material during programming without heating the contact or the access device.
For these and other reasons, there is a need for the present invention.
One embodiment provides an integrated circuit. The integrated circuit includes a first electrode, a second electrode, and resistivity changing material between the first electrode and the second electrode. The integrated circuit includes a contact contacting a bottom and a first sidewall portion of the first electrode.
The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
Each phase change memory cell 104 includes a bottom electrode that extends or is recessed into a bottom contact. The bottom electrode is cylindrical in shape, tapered, or has another suitable shape. In one embodiment, the bottom electrode is a ring electrode, which includes a dielectric material core. The 5 bottom electrode provides an increased contact area to the bottom contact compared to bottom electrodes that do not extend into the bottom contact. The increased contact area provides improved memory cell reliability due to less heat dissipation at the interface between the bottom electrode and the bottom contact.
As used herein, the term “electrically coupled” is not meant to mean that the elements must be directly coupled together and intervening elements may be provided between the “electrically coupled” elements.
Memory array 101 is electrically coupled to write circuit 124 through signal path 125, to controller 120 through signal path 121, and to sense circuit 126 through signal path 127. Controller 120 is electrically coupled to write circuit 124 through signal path 128 and to sense circuit 126 through signal path 130. Each phase change memory cell 104 is electrically coupled to a word line 110, a bit line 112, and a common or ground 114. Phase change memory cell 104a is electrically coupled to bit line 112a, word line 110a, and common or ground 114, and phase change memory cell 104b is electrically coupled to bit line 112a, word line 110b, and common or ground 114. Phase change memory cell 104c is electrically coupled to bit line 112b, word line 110a, and common or ground 114, and phase change memory cell 104d is electrically coupled to bit line 112b, word line 110b, and common or ground 114.
Each phase change memory cell 104 includes a phase change element 106 and a transistor 108. While transistor 108 is a field-effect transistor (FET) in the illustrated embodiment, in other embodiments, transistor 108 can be another suitable device such as a bipolar transistor or a 3D transistor structure. In other embodiments, a diode-like structure may be used in place of transistor 108. Phase change memory cell 104a includes phase change element 106a and transistor 108a. One side of phase change element 106a is electrically coupled to bit line 112a, and the other side of phase change element 106a is electrically coupled to one side of the source-drain path of transistor 108a. The other side of the source-drain path of transistor 108a is electrically coupled to common or ground 114. The gate of transistor 108a is electrically coupled to word line 110a.
Phase change memory cell 104b includes phase change element 106b and transistor 108b. One side of phase change element 106b is electrically coupled to bit line 112a, and the other side of phase change element 106b is electrically coupled to one side of the source-drain path of transistor 108b. The other side of the source-drain path of transistor 108b is electrically coupled to common or ground 114. The gate of transistor 108b is electrically coupled to word line 110b.
Phase change memory cell 104c includes phase change element 106c and transistor 108c. One side of phase change element 106c is electrically coupled to bit line 112b and the other side of phase change element 106c is electrically coupled to one side of the source-drain path of transistor 108c. The other side of the source-drain path of transistor 108c is electrically coupled to common or ground 114. The gate of transistor 108c is electrically coupled to word line 110a.
Phase change memory cell 104d includes phase change element 106d and transistor 108d. One side of phase change element 106d is electrically coupled to bit line 112b and the other side of phase change element 106d is electrically coupled to one side of the source-drain path of transistor 108d. The other side of the source-drain path of transistor 108d is electrically coupled to common or ground 114. The gate of transistor 108d is electrically coupled to word line 110b.
In another embodiment, each phase change element 106 is electrically coupled to a common or ground 114 and each transistor 108 is electrically coupled to a bit line 112. For example, for phase change memory cell 104a, one side of phase change element 106a is electrically coupled to common or ground 114. The other side of phase change element 106a is electrically coupled to one side of the source-drain path of transistor 108a. The other side of the source-drain path of transistor 108a is electrically coupled to bit line 112a.
Each phase change element 106 comprises a phase change material that may be made up of a variety of materials in accordance with the present invention. Generally, chalcogenide alloys that contain one or more elements from group VI of the periodic table are useful as such materials. In one embodiment, the phase change material of phase change element 106 is made up of a chalcogenide compound material, such as GeSbTe, SbTe, GeTe or AgInSbTe. In another embodiment, the phase change material is chalcogen free, such as GeSb, GaSb, InSb, or GeGaInSb. In other embodiments, the phase change material is made up of any suitable material including one or more of the elements Ge, Sb, Te, Ga, As, In, Se, and S.
Each phase change element 106 may be changed from an amorphous state to a crystalline state or from a crystalline state to an amorphous state under the influence of temperature change. The amount of crystalline material coexisting with amorphous material in the phase change material of one of the phase change elements 106a-106d thereby defmes two or more states for storing data within memory device 100. In the amorphous state, a phase change material exhibits significantly higher resistivity than in the crystalline state. Therefore, the two or more states of phase change elements 106a-106d differ in their electrical resistivity. In one embodiment, the two or more states are two states and a binary system is used, wherein the two states are assigned bit values of “0” and “1”. In another embodiment, the two or more states can be three states and a ternary system can be used, wherein the three states are assigned bit values of “0”, “1”, and “2”. In another embodiment, the two or more states are four states that can be assigned multi-bit values, such as “00”, “01”, “10”, and “11”. In other embodiments, the two or more states can be any suitable number of states in the phase change material of a phase change element.
Controller 120 includes a microprocessor, microcontroller, or other suitable logic circuitry for controlling the operation of memory device 100. Controller 120 controls read and write operations of memory device 100 including the application of control and data signals to memory array 101 through write circuit 124 and sense circuit 126. In one embodiment, write circuit 124 provides voltage pulses through signal path 125 and bit lines 112 to memory cells 104 to program the memory cells. In other embodiments, write circuit 124 provides current pulses through signal path 125 and bit lines 112 to memory cells 104 to program the memory cells.
Sense circuit 126 reads each of the two or more states of memory cells 104 through bit lines 112 and signal path 127. In one embodiment, to read the resistance of one of the memory cells 104, sense circuit 126 provides current that flows through one of the memory cells 104. Sense circuit 126 then reads the voltage across that one of the memory cells 104. In one embodiment, sense circuit 126 provides voltage across one of the memory cells 104 and reads the current that flows through that one of the memory cells 104. In one embodiment, write circuit 124 provides voltage across one of the memory cells 104 and sense circuit 126 reads the current that flows through that one of the memory cells 104. In one embodiment, write circuit 124 provides current that flows through one of the memory cells 104 and sense circuit 126 reads the voltage across that one of the memory cells 104.
During a set operation of phase change memory cell 104a, one or more set current or voltage pulses are selectively enabled by write circuit 124 and sent through bit line 112a to phase change element 106a thereby heating phase change element 106a above its crystallization temperature (but usually below its melting temperature) with word line 110a selected to activate transistor 108a. In this way, phase change element 106a reaches its crystalline state or a partially crystalline and partially amorphous state during this set operation.
During a reset operation of phase change memory cell 104a, a reset current or voltage pulse is selectively enabled by write circuit 124 and sent through bit line 112a to phase change element 106a. The reset current or voltage quickly heats phase change element 106a above its melting temperature. After the current or voltage pulse is turned off, phase change element 106a quickly quench cools into the amorphous state or a partially amorphous and partially crystalline state. Phase change memory cells 104b-104d and other phase change memory cells 104 in memory array 100 are set and reset similarly to phase change memory cell 104a using a similar current or voltage pulse.
Bottom contact 202a includes TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, Cu, WN, C, or other suitable contact material. Bottom contact 202a contacts the bottom and sidewalls of first portion 216a of bottom electrode 204a. In one embodiment, the height of first portion 216a is greater than 10% of the critical dimension or diameter of bottom electrode 204a. In another embodiment, the height of first portion 216a is greater than 50% of the critical dimension or diameter of bottom electrode 204a. In one embodiment, bottom electrode 204a has a sublithographic cross-sectional width. Bottom electrode 204a includes TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, WN, C, Ru, or other suitable electrode material.
The top of second portion 214 of bottom electrode 204a contacts the bottom of phase change material storage location 206. Phase change material storage location 206 has a greater cross-sectional width than bottom electrode 204a. Phase change material storage location 206 provides a storage location for storing one or more bits of data. The active or phase change region in phase change material storage location 206 is at the interface between phase change material storage location 206 and bottom electrode 204a. In one embodiment, phase change material storage location 206 includes two or more layers of phase change material or a graded composition of two or more phase change materials.
The top phase change material storage location 206 contacts the bottom of top electrode 208. In one embodiment, top electrode 208 has the same cross-sectional width as phase change material storage location 206. Top electrode 208 includes TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TIAlN, WN, C, or other suitable electrode material. The top of top electrode 208 contacts the bottom of top contact 210. Top contact 210 includes TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, WN, C, or other suitable contact material. Top contact 210, top electrode 208, phase change material storage location 206, second portion 214 of bottom electrode 204a, and bottom contact 202a are laterally surrounded by dielectric material 212. Dielectric material 212 includes SiO2, SiOx, SiN, fluorinated silica glass (FSG), boro-phosphorous silicate glass (BPSG), boro-silicate glass (BSG), or other suitable dielectric material.
The current path through memory element 200a is from top contact 210 through top electrode 208, phase change material storage location 206, and bottom electrode 204a to bottom contact 202a. In another embodiment, the current path is reversed. During operation, current or voltage pulses are applied between top contact 210 and bottom contact 202a to program phase change element 200a. During a set operation of phase change element 200a, a set current or voltage pulse is selectively enabled by write circuit 124 and sent through a bit line to top contact 210. From top contact 210, the set current or voltage pulse passes through top electrode 208 and phase change material storage location 206 thereby heating the phase change material above its crystallization temperature (but usually below its melting temperature). In this way, the phase change material reaches a crystalline state or a partially crystalline and partially amorphous state during the set operation.
During a reset operation of phase change element 200a, a reset current or voltage pulse is selectively enabled by write circuit 124 and sent through a bit line to top contact 210. From top contact 210, the reset current or voltage pulse passes through top electrode 208 and phase change material storage location 206. The reset current or voltage quickly heats the phase change material above its melting temperature. After the current or voltage pulse is turned off, the phase change material quickly quench cools into an amorphous state or a partially amorphous and partially crystalline state.
The following
The following
A dielectric material, such as SiO2, SiOx, SiN, FSG, BPSG, BSG, or other suitable dielectric material is deposited over first electrode material layer 203b to provide second dielectric material layer 218a. Second dielectric material layer 218a is deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique.
An electrode material, such as TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, Cu, WN, C, or other suitable electrode material is deposited over phase change material layer 206a to provide second electrode material layer 208a. Second electrode material layer 208a is deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique.
A dielectric material, such as SiO2, SiOx, SiN, FSG, BPSG, BSG, or other suitable dielectric material is then deposited over exposed portions of top electrode 208, phase change material storage location 206, and first dielectric material layer 212c to provide a dielectric material layer. The dielectric material layer is deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. The dielectric material layer is then planarized using CMP or another suitable planarization technique. Top contact 210 is then formed over top electrode 208 using additional deposition and etching processes to provide phase change element 200a-200c as previously described and illustrated with reference to
Embodiments provide a heater phase change memory cell including a bottom electrode that extends or is recessed into a bottom contact. In one embodiment, the portion of the bottom electrode that extends or is recessed into the bottom contact is tapered. In one embodiment, the bottom electrode includes a ring electrode. The interface area between the bottom electrode and the bottom contact is increased over typical heater memory cells thereby improving the reliability of the memory cells.
While the specific embodiments described herein substantially focused on using phase change memory elements, the present invention can be applied to any suitable type of resistive or resistivity changing memory elements.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
