Claims
- 1. A method for fabricating integrated circuits, comprising the steps of:
- providing a plurality of wafers in a vacuum sealable wafer carrier, said wafer carrier comprising a bell jar shape cover which is vacuum sealable to a body thereof, said bell jar shape cover being removable from said body in a direction which is substantially normal to the plane of wafers supported in said body;
- placing said wafer carrier into a vacuum sealable load lock upper chamber having a partial floor with an aperture therein and a stage positioned below said aperture in close proximity to said floor;
- pumping down said load lock upper chamber to a pressure less than 10 to the -4 Torr;
- lowering said stage in a linear, vertical direction, so that said bell jar shape cover remains supported on said partial floor in said upper process chamber while said body including wafers is lowered into the lower chamber;
- transferring wafers in a desired sequence from said wafer carrier under vacuum to one or more selected process stations which are enclosed inside a connecting contiguous vacuum-tight space with said lower chamber until a desired sequence of processing operations has been completed;
- and then raising said stage to rejoin said wafer carrier body with said wafer carrier bell jar shape cover and again effect a vacuum seal therebetween;
- venting said upper chamber to ambient; and
- removing said wafer carrier from said upper chamber.
- 2. The method of claim 1, wherein said stage effects a vacuum seal between said upper chamber and said lower chamber when said stage is subsequently in its upper position, so that said upper chamber is hermetically sealed from said lower chamber while said wafer carrier is removed or emplaced in said upper chamber.
- 3. The method of claim 1, wherein said upper chamber has exhaust and purging ports separate from said lower chamber; and
- further comprising the initial step of, prior to lowering said stage, purging said upper chamber with clean gas flow to reduce the particulates therein.
- 4. The method of claim 1, wherein said upper chamber, with a wafer carrier emplaced therein and the lid of said upper chamber closed, has substantially only smooth surfaces exposed on the interior thereof to said exhaust and purging ports.
- 5. The method of claim 1, wherein said pressure in said wafer carrier is less than 10 to the -4 Torr at the time said wafer carrier body is resealed with said wafer carrier bell jar shape cover.
- 6. The method of claim 1, wherein said slots in said wafer carrier are sized to hold wafer holders of a predetermined size, said wafer holders directly supporting integrated circuit wafers.
- 7. A method for fabricating integrated circuits, comprising the steps of:
- providing a plurality of wafers in a vacuum sealable wafer carrier, said wafer carrier comprising a bell jar shape cover which is vacuum sealable to a body thereof, said bell jar shape cover being removable from said body in a direction which is substantially normal to the plane of wafers supported in said body;
- placing said wafer carrier into a vacuum sealable load lock upper chamber having a partial floor with an aperture therein and a stage positioned below said aperture in close proximity to said floor;
- pumping down said load lock upper chamber;
- lowering said stage in a linear, vertical direction, so that said bell jar shape cover remains supported on said partial floor in said upper load lock chamber while said body including wafers is lowered into the lower chamber;
- transferring wafers under vacuum in a desired sequence from said wafer carrier to one or more selected process stations until a desired sequence of processing operations has been completed;
- raising said stage to rejoin said wafer carrier body with said wafer carrier bell jar shape cover and again effect a vacuum seal therebetween;
- raising the pressure of said upper chamber to ambient; and removing said wafer carrier from said upper chamber.
- 8. The method of claim 7, wherein said step of pumping down said load lock upper chamber is a step of pumping down to a pressure less than 10 to the -4 Torr.
- 9. A method for fabricating integrated circuits, comprising the steps of:
- providing a plurality of wafers in a vacuum sealable wafer carrier, said wafer carrier comprising a bell jar shape cover which is vacuum sealable to a body thereof;
- placing said wafer carrier into a vacuum sealable load lock upper chamber having a partial floor with an aperture therein and a stage positioned below said aperture in close proximity to said floor;
- pumping down said load lock upper chamber to lower the pressure;
- lowering said stage so that said bell jar shape cover remains in said upper process chamber while said body including wafers is lowered into the lower chamber;
- raising said stage to rejoin said wafer carrier body with said wafer carrier bell jar shape cover; and raising the pressure of said upper chamber to ambient.
CROSS-REFERENCE TO RELATED APPLICATIONS
This is a division of application Ser. No. 114,812, filed Oct. 29, 1987 now U.S. Pat. No. 4,966,519 which is a division of Ser. No. 061,017 filed on June 12, 1987, now abandoned, which is a continuation of Ser. No. 824,342 filed on Jan. 30, 1986 now abandoned which is a continuation-in-part of Ser. No. 790,708 filed Oct. 24, 1985, now abandoned Ser. No. 790,918 filed Oct. 24, 1985, now abandoned and Ser. No. 790,924 filed Oct. 24, 1985, now U.S. Pat. No. 4,687,542.
Government Interests
The U.S. Government has a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terms of contract No. N00014-85-C-0286 awarded by DARPA.
US Referenced Citations (11)
Divisions (2)
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Date |
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114812 |
Oct 1987 |
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Parent |
61017 |
Jun 1987 |
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Continuations (1)
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824342 |
Jan 1986 |
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Continuation in Parts (3)
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790708 |
Oct 1985 |
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Parent |
790918 |
Oct 1985 |
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Parent |
790924 |
Oct 1985 |
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