1. Field of the Invention
The present invention relates generally to integrated circuits and devices, and, more particularly to matching the threshold voltages of enhancement mode and depletion mode devices and reducing output capacitance of gallium nitride (GaN) devices.
2. Description of the Related Art
GaN semiconductor devices are increasingly desirable because of their ability to switch at high frequency, to carry large current, and to support high voltages. Development of these devices has generally been aimed at high power/high frequency applications. Devices fabricated for these types of applications are based on general device structures that exhibit high electron mobility and are referred to variously as heterojunction field effect transistors (HFET), high electron mobility transistors (HEMT), or modulation doped field effect transistors (MODFET). These types of devices can typically withstand high voltages, e.g., 30V-to-2000 Volts, while operating at high frequencies, e.g., 100 kHZ-100 GHz.
A GaN HEMT device includes a nitride semiconductor with at least two nitride layers. Different materials formed on the semiconductor or on a buffer layer causes the layers to have different band gaps. The different material in the adjacent nitride layers also causes polarization, which contributes to a conductive two dimensional electron gas (2DEG) region near the junction of the two layers, specifically in the layer with the narrower band gap.
The nitride layers that cause polarization typically include a barrier layer of AlGaN adjacent to a layer of GaN to include the 2DEG, which allows charge to flow through the device. This barrier layer may be doped or undoped. Because the 2DEG region exists under the gate at zero gate bias, most nitride devices are normally on, or depletion mode devices. If the 2DEG region is depleted (i.e., removed) below the gate at zero applied gate bias, the device can be an enhancement mode device. Enhancement mode devices are normally off and are desirable because of the added safety they provide and because they are easier to control with simple, low cost drive circuits. An enhancement mode device requires a positive bias applied at the gate in order to conduct current.
In some integrated circuit designs, a high electron mobility transistor (HEMT) or pseudomorphic High-Electron Mobility Transistor ((p-)HEMT) is divided into a depletion mode transistor having a negative value of threshold voltage VTh and an enhancement mode transistor having a positive value of threshold voltage VTh. In such designs, it is desirable for the absolute value of the threshold voltages VTh of the enhancement mode and depletion mode devices to be equal. For example, if the enhancement mode threshold voltage VTh is positive 1.5 volts, the depletion mode device threshold voltage VTh should be negative 1.5 volts.
The present invention provides an approach to achieve enhancement mode and depletion mode devices with the same absolute value.
Embodiments described below address the problems discussed above and other problems, by providing an integrated circuit having an enhancement mode device and depletion mode device that includes an isolation region isolating the two devices and a thinner region or gate contact recess in the aluminum gallium nitride (AlGaN) barrier layer under the gates that can be used to modulate the threshold voltages VTh of the enhancement mode and depletion mode devices so that the absolute values of the threshold voltages are approximately equal.
In particular, an integrated circuit is disclosed herein having a substrate; at least one buffer layer formed over the substrate; a barrier layer formed over the at least one buffer layer; and an isolation region formed to isolate a first portion of the barrier layer for a first transistor device from a second portion of the barrier layer for a second transistor device, the first and second portions of the barrier layer each having respective gate contact recesses. The integrated circuit further includes a first gate contact disposed at least partially in the gate contact recess of the first portion of the barrier layer for the first transistor device; and a second gate contact disposed at least partially in the gate contact recess of the second portion of the barrier layer for the second transistor device. In the exemplary embodiment, the first and second transistor devices are an enhancement mode device and depletion mode device, respectively.
One object of the exemplary embodiments is to provide a gallium nitride power device with a lower gate-drain capacitance (Cgd) and a lower output capacitance (Coss). According to an exemplary embodiment, the gate contact recess of the thinner AlGaN barrier extends outside of the gate contact towards the drain. In this embodiment, since the barrier at the drain side gate corner is thinner, the device has lower 2DEG density, and, therefore, gate-drain capacitance (Cgd) and output capacitance (Coss) are reduced.
The above-noted and other features, objects, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:
In the following detailed description, reference is made to certain embodiments. These embodiments are described with sufficient detail to enable those skilled in the art to practice them. It is to be understood that other embodiments may be employed and that various structural, logical, and electrical changes may be made. The combinations of features disclosed in the following detailed description may not be necessary to practice the teachings in the broadest sense, and are instead taught merely to describe particularly representative examples of the present teachings.
As further shown, the enhancement mode device 101 includes a source 102, gate 103, and drain 105, with a dielectric film 107 that covers the device and an optional field plate 106. Likewise, the depletion mode device 201 includes a source 202, gate 203, and drain 205, and also includes a dielectric film 207 and an optional field plate 206. An isolation area 301 is formed in the barrier layer 304 to divide the barrier layer into first and second portions for the enhancement mode device 101 and the depletion mode device 201. It should be appreciated that although isolation area 301 is illustrated as an etched window in the barrier 304 of
In order to modulate the threshold voltage VTh of the enhancement mode device 101, the barrier layer 304 includes thinner portion 104 (i.e., a gate contact portion 104) under the gate 103, relative to the portions of the barrier layer 304 not disposed under the gate 103. The thinner portion 104 of the barrier layer under gate 103 increases the value of the positive threshold voltage VTh. As shown in
In the exemplary embodiment of the integrated circuit 100 illustrated in
As shown in these embodiments of
It is noted that each of the enhancement mode device 1001 and the depletion mode device 2001 illustrated in
Initially, as shown in
Next, as shown in
After these thinner portions of barrier layer 304 have been formed, a pGaN layer is grown over the top surface, which is patterned and etched to form the enhancement mode device gate 103 as shown in
Next, with reference to
As shown in
The above description and drawings are only to be considered illustrative of specific embodiments, which achieve the features and advantages described herein. Modifications and substitutions to specific process conditions can be made. Accordingly, the embodiments of the invention are not considered as being limited by the foregoing description and drawings.
This is a divisional application of application Ser. No. 14/446,985, filed on Jul. 30, 2014, which claims the benefit of U.S. Provisional Application No. 61/859,803, filed on Jul. 30, 2013, the entire disclosures of which are hereby incorporated by reference.
Number | Name | Date | Kind |
---|---|---|---|
4849368 | Yamashita | Jul 1989 | A |
5341007 | Kuwata | Aug 1994 | A |
5514605 | Asai | May 1996 | A |
6563197 | Wagers et al. | May 2003 | B1 |
6703638 | Danzilio | Mar 2004 | B2 |
7829957 | Kato et al. | Nov 2010 | B2 |
8253218 | Bito | Aug 2012 | B2 |
20060027840 | Wohlmuth | Feb 2006 | A1 |
20060284212 | Murayama | Dec 2006 | A1 |
20070295991 | Kato | Dec 2007 | A1 |
20080185613 | Beach et al. | Aug 2008 | A1 |
20090230482 | Kato et al. | Sep 2009 | A1 |
20100006895 | Cao et al. | Jan 2010 | A1 |
20110221011 | Bahat-Treidel et al. | Sep 2011 | A1 |
20110248283 | Cao et al. | Oct 2011 | A1 |
20110309372 | Xin et al. | Dec 2011 | A1 |
20120091513 | Saimei et al. | Apr 2012 | A1 |
20120235209 | Briere et al. | Sep 2012 | A1 |
20120261720 | Puglisi et al. | Oct 2012 | A1 |
20140138743 | Saeki | May 2014 | A1 |
Number | Date | Country |
---|---|---|
WO 2013018580 | Feb 2013 | WO |
Entry |
---|
M. Charfeddine et al., β2-D Theoretical Model for Current-Voltage Characteristics in AlGaN/GaN HEMT's,β Journal of Modern Physics, vol. 3, pp. 881-886, Aug. 2012. |
Number | Date | Country | |
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20160111416 A1 | Apr 2016 | US |
Number | Date | Country | |
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61859803 | Jul 2013 | US |
Number | Date | Country | |
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Parent | 14446985 | Jul 2014 | US |
Child | 14958604 | US |