Patent Application
20190013240
The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to interconnects and methods for forming interconnects.
An interconnect structure may be used to electrically connect device structures fabricated by front-end-of-line (FEOL) processing. A back-end-of-line (BEOL) portion of the interconnect structure may include metallization formed using a damascene process in which via openings and trenches etching in a dielectric layer are filled with metal to create features of a metallization level.
Copper is a common material used in the metallization of the BEOL portion of the interconnect structure. With scaling to smaller feature sizes (e.g., 5 nm and smaller nodes), the behavior of copper hinders the formation BEOL features, such as fully aligned vias (FAVs), that are characterized by high aspect ratios of depth to width. After planarization, the top surfaces of BEOL features are recessed prior to the formation of a cap. The etching process that provides the recessing may exhibit a dependence in etch rate upon grain structure. The result is that the top surface, which is initially planar after polishing, is no longer planar due to roughness resulting from the grain-structure dependent etch rate.
Improved interconnects and methods for forming interconnects are needed.
According to an embodiment of the invention, a method includes forming an interconnect opening in a dielectric layer, forming a conductive layer in the interconnect opening, and forming a modified section in the conductive layer near a top surface of the conductive layer. After the modified section is formed, the modified section of the conductive layer is recessed with an etching process that at least partially removes the modified section. The modified section may have a composition that includes niobium.
According to an embodiment of the invention, a structure includes a dielectric layer with an interconnect opening and a conductive layer in the interconnect opening. The conductive layer includes a top surface, a bottom surface, and a modified section near the top surface. The modified section may have a composition that includes niobium.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.
With reference to
Interconnect openings, of which interconnect opening 12 is representative, may be formed by photolithography and etching at selected locations distributed across the surface area of dielectric layers 10, 11. Specifically, a photoresist layer may be applied, exposed to a pattern of radiation projected through a photomask, and developed to form a corresponding pattern of openings situated at the intended locations for the interconnect openings The patterned photoresist layer is used as an etch mask for a dry etching process, such as a reactive-ion etching (RIE), that removes portions of the dielectric layers 10, 11 to form the interconnect openings. The etching process may be conducted in a single etching step or multiple etching steps with different etch chemistries and with the use of additional hard mask layers.
The interconnect opening 12 may be a contact opening or a trench defined in the dielectric layers 10, 11 and may have an aspect ratio of height-to-width that is characteristic of a contact opening or a trench. The interconnect opening 12 has one or more sidewalls 14 that penetrate from a top surface of the dielectric layer 11 to a surface at the bottom 15 of the interconnect opening 12. The sidewalls 14 are bounded by the dielectric material of the dielectric layers 10, 11 and primarily by the dielectric material of the dielectric layer 10), and the bottom 15 may also be bounded by the dielectric material of the dielectric layer 10. The interconnect opening 12 may penetrate to a given depth into the dielectric layer 10 that is less than the thickness of dielectric layer 10 or may penetrate completely through the thickness of dielectric layer 10. The interconnect opening 12 may land at its bottom 15 on an underlying conductive feature (not shown) as part of a process to establish a vertical interconnection.
A barrier/liner layer 18 of a given thickness is arranged on the sidewalls 14 and at the bottom 15 of the interconnect opening 12. The barrier/liner layer 18 may be comprised of cobalt (Co), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), or a multilayer combination of these materials (e.g., a Ta/TaN bilayer) deposited by physical vapor deposition (PVD) with, for example, a sputter-assisted process, chemical vapor deposition (CVD) or atomic layer deposition (ALD). The barrier/liner layer 18 conforms to the shape of the interconnect opening 12 such that the dielectric layers 10, 11 bordering the sidewalls 14 of the interconnect opening 12 and the bottom surface 15 of the interconnect opening 12 are completely covered by a uniform given thickness.
An interconnect feature 16 is arranged inside the interconnect opening 12. The interconnect feature 16 includes a conductive layer 20 of a given thickness that is formed inside the interconnect opening 12 in contact with the barrier/liner layer 18. The conductive layer 20 may be deposited by electroless deposition, which may require the prior deposition of a conformal seed layer by PVD, or may be formed by a reflow process. The conductive layer 20 may be composed of copper (Cu) or a copper-manganese (Cu—Mn) alloy, and may be polycrystalline and characterized by material properties, such as an average grain size.
The materials of the barrier/liner layer 18 and the conductive layer 20 and/or its seed layer formed on the field area on the top surface of the dielectric layers 10, 11 may be removed with a chemical mechanical polishing (CMP) process. Material removal during the CMP process combines abrasion and an etching effect that polishes the targeted material and may be conducted with a commercial tool using polishing pads and slurries selected to polish the targeted material(s). The conductive layer 20 of the interconnect feature 16 inside the interconnect opening 12 is planarized relative to the top surface of the dielectric layer 11 by the CMP process. The top surface 21 of the conductive layer 20 may be planar and flat, and may be coplanar with the top surface of the dielectric layer 11. The conductive layer 20 has a bottom surface 19 that is located adjacent to the bottom 15 of the interconnect opening 12. The barrier/liner layer 18 is disposed between the conductive layer 20 and the sidewalls 14 and bottom 15 of the interconnect opening 12.
With reference to
An element is introduced into the conductive layer 20 so as to form the modified section 22. The introduced element may be an element that is initially absent from the as-formed conductive layer 20. In an embodiment, the modified section 22 may be formed by implanting the conductive layer 20 with energetic ions that are introduced through the top surface 21 of the conductive layer 20 and that stop in the conductive layer 20 adjacent to the top surface 21. The trajectories of the ions penetrate into the conductive layer 20 with a depth profile parameterized by a projected range and a range straggle. The ions may be generated from a suitable source gas and implanted with selected implantation conditions using an ion implantation tool. The implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to tune the characteristics (e.g., depth profile and physical properties) of the modified section 22. In embodiments, the element delivered by the ions may include, but is not limited to, niobium (Nb), aluminum (Al), cobalt (Co), ruthenium (Ru), or hydrogen (H).
The ions may deliver an element that is capable of combining with the conductor of the conductive layer 20 to dope the modified section 22 and/or to form an alloy in the modified section 22. The crystal structure of the modified section 22, in comparison with the polycrystalline structure of the non-modified section, may be amorphous and free of detectable grains. Alternatively, the crystal structure of the modified section 22, in comparison with the polycrystalline structure of the non-modified section, may be a fine-grained structure characterized by grains with an average grain size that is significantly smaller than the average grain size of the grains in the non-modified section of the conductive layer 20. The modified section 22 may be conductive following the implantation.
In an embodiment, the element delivered by the ions may be niobium (Nb). For example, niobium ions may be implanted at an energy in a range of 5 keV to 25 keV and with a dose of 1×1015 cm−2 to 1×1016 cm−2. The modified section 22 may be an alloy of niobium and copper, as well as any alloying elements (e.g., manganese) present in the conductive layer 20 before the performance of the implantation. The thickness of the ion-implanted modified section 22 can range from two (2) nm to fifteen (15) nm.
In an alternative embodiment, the modified section 22 may be formed by in a different manner. For example, a plasma containing the modifying element (e.g., Nb) can be used to selectively incorporate the element into the conductive layer 20 at the top surface 21 of the conductive layer 20. The plasma may include, for example, the species NbH4 that is generated from an organic precursor such as Tris(diethylamido)(tert-butylimido)niobium(V) (C16H39N4Nb) or Bis(cyclopentadienyl)niobium(IV) dichloride 95% (C10H10C12Nb).
With reference to
With reference to
A dielectric cap 28 composed of a dielectric material, such as silicon nitride (Si3N4), with etch selectivity to the dielectric material of the dielectric layer 10 may be deposited to cover the top surface 21 of the conductive layer 20 and the top surface of the dielectric layer 11. The remainder of the modified section 22 operates as a metal cap that is arranged between the dielectric cap 28 and the non-modified section of the conductive layer 20 that is located between the modified section 22 and the bottom 15 of the interconnect opening 12. In this regard, the conductive layer 20 may not require the formation of an additional metal cap (e.g., a metal cap composed of cobalt).
In an alternative embodiment shown in
With reference to
The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.
References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction within the horizontal plane. Terms such as “above” and “below” are used to indicate positioning of elements or structures relative to each other as opposed to relative elevation.
A feature “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
