Patent Application
20250105010
Layer transfer using patterned masks and related systems are generally described.
The present disclosure is related to layer transfer using patterned masks and related systems. Certain of the methods in this disclosure comprise growing epitaxial layers over masks patterned with respect to crystallographic directions on a crystalline substrate in a manner that improves the quality of epitaxial layer (e.g., by reducing defects). The subject matter of the present disclosure involves, in some cases, interrelated products, alternative solutions to a particular problem, and/or a plurality of different uses of one or more systems and/or articles.
In one aspect, methods of growing an epitaxial layer are provided. In some embodiments, the method comprises growing an epitaxial layer over a structure comprising a crystalline substrate and a mask such that the mask is between the epitaxial layer and the crystalline substrate; and separating the epitaxial layer and the crystalline substrate from each other; wherein: the crystalline substrate has a diamond cubic crystal structure or a zinc blende crystal structure; the mask and the epitaxial layer are over a {100} plane of the crystalline substrate; the mask comprises a plurality of elongated domains, each elongated domain having long edges; each of the long edges is within 10 degrees of parallel to a <110> direction on the {100} plane of the crystalline substrate, on a {100} plane of the epitaxial layer, or both.
In certain embodiments, the method comprises growing an epitaxial layer over a structure comprising a crystalline substrate and a mask comprising a plurality of elongated domains, each elongated domain having long edges, such that elongated domains are between the epitaxial layer and the crystalline substrate; and separating the epitaxial layer and the crystalline substrate from each other; wherein: the elongated domains of the mask are not connected to each other; and the elongated domains occupy at least 50% of a facial surface area of the crystalline substrate.
Other advantages and novel features of the present disclosure will become apparent from the following detailed description of various non-limiting embodiments of the disclosure when considered in conjunction with the accompanying figures. In cases where the present specification and a document incorporated by reference include conflicting and/or inconsistent disclosure, the present specification shall control.
Non-limiting embodiments of the present disclosure will be described by way of example with reference to the accompanying figures, which are schematic and are not intended to be drawn to scale unless otherwise indicated. In the figures, each identical or nearly identical component illustrated is typically represented by a single numeral. For purposes of clarity, not every component is labeled in every figure, nor is every component of each embodiment of the disclosure shown where illustration is not necessary to allow those of ordinary skill in the art to understand the disclosure. In the figures:
Methods for growing epitaxial layers (also sometimes referred to as “epilayers”) are described herein. In some embodiments, an epitaxial layer is grown over a structure comprising a crystalline substrate and a mask. The mask can be patterned with a plurality of elongated domains that are parallel or close to parallel (e.g., within 10 degrees of parallel, or closer to parallel) to a direction of the <110> family of directions on a plane of the {100} family of planes on the crystalline substrate. The plurality of elongated domains may facilitate the growth of the epitaxial layer with a reduced number of defects on the crystalline substrate. The mask may also facilitate the separation of the epitaxial layer from the crystalline substrate. This can allow for the formation of freestanding epitaxial layers. In some embodiments, the method for growing an epitaxial layer may allow for heteroepitaxy of compound semiconductors on elemental substrates with a reduced number of defects despite polarity and/or lattice mismatches.
With the advancement of current electronic and photonic devices, demands for heterogeneous integration of dissimilar materials are continuously increasing to realize multifunctional chips on a single platform. Heterointegration of single-crystalline materials has traditionally been carried out either by monolithic approaches using heteroepitaxy or by transfer of semiconductor membranes from foreign substrates. For heteroepitaxy, elemental semiconductors such as Si and Ge have been utilized as epitaxial templates for growing compound semiconductors owing to their substantially lower costs and compatibility with mature platforms. However, heteroepitaxy has historically not avoided the formation of crystalline defects such as dislocations and antiphase boundaries (APBs), which severely deteriorate device performance. Anti-phase boundaries generally form due to defects and/or step-edges on surfaces of the crystalline substrate and are difficult to eliminate during wafer and/or crystalline substrate production.
Certain aspects of the present disclosure involve methods to reduce crystallographic defects in heteroepitaxial layers while allowing relatively fast mechanical layer release. In accordance with certain embodiments, this can be realized by performing epitaxy over a substrate over which a patterned mask (e.g., a nanopatterned mask) is positioned. The epitaxial growth can involve initial formation of the epilayer on exposed portions of the substrate followed by lateral overgrowth. Certain embodiments described herein can provide one or more of the following advantages: i) epilayers and wafters can be readily separated from each other by simple mechanical exfoliation (e.g., due to reduced interface toughness with the nanopatterned mask), ii) elemental materials can be used not only as substrates but can be made as freestanding membranes, iii) the materials (e.g., compound semiconductors and/or other crystalline materials) can be fabricated with a reduced number of APBs, even on elemental semiconductor substrates, and iv) dislocations can be reduced in lattice-mismatched heteroepitaxial systems due to lateral relaxation and/or by the flexibility and chemical inertness of the mask material (e.g., graphene).
Certain aspects are directed to methods of growing an epitaxial layer. In some embodiments, the method of growing an epitaxial layer comprises growing an epitaxial layer over a structure. The structure comprises, in accordance with certain embodiments, a crystalline substrate and a mask. The mask, in certain embodiments, can be between the epitaxial layer and the crystalline substrate. The mask may comprise a plurality of elongated domains wherein each elongated domain has long edges (e.g., two edges that are parallel or substantially parallel to each other, such as when the elongated domain is in the form of a stripe). The long edges of the plurality of elongated domains can, in some embodiments, be within 10 degrees of parallel to a direction in the <110> family of directions on a plane in the {100} family of planes on the crystalline substrate. In some embodiments, the method of growing the epitaxial layer further comprises separating the epitaxial layer and the crystalline substrate from each other. This separation can result in the formation of a first structure that comprises a substrate and a second structure that comprises the epitaxial layer.
Advantageously, in accordance with certain embodiments, the epitaxial layers produced using the systems and methods described herein can comprise relatively low defect densities and/or anti-phase domain (APD) densities. Accordingly, electronic devices (e.g., diodes, transistors, rectifiers, etc.) comprising the epitaxial layers can, in some embodiments, exhibit improved performance. For example, in some embodiments, a light-emitting diode comprising the separated epitaxial layer may exhibit higher electroluminescence and/or lower forward bias recombination current than a light-emitting diode not comprising the separated epitaxial under otherwise identical conditions.
The epitaxial layer can be formed, in some embodiments, over a substrate. One example of such a substrate is shown in
A variety of types of substrates can be employed. In some embodiments, the crystalline substrate comprises silicon, germanium, carbon (e.g., diamond), α-tin, and/or compound semiconductors including but not limited to gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), aluminum phosphide (AlP), aluminum arsenide (AlAs), aluminum antimonide (AlSb), zinc selenide (ZnSe), cadmium sulfide (CdS), III-V semiconductors, I-VII semiconductors, and/or II-VI semiconductors. In some embodiments, the substrate comprises a III-nitride material, such as a gallium nitride material or an aluminum nitride material. In some embodiments, the substrate comprises a III-phosphide material. In some embodiments, the substrate comprises a III-arsenide material. In some embodiments, the substrate is an elemental substrate.
In some embodiments, the crystalline substrate comprises at least one crystalline domain. In some embodiments, the at least one crystalline domain comprises a diamond cubic crystal structure or a zinc blende crystal structure. In some embodiments, the crystalline substrate is a single crystal (e.g., a single crystalline substrate comprising a diamond cubic crystal structure or a zinc blende crystal structure). For example, in some embodiments, the substrate is a single crystal wafter (e.g., single crystal semiconductor wafer or other single crystal wafer).
In some embodiments, a surface of the crystalline substrate on which epitaxy is performed to form the epitaxial layer is not monoatomically smooth. For example, in certain embodiments, the surface of the crystalline substrate on which epitaxy is performed may comprise defects including but not limited to monoatomic steps and/or terraces. Traditionally, epitaxy (homoepitaxial or heteroepitaxy) on the surface of the crystalline substrate that is not monoatomically smooth can result in epitaxial layers comprising crystalline defects including but not limited to edge dislocations, screw dislocations, and/or anti-phase boundaries (APBs). Such defects can negatively impact the performance of electronic devices fabricated from the epitaxial formations. Certain embodiments involve the use of systems and methods under which such defects are reduced or even eliminated, even when the surface of the crystalline substrate on which epitaxy is performed is not monoatomically smooth. Of course, the embodiments described herein are not limited to such examples, and in some cases, the surface of the crystalline substrate on which epitaxy is performed is monoatomically smooth.
In some embodiments, the crystalline substrate has no polarity. For example, the crystalline substrate can be, in some embodiments, a IV substrate such as silicon or germanium substrates. In some embodiments, the crystalline substrate can have a polarity. For example, in some embodiments, the crystalline substrate is a III-V substrate. In some embodiments, the crystalline substrate has a different polarity than that of the epitaxial layer that is grown on the substrate. Polarity mismatches between the crystalline substrate and the epitaxial layer have, traditionally, led to the formation of anti-phase boundaries within the epitaxial layer. As mentioned above, such defects generally negatively impact the performance of electronic devices fabricated from the epitaxial layer with anti-phase boundaries. Certain embodiments involve the use of systems and methods under which such anti-phase boundaries are reduced or even eliminated.
In certain embodiments, the epitaxial layer is grown over a structure comprising the crystalline substrate and a mask. One example of such a structure is structure 115 in
In some embodiments, the mask comprises plurality of elongated domains. The elongated domains can be made of a solid material that covers a portion of the substrate and is positioned between the substrate and the epitaxial layer during and after growth of the epitaxial layer. For example, referring to
In some embodiments, the mask is between the epitaxial layer and the crystalline substrate. For example, in
In some embodiments, the mask material has a relatively low thickness. For example, in
In some embodiments, the mask comprises a monolayer of atoms. In some embodiments, the mask comprises a bilayer of atoms). In some embodiments, the mask can be arranged as a plurality of atomic layers (e.g., at least 2, 3, 4, 5, 6, 7, or more atomic layers). For example, in some embodiments, a plurality of graphene layers (e.g., 2, 3, 4, 5, 6, 7, or more graphene layers thick) can be used. In some embodiments, the mask is an atomically thin material.
In some embodiments, the mask comprises a two-dimensional (2D) material. 2D materials are those that are arranged as a single layer of atoms and, accordingly, are a single atom in thickness. The 2D material can include any of a variety of 2D materials. In some embodiments, the 2D material can include graphene (single crystalline or polycrystalline). In some cases, the 2D material comprises a transition metal dichalcogenide (TMD) monolayer (e.g., MoS2 and/or Wse2) which is an atomically thin semiconductor of the type MX2, where M is a transition metal atom (e.g., Mo, W, etc.) and X is a chalcogen atom (e.g., S, Se, or Te). The 2D layer, in certain embodiments, comprises 2D boron nitride. In certain embodiments a single layer of mask material is present (e.g., a single layer of 2D material may be used as a mask). In other embodiments, multiple layers of material (e.g., multiple layers of 2D material) may be used as a mask.
In some embodiments, the mask comprises a dielectric mask. Examples of dielectric masks include but are not limited to silicon dioxide, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, tungsten oxide, and other hard mask materials. In some embodiments, the mask comprises tungsten.
In some embodiments, the mask occupies a relatively high portion of the facial surface area of the crystalline substrate over which the epitaxial layer is grown. The facial surface area of the crystalline substrate over which the epitaxial layer is grown, in certain embodiments, is a plane of the {100} family of planes of the crystalline substrate. The facial surface area of the crystalline substrate that the mask occupies may influence the quality and ease of separation of the separated epitaxial layer. In some embodiments, the mask occupies at least 90%, at least 95%, at least 98%, at least 99%, at least 99.9%, or at least 99.99% of the facial surface area of the crystalline substrate over which the epitaxial layer is grown. In this context, the facial surface area of the crystalline substrate that the mask occupies is calculated by dividing the facial surface area occupied by the outer boundaries of the mask (which includes both the areas that are covered by mask material and areas that are uncovered by mask material but which are, nonetheless, within the outer boundaries of the mask material) by the facial surface area of the substrate over which the epitaxial layer is grown and multiplying the result by 100%. For example, in
In some embodiments, the plurality of elongated domains occupies a relatively large percentage of the facial surface area of the crystalline substrate over which the epitaxial layer is grown. In certain embodiments, the plurality of elongated domains occupies at least 20%, at least 35%, at least 50%, at least 60%, at least 75%, at least 85%, at least 90%, or at least 95% of the facial surface area of the crystalline substrate over which the epitaxial layer is grown. In certain embodiments, the plurality of elongated domains occupies less than or equal to 99% or less than or equal to 98% of the facial surface area of the crystalline substrate over which the epitaxial layer is grown. Combinations of these ranges are also possible (e.g., at least 20% and less than or equal to 99%). In this context, the facial surface area of the crystalline substrate that the elongated domains occupy is calculated by dividing the facial surface area of the elongated domains (which includes only the areas that are occupied by the elongated domains and does not include the areas of the substrate that are uncovered by mask material but which are within the outer boundaries of the mask material) by the facial surface area of the substrate over which the epitaxial layer is grown and multiplying the result by 100%. For example, in
In some embodiments, the mask can be grown and/or deposited over the crystalline substrate. The mask may be grown over the crystalline substrate via chemical vapor deposition (CVD). In some embodiments, the mask can be grown on a second substrate (e.g., copper foil) and can be transferred over to the crystalline substrate. In some embodiments, the mask can be annealed after deposition over the crystalline substrate.
In some embodiments, the mask comprises a pattern. In some embodiments, the mask can be patterned via any of a variety of lithography techniques. The mask, in certain embodiments, can be patterned via electron-beam lithography, interference lithography, stepper lithography, and/or other lithographic techniques known in the art.
In some embodiments, the mask can be over a plane in the {100} family of planes of the crystalline substrate. The {100} family of planes, denoted with braces used in accordance with the Miller index notation for crystallographic planes and directions, indicates the (100) plane as well as other planes of the same plane family. That is to say, the {100} family of planes is the following set of planes: the (100) plane, the (
As noted above, in some embodiments, the mask comprises a plurality of elongated domains. The elongated domains can be made of a material that covers a portion of the substrate and is positioned between the substrate and the epitaxial layer during and after growth of the epitaxial layer.
In some embodiments, each of the plurality of elongated domains comprises long edges and short edges. For example, in
The <110> family of directions, denoted with angle brackets in accordance with the Miller index notation for crystallographic planes and directions, includes the [110] direction as well as other directions in the same family of directions. That is to say, the <110> family of directions is the following set of directions: the [110] direction, the [110] direction, the [110] direction, the [110] direction, the [101] direction, the [101] direction, the [101] direction, the [101] direction, the [011] direction, the [011] direction, the [011] direction, and the [011] direction.
In some embodiments, the long edges of the elongated domains are within 10 degrees of parallel to a direction in the <110> family of directions on a plane in the {100} family of planes on the crystalline substrate, the epitaxial layer, or both. In some embodiments, the long edges of the elongated domains are within 10 degrees, within 5 degrees, within 2 degrees, within 1 degree, or within 0.5 degrees of parallel to a direction in the <110> family of directions on a plane in the {100} family of planes on the crystalline substrate. One example of this is shown in
In some embodiments, the mask comprises a plurality of elongated domains that are not connected to each other via the same material from which the elongated domains are made. That is to say, the elongated domains within the mask can be discontinuous. For example, in
In some embodiments, the long edges of the elongated domains are parallel to or substantially parallel to one, more, or all of the long edges of the other elongated domains of the mask material. For example, in some embodiments, the long edges of the elongated domains are within 10 degrees, within 5 degrees, within 2 degrees, within 1 degree, or within 0.5 degrees of parallel to at least 2, at least 4, at least 6, or more (e.g., all) of the long edges of other elongated domains within the mask. In
The elongated domains can have any of a variety of aspect ratios. In this context, the aspect ratio is the ratio of the length of the elongated domain to the width of the elongated domain. For example, in
The elongated domains can have any of a variety of widths. In some embodiments, each of the plurality of elongated domains has a width that is greater than or equal to 25 nm, greater than or equal to 50 nm, greater than or equal to 100 nm, greater than or equal to 250 nm, greater than or equal to 500 nm, greater than or equal to 1000 nm, greater than or equal to 5 micrometers, or greater than or equal to 10 micrometers. In some embodiments, each of the plurality of elongated domains have a width that is less than or equal to 10 micrometers, less than or equal to 5 micrometers, less than or equal to 1000 nm, less than or equal to 500 nm, less than or equal to 250 nm, less than or equal to 100 nm, less than or equal to 50 nm, or less than or equal to 25 nm. Combinations of these ranges are also possible (e.g., greater than or equal to 25 nm and less than or equal to 10 micrometers).
In some embodiments, the plurality of elongated domains is arranged in a periodic pattern. The average frequency, or average pitch, of the periodic pattern may, in certain embodiments, reduce the formation of anti-phase boundaries in the epitaxial layer and/or facilitate separation of the epitaxial layer from the substrate and/or other parts of the structure. For example, in
In some embodiments, each of the plurality of elongated domains has a nearest neighbor (i.e., another of the elongated domains that is closest to the elongated domain being analyzed). It is possible that an elongated domain can have two nearest neighbors, one on either side of the elongated domain. In
In some embodiments, the mask has a relatively large facial surface area. In some embodiments, the facial surface area of the mask is at least 10 square micrometers; at least 100 square micrometers; at least 1000 square micrometers; at least 10,000 square micrometers; at least 100,000 square micrometers; at least 0.01 square centimeters; at least 0.1 square centimeters; at least 1 square centimeter; at least 10 square centimeters; or at least 100 square centimeters (and/or, up to 100 square centimeters; up to 1,000 square centimeters; up to 10,000 square centimeters, or more). Combinations of these ranges are also possible.
As noted above, the epitaxial layer can be grown over the structure comprising the crystalline substrate and the mask. The epitaxial layer can be grown via any of a variety of epitaxial growth techniques. In some embodiments, the epitaxial growth can be homoepitaxial growth. In other embodiments, the epitaxial growth can be heteroepitaxial growth. In some embodiments, the epitaxial layer can be grown using chemical vapor deposition (CVD) and/or physical vapor deposition (PVD). The growth of the epitaxial layer may rely on the structure comprising the crystalline substrate and the mask as a seed for crystal growth. For example, in some embodiments, the crystalline substrate acts as a seed for crystal growth of the epitaxial layer. In some embodiments, the growth of the epitaxial layer may initiate directly over the crystalline substrate growing in a direction orthogonal to the geometric plane parallel to at least one in the {100} family of planes on the crystalline substrate, between the plurality of elongated domains. In some embodiments, after the growth of the epitaxial layer has exceeded the thickness of the mask, the epitaxial layer may grow laterally and merge into a single layer. In some embodiments, the epitaxial layer is planar.
In some embodiments, the epitaxial layer can be grown over a relatively large facial surface area. In some embodiments, the epitaxial layer is grown over a facial surface area of at least 10 square micrometers; at least 100 square micrometers; at least 1000 square micrometers; at least 10,000 square micrometers; at least 100,000 square micrometers; at least 0.01 square centimeters; at least 0.1 square centimeters; at least 1 square centimeter; at least 10 square centimeters; or at least 100 square centimeters (and/or, up to 100 square centimeters; up to 1,000 square centimeters; up to 10,000 square centimeters, or more). Combinations of these ranges are also possible.
When a structure (e.g., a layer) is referred to as being “on,” “over,” or “overlying” another structure (e.g., a layer or a substrate), it is over at least a portion of that structure. In some cases, a structure that is referred to as being “on,” “over,” or “overlying” another structure is over the entirety of that structure. When a structure (e.g., a layer) is referred to as being “on,” “over,” or “overlying” another structure (e.g., a layer or a substrate), it can be directly on the structure, or an intervening structure (e.g., a layer) also may be present. A structure that is “directly on” or “in direct contact with” another structure means that no intervening structure is present. It should also be understood that when a structure is referred to as being “on” or “over” another structure, it may cover the entire structure, or a portion of the structure. In addition, when a structure is referred to as being “on” or “over” another structure, it may be embedded within that structure. When a structure (e.g., a layer or a substrate) is referred to as being “on,” “over,” or “overlying” another structure, it can be above that other structure or below that other structure.
As noted above, systems and methods described herein can be used for growing epitaxial layers. The epitaxial layer can comprise a crystalline material. In some embodiments, the epitaxial is made up of a single crystalline domain. In some embodiments, the epitaxial layer has a diamond cubic crystal structure and/or a zinc blende crystal structure.
In some embodiments, the epitaxial layer can have no polarity (e.g., IV materials). In some embodiments, the epitaxial layer can have a polarity (e.g., III-V materials). In certain embodiments, the epitaxial layer has a different polarity than that of the crystalline substrate (e.g., by growing a compound semiconductor epitaxially on an elemental crystalline substrate). The methods described herein may advantageously grow epitaxial layers with a polarity mismatch with the crystalline substrate with a relatively low amount of anti-phase boundaries. In some embodiments, the epitaxial layer can have a lattice mismatch with the crystalline substrate (e.g., a InGaAs epitaxial layer on a Ge crystalline substrate). In some embodiments, the lattice mismatch between the crystalline substrate and the epitaxial layer can be at least 1%, at least 2.5%, at least 5%, at least 7.5%, at least 10%, or more. In some embodiments, the lattice mismatch between the crystalline substrate and the epitaxial layer can be less than or equal 80%, less than or equal to 50%, less than or equal to 25%, less than or equal to 20%, less than or equal to 15%, less than or equal to 12.5%, less than or equal to 10%, less than or equal to 7.5%, or less. Combinations of these ranges are also possible (e.g., at least 1% and less than or equal to 80%). Methods described herein may, in certain embodiments, advantageously grow epitaxial layers with a lattice mismatch with the crystalline substrate with a relatively low number of defects.
The epitaxial layer may be made of any of a variety of materials. In some embodiments, the crystalline structure of the epitaxial layer is made of a group V element such as silicon, germanium, carbon (e.g., diamond), or α-tin. In certain embodiments, the crystalline structure of the epitaxial layer is made of a compound semiconductor. For example, in some embodiments, the crystalline structure of the epitaxial layer is made of a III-V semiconductor (materials containing one or more Group III elements and one or more Group V elements), a II-VI semiconductor (materials containing one or more Group II elements and one or more Group VI elements, including but not limited to zinc selenide (ZnSe)), or I-VII semiconductors (materials containing one or more Group I elements and one or more Group VII elements). The epitaxial layer may include impurities. In some embodiments, at least 99 at %, at least 99.9 at %, at least 99.99 at %, at least 99.999 at %, at least 99.9999 at %, at least 99.99999 at % at least 99.99999 at %, at least 99.999999 at %, at least 99.999999 at %, at least 99.9999999 at %, or at least 99.99999999 at % of the epitaxial layer is made up of the materials that form the crystal structure of the epitaxial layer. In some such embodiments, the rest of the crystalline structure comprises other materials (e.g., dopants, impurities, etc.).
In certain embodiments, the crystalline structure of the epitaxial layer comprises a III-nitride material. The term “III-nitride material” is used herein to refer to any Group III element-nitride compound. Non-limiting examples of III-nitride materials include boron nitride (BN), aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), and thallium nitride (TlN), as well as any alloys including Group III elements and Group V elements (e.g., AlxGa(1-x)N, AlxInyGa(1-x-y)N, InxGa(1-x)N, AlxIn(1-x)N, GaAsaPbN(1-a-b), AlxInyGa(1-x-y)AsaPbN(1-a-b), and the like). III-nitride materials may be doped n-type or p-type, or may be intrinsic.
In certain embodiments, the crystalline structure of the epitaxial layer comprises an aluminum nitride material. The phrase “aluminum nitride material” refers to aluminum nitride (AlN) and any of its alloys, such as aluminum gallium nitride (AlxGa(1-x)N), aluminum indium nitride (AlxIn(1-x)N), aluminum indium gallium nitride (AlxInyGa(1-x-y)N), aluminum indium gallium arsenide phosphoride nitride (AlxInyGa(1-x-y)AsaPbN(1-a-b)), and the like. In certain embodiments, the aluminum nitride material comprises AlN.
In certain embodiments, the crystalline structure of the epitaxial layer comprises a gallium nitride material. The phrase “gallium nitride material” refers to gallium nitride (GaN) and any of its alloys, such as aluminum gallium nitride (AlxGa(1-x)N), indium gallium nitride (InyGa(1-y)N), aluminum indium gallium nitride (AlxInyGa(1-x-y)N), gallium arsenide phosphoride nitride (GaAsaPbN(1-a-b)), aluminum indium gallium arsenide phosphoride nitride (AlxInyGa(1-x-y)AsaPbN(1-a-b)), and the like. In certain embodiments, the gallium nitride material comprises GaN.
In certain embodiments, the crystalline structure of the epitaxial layer comprises a III-phosphide material. The term “III-phosphide material” is used herein to refer to any Group III element-phosphide compound. Non-limiting examples of III-phosphide materials include gallium phosphide (GaP), boron phosphide (BP), aluminum phosphide (AlP), indium phosphide (InP), and thallium phosphide (TlP), as well as any alloys including Group III elements and Group V elements (e.g., AlxGa(1-x)P, AlxInyGa(1-x-y)P, InxGa(1-x)P, AlxIn(1-x)P, GaAsaPbN(1-a-b), AlxInyGa(1-x-y)AsaPbN(1-a-b), and the like). III-phosphide materials may be doped n-type or p-type, or may be intrinsic.
In certain embodiments, the crystalline structure of the epitaxial layer comprises a III-arsenide material. The term “III-arsenide material” is used herein to refer to any Group III element-arsenide compound. Non-limiting examples of III-arsenide materials include gallium arsenide (GaAs), boron arsenide (Bas), aluminum arsenide (AlAs), as well as any alloys including Group III elements and Group V elements.
In some embodiments, the methods described herein comprise separating the epitaxial layer and the crystalline substrate from each other. In some embodiments, separating the epitaxial layer and the crystalline substrate can involve applying a force to the epitaxial layer, the crystalline substrate, or both. Separation of the epitaxial layer and the crystalline substrate can involve removing the epitaxial layer while leaving the substrate behind or removing the substrate while leaving the epitaxial layer behind.
In some embodiments, the epitaxial layer can be exfoliated from the crystalline substrate. Mechanical exfoliation of the epitaxial layer may be implemented via the deposition of a stressor layer (e.g., a Ni stressor layer) to form a separated epitaxial layer. The stressor layer can have a relatively high internal stress that may facilitate the propagation of cracks during mechanical exfoliation. In some embodiments, the mask comprising the plurality of elongated domains reduces the interfacial toughness between the crystalline substrate and the epitaxial layer thereby readily allowing the separation of the epitaxial layer from the crystalline substrate. By controlling the thickness of the stressor layer and the internal stress, the mode of fracture may be controlled. For example, in
In certain embodiments, the epitaxial layer is separated from the crystalline leaving the mask over the crystalline substrate. In this manner, the crystalline substrate and the mask, can be reused multiple times (e.g., at least 2 times, at least 5 times, at least 10 times, at least 50 times, at least 100 times, at least 500 times, and/or, up to 1000 times, or more). For example, referring to
In certain cases, insufficient internal stress in the stressor layer and/or insufficient thickness of the stressor layer may lead to delamination of the stressor layer, which may prevent separation of the epitaxial layer from the crystalline substrate. On the other hand, excessive internal stress in the stressor layer and/or excessive thickness of the stressor layer may lead to spalling of the crystalline substrate thereby reducing the quality of the separated epitaxial layer. In certain embodiments, the thickness and/or material type of the stressor layer are selected such that the epitaxial layer is removed from the substrate without spalling of the crystalline substrate. In certain embodiments, the thickness and/or material type of the stressor layer are selected such that delamination of the stressor layer from the epitaxial layer is avoided. More information regarding the influence of the stressor layer on crack propagation can be found in the published manuscript: Kim, H., Lee, S., Shin, J. et al. “Graphene nanopattern as a universal epitaxy platform for single-crystal membrane production and defect reduction,” Nat. Nanotechnol. 17, 1054-1059 (2022). https://doi.org/10.1038/s41565-022-01200-6, and its corresponding Supplementary Information, which is incorporated herein by reference in its entirety for all purposes.
In some embodiments, the epitaxial layer is separated from the structure to form a separated epitaxial layer. In some embodiments, the epitaxial layer (while on the growth substrate and/or after separation from the growth substrate) has a thickness that is relatively low. In the embodiment shown in
In some embodiments, the separated epitaxial layer can be or can be made into a freestanding layer. A layer is considered to be “freestanding,” as that term is used herein, when it is not bound to an adjacent substrate. For example, in
In some embodiments, the epitaxial layer (while on the growth substrate and/or after separation from the growth substrate) comprises a relatively low number of defects. Arranging the mask such that it comprises a plurality of elongated domains parallel or substantially parallel to a direction in the <110> family of direction of the crystalline substrate, the epitaxial layer, or both may reduce the presence of defects (e.g., edge dislocations, screw dislocations, and/or anti-phase boundaries). Without wishing to be bound to any particular theory, the plurality of elongated domains may periodically cover step edges on the crystalline substrate that generally occur along the <110> family of directions for any of a variety of diamond cubic crystal structures and/or zinc blende crystal structures. It is believed that, in order for certain defects to form, such as anti-phase boundaries, at least two step edges may coexist between each of the plurality of elongated domains and the nearest neighbor. The geometric dimensions of the plurality of elongated domains may reduce and/or prevent such defects from forming by reducing the existence of more than step edge per distance between each of the elongated domain and the nearest neighbor.
In some embodiments, the epitaxial layer (while on the growth substrate and/or after separation from the growth substrate) comprises a relatively large facial surface area. The facial surface area, in this context, is the surface area of the face of the epitaxial layer that faces outward from the substrate. For example, referring to
In some embodiments, the epitaxial layer (while on the growth substrate and/or after separation from the growth substrate) advantageously comprises a relatively low threading dislocation density. In some embodiments, the epitaxial layer (while on the growth substrate and/or after separation from the growth substrate) comprises a threading dislocation density of less than or equal to 109 threading dislocations per cm2, less than or equal to 108 threading dislocations per cm2, less than or equal to 107 threading dislocations per cm2, less than or equal to 106 threading dislocations per cm2, less than or equal to 105 threading dislocations per cm2, less than or equal to 104 threading dislocations per cm2, less than or equal to 1,000 threading dislocations per cm2, less than or equal to 100 threading dislocations per cm2, or less than or equal to 10 threading dislocations per cm2. In some embodiments, the epitaxial layer (while on the growth substrate and/or after separation from the growth substrate) comprises a threading dislocation density of greater than or equal to 1 threading dislocation per cm2, greater than or equal to 10 threading dislocations per cm2, greater than or equal to 100 threading dislocations per cm2, greater than or equal to 1,000 threading dislocations per cm2, greater than or equal to 104 threading dislocations per cm2, or greater than or equal to 105 threading dislocations per cm2. Combinations of these ranges are also possible (e.g., less than or equal to 109 threading dislocations per cm2 and greater than or equal to 1 threading dislocations per cm2).
In some embodiments, the epitaxial layer (while on the growth substrate and/or after separation from the growth substrate) advantageously comprises a relatively low anti-phase domain density. In some embodiments, the epitaxial layer (while on the growth substrate and/or after separation from the growth substrate) comprises a surface anti-phase domain density of less than or equal to 107 anti-phase domains per cm2, less than or equal to 106 anti-phase domains per cm2, less than or equal to 105 anti-phase domains per cm2, less than or equal to 104 anti-phase domains per cm 2, less than or equal to 1,000 anti-phase domains per cm2, less than or equal to 100 ani-phase domains per cm2, less than or equal to 10 anti-phase domains per cm2, less than or equal to 5 anti-phase domains per cm2, less than or equal to 1 anti-phase domain per cm2, or no anti-phase domains per cm2. In certain embodiments, the epitaxial layer can contain less than or equal to 100, less than or equal to 10, less than or equal to 5, less than or equal to 2, less than or equal to 1, or no anti-phase boundaries per cubic centimeter. The relatively low number of anti-phase boundaries and the relatively low surface anti-phase domain density may lead to improved device performance. For example, a light-emitting diode comprising the separated epitaxial layer may exhibit higher electroluminescence and/or lower forward bias recombination current than a light-emitting diode not comprising the separated epitaxial under otherwise identical conditions.
In certain embodiments, methods described herein further comprise integrating the epitaxial layer into an electronic device. For example, in some embodiments, after epitaxial layer 120 and substrate 1011 have been separated from each other, and epitaxial layer 120 can be integrated into an electronic device. In some such embodiments, stressor layer 201 can be removed from epitaxial layer 120 (e.g., before, during, or after integration of epitaxial layer 120 into the electronic device). In some embodiments, the method further comprises integrating the epitaxial layer into a diode (e.g., a light emitting diode). In some embodiments, the method further comprises integrating the epitaxial layer into a transistor (e.g., a field effect transistor). In some embodiments, the method further comprises integrating the epitaxial layer into a rectifier.
The following publications and patent applications are incorporated herein by reference in their entirety for all purposes: Kim, H., Lee, S., Shin, J. et al. “Graphene nanopattern as a universal epitaxy platform for single-crystal membrane production and defect reduction.” Nat. Nanotechnol. 17, 1054-1059 (2022). https://doi.org/10.1038/s41565-022-01200-6, and its corresponding Supplementary Information; Sui, Z. and Hutchinson, J. W., “Steady-State Cracking in Brittle Substrates Beneath Adherent Films,” Int. J. Solids Structures, Vol. 25, No. 11, pp. 1337-1353, 1989; U.S. Patent Application Publication No. 2020-0286786 A1, published on Sep. 10, 2020, and filed as International Patent Application No. PCT/US2018/060945 on Nov. 14, 2018, entitled “Epitaxial Growth and Transfer via Patterned Two-dimensional (2D) layers”; and U.S. Pat. No. 10,770,289 to Kim, issued Sep. 8, 2020, and entitled “Systems and Methods for Graphene Based Layer Transfer.”
The following example is intended to illustrate certain embodiments of the present invention but does not exemplify the full scope of the invention.
This example describes the growth of various epitaxial materials on substrates using graphene as a mask material, in accordance with certain embodiments. It was observed that growing epitaxial layers over graphene masks having elongated graphene domains aligned along <110> directions resulted in a substantial reduction in defects. The introduction of patterned graphene can also aid in exfoliating the epitaxial layer from the substrate (as opposed to spalling the substrate and/or delaminating the stressor material from the epitaxial material).
Formation of graphene was conducted as follows.
For Ge substrates, graphene was grown directly on Ge(100) by CVD (TCVD-50B, Graphene Square Inc.) at atmospheric pressure. Ge(100) wafers were first cleaned in a diluted HCl solution (10% HCl in water) for 3 minutes, followed by a water rinse and a nitrogen blow-dry. After loading Ge substrates into the CVD system, the CVD tube was first purged with Ar for 30 minutes at room temperature, followed by a temperature ramp up to 910° C. which took 30 minutes. At 910° C., graphene was grown by flowing H2 of 730 sccm and CH4 of 200 sccm for 60 minutes. After the growth, the tube was cooled to room temperature via an argon flow of 140 sccm. The graphene thickness obtained was between monolayer and bilayer.
For III-V substrates, graphene was first formed on a copper foil by CVD, followed by a standard wet transfer process to transfer the graphene onto the III-V substrate. GaAs substrates were deoxidized by a diluted HCl, and InP substrates by a 5:1 buffered oxide etchant (BOE; J.T. Baker, USA), and both were cleaned with water right before scooping the graphene. Because remote epitaxy of III-V requires dry-transferred graphene and does not work on wet-transferred graphene due to interfacial oxidation, employing wet-transferred graphene in this study ensured that the growth of single-crystalline membranes is the result of a purely lateral overgrowth, not by a mixed growth mode with a portion of remote epitaxy.
Patterning of the graphene mask was conducted as follows.
After the graphene formation, graphene was patterned at the nanoscale by various types of lithographic methods, including e-beam lithography, interference lithography, and stepper lithography. E-beam lithography was mainly used to study the epitaxial film growth and exfoliation behavior, depending on the pattern geometries. 200 nm-thick polymethyl methacrylate (PMMA) resist layer was spin-coated on graphene and baked at 180° C. for 2 min, followed by exposure using Elionix ELS-F125 e-beam lithography system. Exposed samples were then developed in a 1:3 ratio of methyl isobutyl ketone (MIBK):isopropanol (IPA) for 60 s and washed out in pure IPA. Developed PMMA patterns were transferred to graphene by reactive ion etching (RIE) via Plasma-Therm 790 with 02 (20 s, 6 mTorr, 90 W), followed by rinsing of the overlying PMMA layer in acetone to finish graphene patterning process. For large-area thin film growths and LED device fabrication, interference lithography or stepper lithography was employed to produce millimeter- to centimeter-scale patterns. Nanoscale gratings were interferometrically or photolithographically patterned utilizing the interference pattern of 325 nm HeCd laser generated by the Lloyds-mirror lithographic system or exposing in GCA AS200 i-line Stepper, respectively. For both processes, 100 nm-thick positive photoresist (Futurrex PR1-100A1) was first spin-coated on graphene and baked at 120° C. for 2 min. After exposure, the samples are developed in Futurrex RD6 diluted at 3:1 with deionized (DI) water for 15 s and rinsed in pure DI water. The rest of the process was the same as e-beam lithography.
Epitaxial growth was conducted as follows.
Ge, GaAs, and InAs epitaxy were conducted in a close-coupled showerhead MOCVD reactor using arsine, trimethylgallium, trimethylaluminum, trimethylindium, and germane as sources of As, Ga, Al, In, and Ge, respectively. Disilane and dimethylzinc were used as Si and Zn dopants, respectively. The reactor pressure was kept at 100 Torr during the growth, and nitrogen was used as a carrier gas. Ge growth was conducted at 650° C. with a growth rate of about 30 nm/min. GaAs growth was conducted at 650° C. with a growth rate of about 33 nm/min and a V/III flow rate ratio of about 45. InAs growth was conducted at 650° C. with a growth rate of about 23 nm/min and a V/III flow rate ratio of about 65. For the growth on GaAs and InP substrates, arsine and phosphine were respectively flown during the temperature ramp-up from 300° C. to the growth temperature to prevent substrate desorption before the growth. Similarly, after the growth of GaAs and InAs films, arsine was flowed during the temperature ramp-down to 300° C. For the growth of red LED structures, a 2 μm-thick GaAs buffer was first grown at 650° C., followed by a 700 nm-thick p-GaAs bottom contact layer, 350 nm-thick p-Al0.65Ga0.35As barrier, 300 nm-thick Al0.35Ga0.65As emitter, 350 nm-thick n-Al0.65Ga0.35As barrier, and 100 nm-thick n-GaAs top contact layer at 700° C. Although p-GaAs was more commonly used as a top contact layer, n-GaAs was employed as a thin top contact layer and p-GaAs as a thick bottom contact layer because an additional current spreading scheme was not employed and both holes and electrons were laterally injected.
Two-dimensional layer transfer and device fabrication were conducted as follows.
The grown films were exfoliated by first depositing a 30 nm-thick Ti adhesion layer by e-beam evaporation, with a deposition rate of about 0.1 nm/sec. Next, a Ni stressor layer was deposited by direct current (DC) sputtering in the same chamber with a DC power of 500 W and a constant Ar flow of 6 sccm. The stress level of Ni was controlled by the chamber pressure during the sputtering, which typically ranged around 1.1-1.8 mTorr, with a higher pressure resulting in a higher stress level. After the deposition of metal, a thermally releasable tape (TRT; Revalpha, release temperature about 150° C.; Semiconductor Equipment Corp., USA) was attached to the metal via gently rubbing with a cotton swab. The tape edge was then lifted up by holding with a tweezer, which propagates cracks from the sample edge. The cracks propagated as the tape was further lifted up, and the mechanical exfoliation finished when the entire TRT/stressor/epilayer stack was detached from the substrate.
Exfoliated AlGaAs LED layer on TRT was transferred onto a Si wafer by treating with oxygen plasma (Anatech Barrel Plasma System), spin-coating 1 vol % aqueous solution of (3-Aminopropyl)triethoxysilane (APTES; Sigma-Aldrich, USA) at a speed of 3000 rpm for 30 seconds, and baking at 110° C. for 1 minute on both LED and receiver substrate surfaces. The substrate was subsequently spin-coated with polyimide precursor (PI-2545; HD Microsystems, USA) at a speed of 3000 rpm for 30 seconds, baked at 110° C. for 30 seconds, bonded with the LED film on TRT and pressed in steel vise (Toomaker's vise; Tormach, Inc., USA), and baked further at 180° C. for 10 minutes before TRT was removed. Final curing in a 250° C. convection oven completed the transfer process. Wet etching in FeCl3 solution (MG Chemicals, Canada) and in 5:1 BOE removed Ti/Ni layers.
LED mesa structures were fabricated by photolithography and reactive ion etching (RIE; PlasmaPro 100 Cobra 300 System; Oxford Instruments, UK) in Cl2 gas. Both the top and bottom metal contact pads were formed by photolithography, electron-beam evaporation of Cr/Au (about 15/100 nm), and metal lift-off.
Various characterizations of the layers and devices were carried out.
Cross-sectional STEM specimens were prepared with conventional focused ion beam lift-out technique using Helios NanoLab 600. Argon ion milling under 900 and 500 eV was used to clean the surface amorphous layer and minimize subsurface damage.
STEM images were collected using a probe-aberration corrected Thermo Fisher Scientific Themis Z S/TEM operated at 300 kV, 20 mrad convergence semi-angle. Strain mapping of the film with respect to the substrate was conducted using GPA based on atomic resolution images.
Atomic force microscopy (AFM) measurements were conducted using an AFM probe with a silicon tip (PPP-NCHR, Nanosensors) by noncontact mode (Park NX10, Park Systems).
SEM and EBSD characterizations were conducted using a Zeiss Merlin high-resolution SEM system. SEM images were measured using a beam acceleration voltage of 3 kV and a current of 0.1 nA, and EBSD maps were measured using an EBSD detector with a beam acceleration voltage of 15 kV and a current of 3 nA.
Raman and EL spectra were measured using a Renishaw Invia Reflex Micro Raman system with a CCD detector, and I-V characteristics were measured using a Signatone Probe Station (Signatone Corp., USA) equipped with a semiconductor parameter analyzer (Agilent 4156C; Keysight Technologies, USA) and a camera system connected with an optical microscope for collecting images.
Epitaxial layers were produced and separated from substrates as follows.
The EPG technique can be shown to eliminate the formation of APBs in III-V epilayers. The formation of APBs is unavoidable in conventional III-V epitaxy on elemental substrates of on-axis (100) orientation due to the presence of monoatomic steps on the surface. Thus, APBs were clearly observed when GaAs is directly grown on Ge(100), as shown in
The Impact of APB elimination was shown by comparing optoelectronic and electronic performances of III-V devices. AlGaAs-based red light-emitting diodes (LEDs) grown on patterned graphene were APB-free while those directly grown on Ge exhibited APBs in its microstructures (
Defect reduction and strain relaxation in lattice-mismatched heteroepitaxial systems was also shown, which was conducted by theoretically and experimentally comparing heteroepitaxy on patterned graphene with direct heteroepitaxy and SiO2 mask-based conventional selective-area epitaxy. Experimentally, the heteroepitaxy of InAs on InP substrates with 3.2% lattice-mismatch as a model system was studied. Heteroepitaxy was performed on both monolayer graphene and 30-nm-thick SiO2 masks with the same mask width and periodicity. Compared to the case of direct growth of 1 μm-thick InAs on InP, a reduction of dislocations was observed for 1 μm-thick InAs grown on graphene patterns as shown in the scanning transmission electron microscopy (STEM) images in
Air voids were occasionally formed during lateral overgrowth on graphene or SiO2 masks, as shown in the cross-sectional STEM images in
The impact of EPG technique on highly mismatched systems was studied by growing InAs on GaAs substrates, exhibiting 7.2% lattice-mismatch, with graphene patterns having various pitches and opening widths. As shown in the electron-channeling contrast images (ECCI) of InAs epilayers of the same thicknesses of 1 m (see
Exfoliation of the epitaxial material using the stressor layer was studied.
Three modes of peeling (spalling, exfoliation, and delamination) were denoted. In the spalling regime, the material is spalled not at the graphene interface, as shown in
A Bulk Medium with a Stressor Layer.
First, a simple case of a stressor layer on a bulk medium, without graphene, was considered. The model represents the case of spalling, by considering the stress intensity factors as a function of stressor/substrate thickness and elastic properties, as well as loading induced by the stressor at arbitrary crack depths. The resulting expressions for the two stress intensity factors, KI and KII, are described as:
where P is the edge load, M is the moment induced, U, V, and y are dimensionless constants derived from the elastic energy stored far behind the crack tip, h is the stressor thickness, and w is a dimensionless number representing the difference in elastic properties of the stressor and the substrate, as well as the crack depth. The values of these variables can be determined using the equations and methods described in the manuscript: Sui, Z. and Hutchinson, J. W., “Steady-State Cracking in Brittle Substrates Beneath Adherent Films,” Int. J. Solids Structures, Vol. 25, No. 11, pp. 1337-1353, 1989, which is incorporated herein by reference in its entirety for all purposes. As an example, consider a case that a 4-μm thick Ni stressor layer with the stress level of 600 Mpa, which is within a range from about 200 to 800 Mpa achievable by Ni sputtering, is deposited on 350-μm thick Ge(100) substrate. Eqns. 1 and 2 can be solved with the parameters of ENi=200 Gpa, vNi=0.31, hNi=4 μm, and σNi=600 Mpa, EGe=103 Gpa, vGe=0.26, and tGe=350 μm, where E denotes Young's modulus. Calculation results are shown in
The introduction of graphene nanopatterns as an interlayer effectively weakens the interface due to the weak adhesion on van der Waals (vdW) surfaces of graphene, which offers a facile path for the propagation of cracks. For the crack to propagate at the interface, the atomic bonds at the interface need to be broken. Because the vdW bonding between the graphene and the bulk material (such as Ge or GaAs), which is formed on the region covered by graphene stripes, is several orders of magnitude weaker than the covalent bonding between the epilayer and the substrate, which is formed at the region uncovered by graphene, the contribution of graphene-covered region can be neglected for the calculation of energy release rate at the interface. At the front of a propagating crack, the portion of graphene-covered region is proportional to the graphene coverage regardless of the direction of peeling, and therefore, the effective fracture toughness, KIC,eff, can be scaled from the fracture toughness of the bulk medium, KIC, by the graphene coverage, x, as follows:
Such reduction in fracture toughness with increasing graphene coverage results in a corresponding reduction in Ni stressor thickness required to peel the epilayer at the interface, as described in the following subsection.
The conditions for three modes of peeling with the presence of graphene interlayer are discussed below. The strain energy release rate, G, is related to the stress intensity factors by:
where c2 is a function of the Poisson's ratio. Therefore, even though KI is solely responsible in conventional cases where crack propagates at the spalling depth (i.e., where KII becomes zero), KII can be non-zero in our case at the graphene interface, and thus both values should be considered to determine the mode of peeling. Therefore, the criteria can be set for spalling (in any direction) within the epilayer or substrate by the following equation:
Considering the case of Ge/graphene/Ge with a graphene coverage of 70%, then at σNi=600 Mpa and tepilayer=1 μm, the required Ni stressor thickness for crack propagation within the bulk material is hNi=2.91 m, which is derived from Eqns. 1, 2, and 5. Below this Ni stressor thickness, exfoliation at the graphene interface can occur if the KI induced by the stressor, as calculated from Eqn. 1, is larger than KIC,eff, as described by Eqn. 3. If not, the crack cannot propagate either within the bulk medium or the graphene interface, resulting in delamination of the stressor or the handling layer under the criterion:
This occurs at hNi=0.30 μm, indicating that the range of Ni thickness for exfoliation of epilayer is 0.30-2.91 μm, as shown in
The required thickness of the Ni stressor layer for successful exfoliation varies by several factors. In general, when the graphene coverage, x, is large (such as >70%), there is a large window of the stressor thickness and stress level that allows for exfoliation. In other words, even if the stressor condition is not well-controlled, the epilayer will still be precisely exfoliated at the interface regardless of the thickness of the epilayer. On the other hand, when the graphene coverage becomes smaller, the stressor thickness required to satisfy Eqn. 3 becomes higher than that required to satisfy Eqn. 6 at some point, meaning that exfoliation cannot occur regardless of the stressor condition below a certain value of x. The same principles can be applied to any other material systems, such as GaAs/graphene/GaAs, GaAs/graphene/Ge, InAs/graphene/InAs, and InP/graphene/InP, with slight differences. First, in the heterostructure such as GaAs/graphene/Ge, the condition for spalling in the epilayer and in the substrate needs to be calculated separately, since GaAs and Ge have different KIC values. Second, in the case of materials having {110} fracture planes, such as GaAs, the KIC of the material along {110} planes needs to be used, not along {100}, and also, the increased surface area of a zig-zag crack needs to be considered. With those differences in mind, the peeling modes can be determined with the same principles, as described in
A broad choice of stressor metals and their stress levels for the design of efficient and functional devices with flexibility in their fabrication processes could be advantageous. Gold and silver can be employed as a stressor layer for peeling based on conventional spalling approaches. Therefore, the gold layer, for example, could be directly utilized as a back reflector of optoelectronic devices after being used as a stressor layer. In addition, a much higher stress level in Ni (over 1000 Mpa) can be achieved by electroplating of Ni instead of sputtering. Higher stress allows for harvesting thinner membranes by conventional mechanical spalling. However, such a high stress level is not required in the approach described in this disclosure because epilayers of any thickness can be exfoliated when the nanopatterned graphene interlayer is introduced, and the peelable window of Ni thickness rather shrinks under high-stress stressors, as illustrated in
The explanation provided here is, to a certain extent, simplified in that the interfacial fracture toughness is scaled as KIC,eff, whereas in reality, the interface is composed of two regions with KIC=KIC,bulk and KIC=KIC,graphene≈0, for exposed and graphene-covered regions, respectively. Such simplification could induce differences between the theoretically derived peeling mode and experimental results under specific conditions. For example, under the condition of σNi=600 Mpa and tepilayer=1 μm, exfoliation is possible when x is larger than about 0.2. Experimentally, exfoliation was not successful below x of about 0.4. Also, at a higher graphene coverage (about 0.5), partial failure of exfoliation (i.e., local spalling) was observed, because KII is non-zero at the interface and the propagation of crack at the exposed region of the interface along out-of-plane direction has a chance for such local spalling.
Analytical solutions from conventional spalling theory to estimate the criteria for exfoliation at graphene interfaces were developed. In principle, the generation and propagation of cracks through a medium are governed by stress intensity factors, KI(opening mode) and KII (shear mode), exerted by the stressor layer, and fracture toughness KIC of the spalled medium. When graphene nanopatterns are introduced, the presence of graphene effectively weakens the interface because the bonding strength of graphene-covered surface is marginal. For a graphene coverage percentage of x, the effective fracture toughness at the interface becomes,
K
IC,eff=(1−x)KIC,
and, as the thickness of the epilayer deviates from the spalling depth (KII≠0), the condition for spalling changes to,
K
I
2
+K
II
2
>K
IC
2.
On the other hand, the delamination of a stressor layer from the surface of the epilayer occurs when the energy release rate provided by the stressor is not sufficient for crack propagation, expressed as,
K
I
<K
IC,eff,
and outside these spalling and delamination regimes, exfoliation occurs at the graphene interface.
The developed exfoliation criteria (
Graphene nanopatterns were demonstrated as a platform for the epitaxy of single-crystal films, where both elemental and compound semiconductors can be used for the substrates as well as the epilayers. Three modes of peeling—spalling, exfoliation, and delamination—were theoretically proposed and experimentally demonstrated, showing that the grown films could be readily exfoliated with good controllability regardless of the film thickness due to the weak interfaces intentionally formed by graphene stripes. Moreover, APBs completely disappeared when III-V films were grown on elemental substrates with graphene stripes, resulting in high-quality optoelectronics III-V devices that can be made freestanding and transferred onto foreign platforms for heterointegration. Theoretical analysis of dislocation reduction by the dangling-bond-free and ultrathin graphene in lattice-mismatched heteroepitaxy supports the experimental results. Overall, a new pathway was provided for the production of various high-quality and single-crystal membranes, overcoming polarity and lattice-matching constraints which have been a critical obstacle for heterointegrated multifunctional systems.
While several embodiments of the present invention have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the functions and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the present invention. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the teachings of the present invention is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments of the invention described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, the invention may be practiced otherwise than as specifically described and claimed. The present invention is directed to each individual feature, system, article, material, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, and/or methods, if such features, systems, articles, materials, and/or methods are not mutually inconsistent, is included within the scope of the present invention.
The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”
The phrase “and/or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Other elements may optionally be present other than the elements specifically identified by the “and/or” clause, whether related or unrelated to those elements specifically identified unless clearly indicated to the contrary. Thus, as a non-limiting example, a reference to “A and/or B,” when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A without B (optionally including elements other than B); in another embodiment, to B without A (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.
As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and/or” as defined above. For example, when separating items in a list, “or” or “and/or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of” or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e. “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.
As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and/or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.
In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of” and “consisting essentially of” shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.
This invention was made with government support under D19AP00037 awarded by the Defense Advanced Research Projects Agency. The government has certain rights in the invention.
