Claims
- 1. A system for exposing a layer of resist on a target comprising:
- a lithographic system configured to direct exposure energy onto the layer of resist;
- a mask mounted to the lithographic system, said mask comprising a plurality of first pattern segments and a plurality of complementary second pattern segments, said first and second pattern segments formed on the mask in an alternating sequence; and
- a stepper apparatus configured to support the target in the lithographic system and to step the target with respect to the mask through a first stepping distance equal to a width of a pattern segment, and then through a second stepping distance equal to a combined width of multiple pattern segments.
- 2. The system as claimed in claim 1 wherein the target comprises a semiconductor wafer.
- 3. The system as claimed in claim 1 wherein the stepper apparatus comprises a wafer stepper.
- 4. The system as claimed in claim 1 wherein the lithographic system comprises an optical projection aligner.
- 5. The system as claimed in claim 1 wherein the lithographic system comprises a non-optical system.
- 6. A system for exposing a layer of resist on a semiconductor wafer comprising:
- a lithographic system configured to direct exposure energy onto the layer of resist;
- a mask mounted to the lithographic ststem, said mask comprising a plurality of first pattern segments and a plurality of complementary second pattern segments, said first and second pattern segments formed on the mask in an alternating pattern of (c) columns each having a width "W";
- a stepper configured to support the wafer in the lithographic system and to step the wafer with respect to the mask through a first stepping distance equal to the width "W", and then through a second stepping distance equal to (c-1).times.W.
- 7. The system as claimed in claim 6 wherein the mask comprises a transparent substrate with an opaque layer etched to form the first and second pattern segments.
- 8. The system as claimed in claim 6 wherein the first and second pattern segments comprise complementary half patterns.
- 9. The system as claimed in claim 6 wherein the first pattern segments comprise phase shift patterns and the second pattern segments are configured to cut stringers formed by the phase shift patterns.
- 10. The system as claimed in claim 6 wherein the lithographic system comprises a step and repeat optical projection aligner.
- 11. The system as claimed in claim 6 wherein the lithographic system comprises a step and scan optical projection aligner.
- 12. The system as claimed in claim 6 wherein the lithographic system comprises a system selected from the group consisting of x-ray, ion beam and electron beam systems.
- 13. A system for exposing a layer of resist on a semiconductor wafer comprising:
- an ion beam lithographic system including an ion source configured to direct ions onto the layer of resist;
- a stencil mask mounted to the projection aligner, said mask comprising a plurality of first pattern segments and a plurality of complementary second pattern segments, said first and second pattern segments formed on the mask in an alternating pattern of columns and rows; and
- a stepper configured to support the wafer in the lithographic system and to step the wafer with respect to the mask through a first stepping distance equal to a width of a pattern segment, and then through a second stepping distance equal to a combined width of multiple pattern segments.
- 14. The system as claimed in claim 13 wherein the first pattern segments comprise half pattern segments and the second pattern segments comprise complementary half pattern segments.
- 15. The system as claimed in claim 13 wherein the second stepping distance equals (c-1).times.W, wherein c equals a number of the columns and W equals the width.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a division of U.S. patent application Ser. No. 08/916,833 filed on Aug. 22, 1997 U.S. Pat. No. 5,780,188.
US Referenced Citations (5)
Non-Patent Literature Citations (2)
Entry |
"Intelligent design splitting in the stencil mask technology used for electron- and ion-beam lithography", U. Behringer et al., J. Vac. Sci. Technology B 11(6), Nov./Dec. 1993, pp. 2400-2403. |
Wolf, Stanley et at, "Silicon Processing For the VLSI Era", vol. 1, Process Technology, Lattice Press, 1986, pp. 472-483. |
Divisions (1)
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Number |
Date |
Country |
Parent |
916833 |
Aug 1997 |
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