Claims
- 1. A method of processing a semiconductor substrate in a plasma processing chamber having a chamber liner and a liner support within an interior of the plasma processing chamber, the liner support including a flexible wall configured to surround an external surfaces of the chamber liner, the flexible wall being spaced apart from the external surface of the chamber liner, wherein a semiconductor wafer is transferred into the chamber and an exposed surface of the substrate is processed with a high density plasma.
- 2. The method of processing a semiconductor substrate as recited in claim 1, wherein the chamber liner is a ceramic material and the liner support includes an outer support extending between the liner support and a temperature controlled part of the chamber, the outer support being dimensioned to minimize temperature drift of the chamber liner during sequential processing of a batch of semiconductor wafers.
- 3. The method of processing a semiconductor substrate as recited in claim 1, wherein the chamber liner is a ceramic liner which is removed from the chamber and replaced with another ceramic liner after processing a predetermined number of semiconductor wafers.
- 4. The method of processing a semiconductor substrate as recited in claim 1, wherein a heater is thermally connected to the liner support so as to thermally conduct beat from the liner support to the chamber liner.
- 5. The method of processing a semiconductor substrate as recited in claim 1, wherein the flexible wall includes slots which divide the liner support into a plurality of fingers which enable the flexible wall to absorb thermal stresses during processing of the semiconductor wafer.
- 6. The method of processing a semiconductor substrate as recited in claim 1, a baffle ring is in thermal contact with the chamber liner and the liner support, the baffle ring defining a plasma screen around an electrostatic chuck located in a central portion of the chamber during processing of the semiconductor wafer.
- 7. The method of processing a semiconductor substrate as recited in claim 1, wherein the chamber liner has low electrical resistivity and provides an RF path to ground during processing of the semiconductor wafer.
- 8. The method of processing a semiconductor substrate as recited in claim 1, wherein process gas is supplied into the chamber through a gas distribution plate and the semiconductor wafer is supported on an electrostatic chuck.
- 9. The method of processing a semiconductor substrate as recited in claim 1, wherein an RF energy source inductively couples RF energy through a gas distribution plate and generates the high density plasma in the chamber.
- 10. The method of processing a semiconductor substrate as recited in claim 1, wherein the RF energy source comprises a planar antenna.
- 11. The method of processing a semiconductor substrate as recited in claim 1, wherein the liner support further includes an outer support thermally connected to a lower extension of the liner support, the outer support being in thermal contact with a water cooled top plate mounted on the chamber.
- 12. The method of processing a semiconductor substrate as recited in claim 1, wherein the exposed surface is etched with the high density plasma.
- 13. The method of processing a semiconductor substrate as recited in claim 1, wherein a cast heater ring is in thermal contact with the liner support, the heater ring including a resistance heated element which heats the liner support so as to thermally control the temperature of the chamber liner.
Parent Case Info
This application is a divisional of application Ser. No. 09/487,325, filed Jan. 19, 2000, U.S. Pat. No. 6,394,026 which is a continuation of application Ser. No. 09/161,074, filed Sep. 25, 1998, U.S. Pat. No. 6,129,808 which is a Continuation-In-Part of application Ser. No. 09/050,902, filed Mar. 31, 1998, now abandoned.
US Referenced Citations (28)
Foreign Referenced Citations (4)
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Date |
Country |
63273 |
Oct 1982 |
EP |
246238 |
Sep 1997 |
JP |
9814980 |
Apr 1998 |
WO |
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Oct 1999 |
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Non-Patent Literature Citations (2)
Entry |
J. Linke et al., “Behavior of boron-doped graphites, plasma-sprayed B4C, and a C/B:H as plasma-facing materials” Fushion Tech. Sep. 20, 1991 pp. 228-231. |
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Continuations (1)
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Number |
Date |
Country |
Parent |
09/161074 |
Sep 1998 |
US |
Child |
09/487325 |
|
US |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
09/050902 |
Mar 1998 |
US |
Child |
09/161074 |
|
US |